09 Dec, 2018
1 commit
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This merges the CRC16-CCITT headers into u-boot/crc.h to prepare for
rolling CRC16 into the hash infrastructure. Given that CRC8, CRC32
and CRC32-C already have their prototypes in a single header file, it
seems a good idea to also include CRC16-CCITT in the same.Signed-off-by: Philipp Tomsich
04 Dec, 2018
1 commit
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According to SD Specifications Part 1 Physical Layer Simplified Specification
Version 6.00 August 29, 2018, section 4.3.10 (Switch Function Command) and
section 5.6 (SCR register), SD cards version 1.00 and 1.01 do not support the
SD CMD 6.Currently, U-Boot will issue CMD 6 unconditionally in sd_set_card_speed()
while configuring the bus for selected frequency. This will make SD cards
version 1.00 and 1.01 time out and thus fail detection altogether.Fix this by not sending CMD 6 on such cards. Tested on Matsushita Electric
Industrial Co., Ltd. Japan RP-SD008B / Victor 8MB SD card, CU-SD008, which
is correctly detected with this patch as:Device: sd@ee160000
Manufacturer ID: 1
OEM: 5041
Name: S008B
Bus Speed: 25000000
Mode : SD Legacy
Rd Block Len: 512
SD version 1.0
High Capacity: No
Capacity: 6.5 MiB
Bus Width: 4-bit
Erase Group Size: 512 BytesSigned-off-by: Marek Vasut
Cc: Masahiro Yamada
03 Dec, 2018
8 commits
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Add support for the HS400 mode to SDHI driver. This uses the up-tune
mechanism from already supported HS200 tuning.Signed-off-by: Marek Vasut
Cc: Masahiro Yamada -
Move the tap_pos variable, which is the HS200/HS400/SDR104 calibration
offset, into private data, so it can be passed around. This is done in
preparation for the HS400 mode, which needs to adjust this value.Signed-off-by: Marek Vasut
Cc: Masahiro Yamada -
Filter out HS400 support on SoCs where HS400 is not supported yet.
Signed-off-by: Marek Vasut
Cc: Masahiro Yamada -
Reorder the tmio_sd_set_clk_rate() function such that it handles all
of the clock requiests correctly. Specifically, before this patch,
clock request with (mmc->clock == 0 && mmc->clk_disable) could leave
the clock enabled, as the function would exit on if (!mmc->clock)
condition on top and will not handle the mmc->clk_disable at all.Rather than band-aid fixing just that particular problem, reorder
the entire function to make it easier to understand and verify that
all the cases are covered. The function has three sections now:First, if mmc->clock != 0, we calculate divider for the SD block.
Second, if mmc->clock != 0 and SD block clock are enabled and
current divider is not equal to the new divider, then
stop the clock and update the divider.
Third, if mmc->clk_disable is set, disable the clock, otherwise
enable the clock. This happens independently of divider
update now.Signed-off-by: Marek Vasut
Cc: Masahiro Yamada -
The TMIO core has a feature where it can automatically disable clock output
when the bus is not in use. While this is useful, it also interferes with
switching the bus to 1.8V and other background tasks of the SD/MMC cards,
which require clock to be enabled.This patch respects the mmc->clk_disable and only disables the clock when
the MMC core requests it. Otherwise the clock are continuously generated
on the bus.Signed-off-by: Marek Vasut
Cc: Masahiro Yamada -
The TMIO core has a quirk where divider == 1 must not be set in DDR modes.
Handle this by setting divider to 2, as suggested in the documentation.Signed-off-by: Marek Vasut
Cc: Masahiro Yamada -
Switch the driver to using clk_get_rate()/clk_set_rate() instead of
caching the mclk frequency in it's private data. This is required on
the SDHI variant of the controller, where the upstream mclk need to
be adjusted when using UHS modes.Platforms which do not support clock framework or do not support it
in eg. SPL default to 100 MHz clock.Signed-off-by: Marek Vasut
Cc: Masahiro Yamada
---
V2: - Fix build on certain platforms using SPL without clock framework
V3: - Turn clk_get_rate into a callback and fill it as needed on both
renesas and socionext platforms -
Add HS400 properties parsing support to mmc_of_parse().
Signed-off-by: Marek Vasut
Cc: Bin Meng
Cc: Jaehoon Chung
Cc: Jean-Jacques Hiblot
Cc: Kishon Vijay Abraham I
Cc: Peng Fan
Cc: Simon Glass
30 Nov, 2018
1 commit
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Cleanup and update towards support for Amlogic Meson AXG SoCs :
- mmc: meson-gx: Add AXG compatible
- net: designware: add meson meson compatibles
- Amlogic Meson cleanup for AXG SoC support
29 Nov, 2018
1 commit
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This patch adds MT7623 host controller driver for accessing SD/MMC.
Cc: Jaehoon Chung
Signed-off-by: Weijie Gao
Signed-off-by: Ryder Lee
Tested-by: Matthias Brugger
Reviewed-by: Simon Glass
26 Nov, 2018
1 commit
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Add the compatible string for the upcoming Amlogic AXG SoC family.
Signed-off-by: Neil Armstrong
22 Nov, 2018
3 commits
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Using new mode improves stability of eMMC and SD cards. Without
it SPL fails to load u-boot from SD on Pinebook.Signed-off-by: Vasily Khoruzhick
Reviewed-by: Chen-Yu Tsai
Tested-by: Jagan Teki # Amarula A64-Relic
Reviewed-by: Jagan Teki -
Comment in Linux driver says that clock needs to be doubled only
if we use DDR modes, moreover divider has to be set accordingly.U-boot driver doesn't declare support for any DDR modes and doesn't
set internal clock divider in CLKCR, so it doubles clock
unconditionally when new mode is used.Some cards can't handle that and as result SPL fails to load u-boot.
Fixes: de9b1771c3b ("mmc: sunxi: Support new mode")
Signed-off-by: Vasily Khoruzhick
Reviewed-by: Jagan Teki
Tested-by: Jagan Teki # Amarula A64-Relic -
Allwinner A64 has new mode but doesn't have a mode switch in CCM,
and CCM_MMC_CTRL_MODE_SEL_NEW is not defined, so compilation fails
if MMC_SUNXI_HAS_NEW_MODE is enabledIntroduce new MMC_SUNXI_HAS_MODE_SWITCH option to be able to ifdef usage
of CCM_MMC_CTRL_MODE_SEL_NEWSigned-off-by: Vasily Khoruzhick
Reviewed-by: Jagan Teki
[jagan: update commit message]
Signed-off-by: Jagan Teki
Tested-by: Jagan Teki # Amarula A64-Relic
16 Nov, 2018
1 commit
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- virtio implementation and supporting patches
- DM_FLAG_PRE_RELOC fixes
- regmap improvements
- minor buildman and sandbox things
15 Nov, 2018
3 commits
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When a driver declares DM_FLAG_PRE_RELOC flag, it wishes to be
bound before relocation. However due to a bug in the DM core,
the flag only takes effect when devices are statically declared
via U_BOOT_DEVICE(). This bug has been fixed recently by commit
"dm: core: Respect drivers with the DM_FLAG_PRE_RELOC flag in
lists_bind_fdt()", but with the fix, it has a side effect that
all existing drivers that declared DM_FLAG_PRE_RELOC flag will
be bound before relocation now. This may expose potential boot
failure on some boards due to insufficient memory during the
pre-relocation stage.To mitigate this potential impact, the following changes are
implemented:- Remove DM_FLAG_PRE_RELOC flag in the driver, if the driver
only supports configuration from device tree (OF_CONTROL)
- Keep DM_FLAG_PRE_RELOC flag in the driver only if the device
is statically declared via U_BOOT_DEVICE()
- Surround DM_FLAG_PRE_RELOC flag with OF_CONTROL check, for
drivers that support both statically declared devices and
configuration from device treeSigned-off-by: Bin Meng
Reviewed-by: Simon Glass -
part_init() is currently called in every DM BLK driver, either
in its bind() or probe() method. However we can use the BLK
uclass driver's post_probe() method to do it automatically.Update all DM BLK drivers to adopt this change.
Signed-off-by: Bin Meng
Reviewed-by: Simon Glass
14 Nov, 2018
1 commit
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A64 and H6 support automatic delay calibration and Linux driver uses it
instead of hardcoded delays. Add support for it to u-boot driver.Fixes eMMC instability on Pinebook
Signed-off-by: Vasily Khoruzhick
Acked-by: Maxime Ripard
Tested-by: Maxime Ripard
Reviewed-by: Andre Przywara
Cc: Vagrant Cascadian
Reviewed-by: Jagan Teki
10 Nov, 2018
1 commit
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This patch adds check for command response CRC failure. The driver
is currently ignoring CRC check failure on command resposes which
have CRC atteched to it, which can be potentially dangerous. Even
more grueling problem happens when the command response is followed
by data transfer though, as in that case, the dwmci_data_transfer()
function will spin until it reaches the 240s timeout.Signed-off-by: Marek Vasut
Cc: Heiko Stuebner
Cc: Philipp Tomsich
02 Nov, 2018
9 commits
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It is perfectly fine to write th DTCNTL TAP count and enable the
SCC sampling clock operation in the same write.Signed-off-by: Marek Vasut
Cc: Masahiro Yamada -
When the bus switches to 1.8V mode of operation, it is necessary to
verify that the card correctly initiated and completed the voltage
switch. This is done by reading out the state of DATA0 line.This patch implement support for reading out the state of the DATA0
line, so the MMC core code can correctly switch to 1.8V mode.Signed-off-by: Marek Vasut
Cc: Masahiro Yamada -
Make sure to clear HS400 configuration when resetting the SCC block.
Signed-off-by: Marek Vasut
Cc: Masahiro Yamada -
Add check to avoid touching the SCC tuning registers in case the IP
doesn't support them or if the support isn't in place yet.Signed-off-by: Marek Vasut
Cc: Masahiro Yamada -
Preinitialize the SD card signals regulator to 3.3V, which is the
default post-reset setting, to be sure the regulator is set to a
valid value.Signed-off-by: Marek Vasut
Cc: Masahiro Yamada -
Configure the clock settings before reconfiguring any other IO settings.
This is required when the clock must be stopped before changing eg. the
pin configuration or any of the other properties of the bus. Running the
clock configuration first allows the MMC core to do just that.Signed-off-by: Marek Vasut
Cc: Masahiro Yamada -
In case the controller performs card tuning, that is, sends MMC
command 19 or 21, silence possible CRC error warning prints. The
warnings are bound to happen, since the tuning will fail for some
settings while searching for the optimal configuration of the bus
and that is perfectly OK.This patch passes around the MMC command structure and adds check
into tmio_sd_check_error() to avoid printing CRC error warning
when the tuning happens.Signed-off-by: Marek Vasut
Cc: Masahiro Yamada -
Properly handle return values and abort operations when they are
non-zero. This is a minor improvement, which fixes two remaining
unchecked return values.Signed-off-by: Marek Vasut
Cc: Masahiro Yamada -
The SD UHS SDR12, SDR25, SDR50, SDR104, DDR50 and MMC HS200, HS400
modes all use 1.8V signaling, while all the legacy modes use 3.3V
signaling. While there are extra modes which use 1.2V signaling,
the existing hardware does not support those.Simplify the pinmux such that 3.3V signaling implies legacy mode
pinmux and the rest implies UHS mode pinmux. This prevents the
massive case statement from growing further. Moreover, it fixes
an edge case where during SD 1.8V switch, the bus mode is still
set to default while the signaling is already set to 1.8V, which
results in an attempt to communicate with a 1.8V card using pins
in 3.3V mode and thus communication failure.Signed-off-by: Marek Vasut
Cc: Masahiro Yamada
25 Oct, 2018
1 commit
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Merged imx8 architecture, fix build for imx8 + warnings
22 Oct, 2018
2 commits
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When CONIFG_CLK is enabled, use uclass clk api to handle
the clock.Signed-off-by: Peng Fan
Reviewed-by: Anatolij Gustschin
Cc: Jaehoon Chung
Cc: Stefano Babic -
Add CONFIG_ARCH_IMX8 to use the 64bits support in usdhc driver.
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
Reviewed-by: Anatolij Gustschin
Cc: Jaehoon Chung
16 Oct, 2018
1 commit
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Xilinx is introducing Versal, an adaptive compute acceleration platform
(ACAP), built on 7nm FinFET process technology. Versal ACAPs combine
Scalar Processing Engines, Adaptable Hardware Engines, and Intelligent
Engines with leading-edge memory and interfacing technologies to deliver
powerful heterogeneous acceleration for any application. The Versal AI
Core series has five devices, offering 128 to 400 AI Engines. The series
includes dual-core Arm Cortex™-A72 application processors, dual-core Arm
Cortex-R5 real-time processors, 256KB of on-chip memory with ECC, more
than 1,900 DSP engines optimized for high-precision floating point with
low latency.The patch is adding necessary infrastructure in place without enabling
platform which is done in separate patch.Signed-off-by: Michal Simek
09 Oct, 2018
2 commits
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The internal DMAC on Gen3 is 32bit only, limit the DMA address
range to 32bit.Signed-off-by: Marek Vasut
Cc: Masahiro Yamada -
Pass the entire source data pointer to tmio_sd_addr_is_dmaable()
so we don't have to apply casts throughout the code.Signed-off-by: Marek Vasut
Cc: Masahiro Yamada
07 Oct, 2018
1 commit
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Adds mmc_rpmb_route_frames() to route RPMB data frames from/to an
external entity.Tested-by: Igor Opaniuk
Signed-off-by: Jens Wiklander
Reviewed-by: Simon Glass
02 Oct, 2018
2 commits
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The rk3188 works nicely with the rockchip mmc driver, so we just need
to add the different compatible for it - as used in the Linux kernel.Signed-off-by: Heiko Stuebner
Reviewed-by: Philipp Tomsich
Acked-by: Philipp Tomsich -
While trying to enable the dw_mmc on rk3188 I managed to confuse
and hang the dw_mmc controller into not delivering further data.
The fifo state never became ready and the driver was iterating in
the while loop reading 0-byte packets forever.So inspired by how other implementations handle this, check the fifo-
state beforhand and add a timeout to catch any glaring fifo issues
without hanging uboot altogether.Signed-off-by: Heiko Stuebner
Reviewed-by: Philipp Tomsich
Acked-by: Philipp Tomsich
