06 Dec, 2018
1 commit
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- Various MTD fixes from Boris
- Zap various unused / legacy paths.
- pxa3xx NAND update from MiquelSigned-off-by: Tom Rini
03 Dec, 2018
1 commit
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Signed-off-by: Christophe Leroy
29 Nov, 2018
1 commit
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Linux uses "cdns,qspi-nor" as compatible string for the cadence
qspi driver, so change driver, docs and all device trees.Signed-off-by: Simon Goldschmidt
27 Nov, 2018
5 commits
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Drop non-dm code and migrate into DM_SPI.
Signed-off-by: Christophe Leroy
[jagan: Move config menu in DM_SPI area]
Signed-off-by: Jagan Teki -
Remove spi_init definition which never used on
respective code since from many years.Signed-off-by: Jagan Teki
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Rename platform_data include file as spi_pl022.h from pl022_spi.h,
this is generic notation used for spi platdata include files.Acked-by: Quentin Schulz
Signed-off-by: Jagan Teki -
This patch can drop unnecessary include files in
pl022_spi driver.Acked-by: Quentin Schulz
Signed-off-by: Jagan Teki -
pl022 spi driver support both OF_CONTROL and PLATDATA, this
patch is trying to simplify the code that differentiating
platdata vs of_control.
- Move OF_CONTROL code at one place
- Handle clock setup code directly in pl022_spi_ofdata_to_platdataAcked-by: Quentin Schulz
Signed-off-by: Jagan Teki
24 Nov, 2018
2 commits
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This patch adds MT7629 qspi driver for accessing SPI NOR flash.
Signed-off-by: Guochun Mao
Reviewed-by: Simon Glass
Reviewed-by: Jagan Teki -
The Amlogic Meson SoCs embeds a Flash oriented SPI Controller name SPIFC.
This driver, ported from the Linux meson-spi-spifc driver, add support
for this controller on the Amlogic Meson GX SoCs in U-Boot.Tested-by: Jerome Brunet
Reviewed-by: Jagan Teki
Signed-off-by: Neil Armstrong
21 Nov, 2018
1 commit
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When the device tree is missing a correct spi slave description below
the bus (compatible "spi-flash" or spi-max-frequency are missing),
the 'set_speed' callback can be called with 'speed' == 0 Hz.
At least with cadence qspi, this leads to a division by zero.Prevent this by initializing speed to 100 kHz in this case (same
fallback value as is done in 'dm_spi_claim_bus') and issue a warning
to console.Signed-off-by: Simon Goldschmidt
Reviewed-by: Simon Glass
16 Oct, 2018
1 commit
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Xilinx is introducing Versal, an adaptive compute acceleration platform
(ACAP), built on 7nm FinFET process technology. Versal ACAPs combine
Scalar Processing Engines, Adaptable Hardware Engines, and Intelligent
Engines with leading-edge memory and interfacing technologies to deliver
powerful heterogeneous acceleration for any application. The Versal AI
Core series has five devices, offering 128 to 400 AI Engines. The series
includes dual-core Arm Cortex™-A72 application processors, dual-core Arm
Cortex-R5 real-time processors, 256KB of on-chip memory with ECC, more
than 1,900 DSP engines optimized for high-precision floating point with
low latency.The patch is adding necessary infrastructure in place without enabling
platform which is done in separate patch.Signed-off-by: Michal Simek
12 Oct, 2018
1 commit
10 Oct, 2018
1 commit
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Davanci spi driver has DM support already, this patch
add support for platdata so-that SPL can use it for
low foot-print.Signed-off-by: Jagan Teki
Tested-by: Adam Ford
09 Oct, 2018
2 commits
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When SPI flash operations fail it is helpful to be able to see the error
codes and where they are generated. Add logging to capture this
information for read operations.Signed-off-by: Simon Glass
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Add logging to aid debugging features in these drivers. Also drop some
code in sandbox_spi_xfer() which is not used.Signed-off-by: Simon Glass
04 Oct, 2018
1 commit
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This patch adds the SPI driver for the MediaTek MT7688 SoC (and
derivates). Its been tested on the LinkIt Smart 7688 and the Gardena
Smart Gateway with and SPI NOR on CS0 and on the Gardena Smart
Gateway additionally with an SPI NAND on CS1.Note that the SPI controller only supports a max transfer size of 32
bytes. This driver implementes a workaround to enable bigger xfer
sizes to speed up the transfer especially for the SPI NAND support.Signed-off-by: Stefan Roese
Cc: Jagan Teki
Cc: Daniel Schwierzeck
Cc: Piotr Dymacz
Reviewed-by: Jagan Teki
Reviewed-by: Daniel Schwierzeck
03 Oct, 2018
4 commits
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This is the PR for SPI-NAND changes along with few spi changes.
[trini: Re-sync changes for ls1012afrwy_qspi*_defconfig]
Signed-off-by: Tom Rini -
Add DM support to the SH QSPI driver while retaining non-DM support.
The later is required as this driver is used in SPL which has a size
limitation of 16 kiB.Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
[jagan: use proper commit head]
Reviewed-by: Jagan Teki -
Convert fsl_qspi.c to complete DM mode.
Signed-off-by: Ashish Kumar
Tested-by: Rajat Srivastava
Tested-by: Ye Li
Reviewed-by: Jagan Teki -
Add code to reset all reset signals as in SPI DT node. A reset property
is an optional feature, so only print out a warning and do not fail if a
reset property is not present.If a reset property is discovered, then use it to deassert, thus
bringing the IP out of reset.Release reset when _remove().
Signed-off-by: Ley Foon Tan
Acked-by: Marek Vasut
Reviewed-by: Jagan Teki
26 Sep, 2018
1 commit
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This adds support for the ARM PL022 SPI controller for the standard
variant (0x00041022) which has a 16bit wide and 8 locations deep TX/RX
FIFO.A few parts were borrowed from the Linux kernel driver.
Cc: Armando Visconti
Cc: Vipin Kumar
Signed-off-by: Quentin Schulz
20 Sep, 2018
1 commit
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Some controllers are exposing high-level interfaces to access various
kind of SPI memories. Unfortunately they do not fit in the current
spi_controller model and usually have drivers placed in
drivers/mtd/spi-nor which are only supporting SPI NORs and not SPI
memories in general.This is an attempt at defining a SPI memory interface which works for
all kinds of SPI memories (NORs, NANDs, SRAMs).Signed-off-by: Boris Brezillon
Signed-off-by: Miquel Raynal
Acked-by: Jagan Teki
03 Aug, 2018
3 commits
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Add spi driver for sun4i, sun5i and sun7i SoCs. The driver is
adapted from mailine kernel.Signed-off-by: Stefan Mavrodiev
Reviewed-by: Jagan Teki -
This matches the compatible string used by the Linux kernel. This will
allow u-boot to use the same device tree files.Signed-off-by: Chris Packham
Reviewed-by: Jagan Teki
[jagan: use armada instead of orion on .data]
Signed-off-by: Jagan Teki -
Get the is_errata_50mhz_ac in .ofdata_to_platdata, and
reuse it in .set_mode this can eventually initialized
dt code at once and adding room to add platdata.Signed-off-by: Jagan Teki
24 Jul, 2018
2 commits
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This patch solves quad read issue with Macronix/Micron spi nor.
Signed-off-by: Christophe Kerello
Signed-off-by: Patrice Chotard -
This patch assigns the functional operation mode in _stm32_qspi_gen_ccr
function.Signed-off-by: Christophe Kerello
Signed-off-by: Patrice Chotard
16 Jul, 2018
5 commits
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This patch adds qspi driver support for ZynqMP SoC. This
driver is responsible for communicating with qspi flash
devices.Signed-off-by: Siva Durga Prasad Paladugu
[jagan: removed GQSPI_MIO_NUM_ macros]
Reviewed-by: Jagan Teki -
Update the xilinx spi driver to support a live tree.
Signed-off-by: Vipul Kumar
Reviewed-by: Jagan Teki -
This patch is for the startup block issue in the spi controller.
SPI clock is passing through STARTUP block to FLASH. STARTUP block
don't provide clock as soon as QSPI provides command. So, first
command fails.This patch added support to read JEDEC id in xilinx_spi_xfer ().
Signed-off-by: Vipul Kumar
Reviewed-by: Jagan Teki -
This patch modify xilinx_spi_xfer() function and add rxfifo() and
txfifo() functions to add the modularity so that these functions
can be used by other functions within the same file.This patch also added support to read fifo_size from dts.
Signed-off-by: Vipul Kumar
Signed-off-by: Siva Durga Prasad Paladugu
Reviewed-by: Jagan Teki -
This patch added support to read register base address from DTS file.
Signed-off-by: Michal Simek
Signed-off-by: Vipul Kumar
Reviewed-by: Jagan Teki
12 Jul, 2018
2 commits
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Use "%p" to print cmdbuf.
Compilation warning as below:
CC spl/drivers/spi/cadence_qspi_apb.o
LD spl/lib/built-in.o
drivers/spi/cadence_qspi_apb.c: In function ‘cadence_qspi_apb_indirect_write_setup’:
drivers/spi/cadence_qspi_apb.c:696:18: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
cmdlen, (unsigned int)cmdbuf);Signed-off-by: Ley Foon Tan
Acked-by: Marek Vasut -
Use "%zu" for size_t data type.
Compilation warning as below:
In file included from include/linux/bug.h:7:0,
from include/common.h:26,
from drivers/spi/cadence_qspi.c:8:
drivers/spi/cadence_qspi.c: In function ‘cadence_spi_xfer’:
drivers/spi/cadence_qspi.c:211:8: warning: format ‘%d’ expects argument of type ‘int’, but argument 3 has type ‘size_t {aka long unsigned int}’ [-Wformat=]
debug("%s: len=%d [bytes]\n", __func__, data_bytes);
^
include/linux/printk.h:37:21: note: in definition of macro ‘pr_fmt’
#define pr_fmt(fmt) fmt
^~~
include/log.h:142:2: note: in expansion of macro ‘debug_cond’
debug_cond(_DEBUG, fmt, ##args)
^~~~~~~~~~
drivers/spi/cadence_qspi.c:211:2: note: in expansion of macro ‘debug’
debug("%s: len=%d [bytes]\n", __func__, data_bytes);Signed-off-by: Ley Foon Tan
Acked-by: Marek Vasut
11 Jul, 2018
1 commit
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Add support for loading U-Boot on the Broadcom 7445 SoC. This port
assumes Broadcom's BOLT bootloader is acting as the second stage
bootloader, and U-Boot is acting as the third stage bootloader, loaded
as an ELF program by BOLT.Signed-off-by: Thomas Fitzsimmons
Cc: Stefan Roese
Cc: Tom Rini
Cc: Florian Fainelli
28 Jun, 2018
1 commit
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The claim/release bus function must not reset the whole SPI core because
settings regarding wordlen, clock-frequency and so on made by
set_wordlen, set_mode, set_speed get lost with this action. Resulting in
a non-functional SPI.Without DM the failure didn't came up since after the spi_reset within
claim bus all the setup (wordlen, mode, ...) was called, in DM they are
called by the spi uclass.We change now the things as following for having a working SPI instance
in DM:- move the spi_reset(...) to the probe call in DM for having a known
hardware state after probe. Without DM we don't have a probe call, so we
issue the reset as before during the claim_bus call.- in release bus we just reset the modulctrl to the reset-value (spi-
slave)Signed-off-by: Hannes Schmelzer
Reviewed-by: Jagan Teki
25 Jun, 2018
3 commits
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commit 84807922874e03895bbf15c4472a2dcee8fbbd03
("spi: omap3: Skip set_mode, set_speed from claim") did break SPI
support on my AM335x board.The named commit:
- ignored the responsible arguments (speed, mode)
The set speed/mode function must use the supplied function arguments to
work properly. With this commit we take those arguments and transfer
them to the priv-data.- used wrong udevice pointer for getting priv data
the udevice-pointer within function argument is already the spi-bus
device, so it is wrong looking here for some parent (ocp-bus in this
case) and getting priv-pointer from there.Signed-off-by: Hannes Schmelzer
Reviewed-by: Jagan Teki -
Otherwise the frequency is zero and the clock divider cannot be setup by
'omap3_spi_set_speed' function.Signed-off-by: Hannes Schmelzer
Reviewed-by: Jagan Teki -
CS GPIO activation low/high is determinated by the device tree
so we don't need to take in accoung in cs_activate and cs_deactivateSigned-off-by: Michael Trimarchi
Reviewed-by: Peng Fan
Reviewed-by: Jagan Teki
