03 Dec, 2018
14 commits
-
Enable the HS400 support code on H3, M3W, M3N Salvator-X(S)
and ULCB boards as well as E3 Ebisu board.Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu -
Enable the HS400 support in DT on H3, M3W, M3N Salvator-X(S)
and ULCB boards as well as E3 Ebisu board.Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu -
Add regulators and pinmuxes for SDHI0 and SDHI1 SD and microSD
slots on E3 Ebisu and mark them as capable of up to SDR104 mode
of operation. With the SDHI fixes in place, it is now possible
to use SDR104.Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu -
Enable SDR104 modes on M3W and H3 boards. With the SDHI fixes
in place, it is now possible to use SDR104.Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu -
Add pinmux entry for the eMMC DS line, as it is connected on these boards.
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu -
Add support for the HS400 mode to SDHI driver. This uses the up-tune
mechanism from already supported HS200 tuning.Signed-off-by: Marek Vasut
Cc: Masahiro Yamada -
Move the tap_pos variable, which is the HS200/HS400/SDR104 calibration
offset, into private data, so it can be passed around. This is done in
preparation for the HS400 mode, which needs to adjust this value.Signed-off-by: Marek Vasut
Cc: Masahiro Yamada -
Filter out HS400 support on SoCs where HS400 is not supported yet.
Signed-off-by: Marek Vasut
Cc: Masahiro Yamada -
Reorder the tmio_sd_set_clk_rate() function such that it handles all
of the clock requiests correctly. Specifically, before this patch,
clock request with (mmc->clock == 0 && mmc->clk_disable) could leave
the clock enabled, as the function would exit on if (!mmc->clock)
condition on top and will not handle the mmc->clk_disable at all.Rather than band-aid fixing just that particular problem, reorder
the entire function to make it easier to understand and verify that
all the cases are covered. The function has three sections now:First, if mmc->clock != 0, we calculate divider for the SD block.
Second, if mmc->clock != 0 and SD block clock are enabled and
current divider is not equal to the new divider, then
stop the clock and update the divider.
Third, if mmc->clk_disable is set, disable the clock, otherwise
enable the clock. This happens independently of divider
update now.Signed-off-by: Marek Vasut
Cc: Masahiro Yamada -
The TMIO core has a feature where it can automatically disable clock output
when the bus is not in use. While this is useful, it also interferes with
switching the bus to 1.8V and other background tasks of the SD/MMC cards,
which require clock to be enabled.This patch respects the mmc->clk_disable and only disables the clock when
the MMC core requests it. Otherwise the clock are continuously generated
on the bus.Signed-off-by: Marek Vasut
Cc: Masahiro Yamada -
The TMIO core has a quirk where divider == 1 must not be set in DDR modes.
Handle this by setting divider to 2, as suggested in the documentation.Signed-off-by: Marek Vasut
Cc: Masahiro Yamada -
Switch the driver to using clk_get_rate()/clk_set_rate() instead of
caching the mclk frequency in it's private data. This is required on
the SDHI variant of the controller, where the upstream mclk need to
be adjusted when using UHS modes.Platforms which do not support clock framework or do not support it
in eg. SPL default to 100 MHz clock.Signed-off-by: Marek Vasut
Cc: Masahiro Yamada
---
V2: - Fix build on certain platforms using SPL without clock framework
V3: - Turn clk_get_rate into a callback and fill it as needed on both
renesas and socionext platforms -
Add HS400 properties parsing support to mmc_of_parse().
Signed-off-by: Marek Vasut
Cc: Bin Meng
Cc: Jaehoon Chung
Cc: Jean-Jacques Hiblot
Cc: Kishon Vijay Abraham I
Cc: Peng Fan
Cc: Simon Glass -
The SDHI clock must be configured differently for HS200/HS400/SDR104
modes. Add support for reconfiguring the SDHI clock settings into the
clock driver.Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
02 Dec, 2018
2 commits
-
Variable 'days' must be defined as signed int. Otherwise the conversion
fails for some dates, e.g. 2004-08-25. Cf function rtc_time64_to_tm() in
the Linux kernel source.Fixes: 992c1db45591 "drivers: rtc: resolve year 2038 problem in rtc_to_tm"
Signed-off-by: Heinrich Schuchardt -
Improvements:
- RK3188 USB-UART functionality
- errors triggering a hard-stop in SPL on the RK3399 are reported
- Rockchip RV1108 (SoC) support
- MicroCrystal RV3029 (RTC) DM driverFixes:
- RK3188 early UART setup
- limit SD-card frequency to 40MHz on the RK3399-Q7
- MIPI fixes
- RK3399 CPUB clock initialisation
01 Dec, 2018
23 commits
-
Fix sound on sandbox
Convert TPM fully to DM
Tidy up sandbox I2C emulation
Add a 'make qcheck' target for faster testing
A few other misc things
(dropped the final patch which breaks clang for some reason) -
- MIPS: MT76xx: minor fixes and updates to gardena-smart-gateway board
-
Sync with other rockchip SoCs, use board_debug_uart_init() to
init default UART iomux.Signed-off-by: Kever Yang
Reviewed-by: Philipp Tomsich -
This patch sets the PLL of CPU cluster B (BPLL) to 600 MHz.
This decreases the boot time of Linux 4.19 by about 8%.The 600 MHz are inspired by the 600 MHz used for LPLL initialization
(came in with commit 9f636a249c1).Tested on RK3399-Q7 on Haikou base board.
Signed-off-by: Christoph Muellner
Reviewed-by: Philipp Tomsich -
The "Flamingo" carrier-board for the RK3399-Q7 has a RV3029 populated
and the application will use the off-module RV3029 RTC including the
battery backed SRAM.To support this use case, this commit includes the following changes:
* updates the rv3029 driver to use DM
* implements the read8/write8 operationsThis syncs the implementation with the Linux code (based on 4.17),
porting the trickle-charger support from there (with improvements to
avoid unnecessary EEPROM updates) and adheres to the Linux DTS
binding.Signed-off-by: Philipp Tomsich
Tested-by: Klaus Goger -
The MicroCrystal RV3029 driver didn't have a Kconfig entry and was not used
anywhere. Add it to Kconfig to make it selectable.Signed-off-by: Philipp Tomsich
Tested-by: Klaus Goger -
This allow easier integration of RV1108 based boards on generic
distributions and build systems.To avoid behavior change, we make evb-rv1108 to use the existing
environment as it boots from its SPI NOR.Signed-off-by: Otavio Salvador
Reviewed-by: Philipp Tomsich -
This adds the definitions need to use the USB OTG in rv1108
board. This has been tested using USB Mass Storage to export and
program a eMMC device.Signed-off-by: Otavio Salvador
Reviewed-by: Philipp Tomsich -
Like it is done for other Rockchip SoCs, introduce a board_usb_init()
function so that USB OTG can be functional on rv1108 too.Signed-off-by: Otavio Salvador
Reviewed-by: Philipp Tomsich -
This adds the pinctrl handles to enable the use of eMMC on custom
boards (as minievk) and makes it easier for later addition.Signed-off-by: Otavio Salvador
Reviewed-by: Philipp Tomsich -
In order to be able to build the Rockchip eMMC driver on rv1108, the
BOUNCE_BUFFER option needs to be selected. Select it like it is done
on the other Rockchip SoC common files.Reviewed-by: Andy Yan
Signed-off-by: Otavio Salvador
Reviewed-by: Philipp Tomsich -
Make adjustments to the rv1108 clock driver in order to align it
with the internal Rockchip version.Signed-off-by: Otavio Salvador
Reviewed-by: Philipp Tomsich -
Some SanDisk Ultra cards trigger intermittent errors on detection
resulting in an -EOPNOTSUPP, when running at 50MHz.Waveform analysis suggest that the level shifters that are used on the
RK3399-Q7 module (for voltage translation between the on-module
voltages and the 3.3V required on the card-edge) don't handle clock
rates at or above 48MHz properly. This change reduces the maximum
frequency on the external SD-interface to 40MHz (for a safety margin
of 20%).Reported-by: Jakob Unterwurzacher
Signed-off-by: Philipp Tomsich
Tested-by: Christoph Muellner -
The RK3188 rock board does not need TPL: remove TPL_TINY_MEMSET from
config.Signed-off-by: Kever Yang
Reviewed-by: Philipp Tomsich
[Fixed up commit message:]
Signed-off-by: Philipp Tomsich -
The RK3399 SPL has two cases that may end in a hard-stop: if either
the pinctrl can not be initialised or if the DRAM fails to initialise.
Both have previously not triggered an error message unless DEBUG was
defined (i.e. both used debug() to print the error).This converts both error messages to be printed using pr_err() to
ensure that some output points to the cause of the hard-stop.Signed-off-by: Philipp Tomsich
-
There was an incorrect check when looping and finding the first
fast enough frequency in the freq_rang table. The code did
actually return the first that was either exactly correct or
too slow.Signed-off-by: Richard Röjfors
Reviewed-by: Philipp Tomsich -
There was a copy and paste error where the data
enable setting was written to the version register.Signed-off-by: Richard Röjfors
Reviewed-by: Philipp Tomsich -
Commit 7a6d7d3e1279 ("rockchip: pinctrl: rk3188: Move the iomux definitions
into pinctrl-driver") moved the iomux settings out of the grf header
to prevent conflicts with the iomux definitions of other rockchip socs.This also breaks the early uart setup, as the iomux for uart2 are needed.
To fix that just put the tiny amount of needed iomux definitions next to
the early uart code.Fixes: 7a6d7d3e1279 ("rockchip: pinctrl: rk3188: Move the iomux definitions into pinctrl-driver")
Signed-off-by: Heiko Stuebner
Reviewed-by: Philipp Tomsich -
Rockchip socs can route the debug uart pins through the d+ and d- pins
of one specific usbphy per soc. Add a config option and implement the
setting on the rk3188.Signed-off-by: Heiko Stuebner
Reviewed-by: Philipp Tomsich
[Fixed up to mark grf as maybe unused:]
Signed-off-by: Philipp Tomsich -
Some factory data is stored in the SPI NOR and needs to get extracted
from there into U-Boot environment variables.This patch also includes a board-specific command "fd_write" to
provide some dummy / default values for this factory-data in the SPI
NOR flash. This should only be necessary for testing purposes though.Signed-off-by: Stefan Roese
Cc: Daniel Schwierzeck -
The following changes are made:
- Add default bootcmd which can be used for initial start-up
- Setup necessary MTD parts for Linux compatibilitySigned-off-by: Stefan Roese
Cc: Daniel Schwierzeck -
As the driver has been changed to be more specific, the DT compatible
property also needs to be adapted.Signed-off-by: Stefan Roese
Cc: Daniel Schwierzeck -
- Some Kirkwood boards converted to DM_SPI by Chris
- New Armada-385 SoC revision printed by Chris
- Ethernet enable on mcbin by Baruch
- Support 2 DRAM banks on Armada-8k boards by Baruch
30 Nov, 2018
1 commit
-
Marvell have release a B0 revision of the Armada-385 SoC. This fixes a
hardware errata enabling RGMII to work when the Ethernet voltage is
configured to 3.3V.Signed-off-by: Chris Packham
Reviewed-by: Stefan Roese
Signed-off-by: Stefan Roese
