Eric Lee / smarc-uboot

13 Sep, 2008

2 commits

  • 8f42bf1c3   fsl_elbc_nand: implement support for flash-based BBT ... Browse Code »

    This patch implements support for flash-based BBT for chips working
    through ELBC NAND controller, so that NAND core will not have to re-scan
    for bad blocks on every boot.

    Because ELBC controller may provide HW-generated ECCs we should adjust
    bbt pattern and bbt version positions in the OOB free area.

    Signed-off-by: Anton Vorontsov
    Signed-off-by: David Woodhouse
    Signed-off-by: Scott Wood

    Anton Vorontsov
     
  • 97ae02364   fsl_elbc_nand: fix OOB workability for large page NAND chips ... Browse Code »

    For large page chips, nand_bbt is looking into OOB area, and checking
    for "0xff 0xff" pattern at OOB offset 0. That is, two bytes should be
    reserved for bbt means.

    But ELBC driver is specifying ecclayout so that oobfree area starts at
    offset 1, so only one byte left for the bbt purposes.

    This causes problems with any OOB users, namely JFFS2: after first mount
    JFFS2 will fill all OOBs with "erased marker", so OOBs will contain:

    OOB Data: ff 19 85 20 03 00 ff ff ff 00 00 08 ff ff ff ff
    OOB Data: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
    OOB Data: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
    OOB Data: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff

    And on the next boot, NAND core will rescan for bad blocks, then will
    see "0xff 0x19" pattern, and will mark all blocks as bad ones.

    To fix the issue we should implement our own bad block pattern: just one
    byte at OOB start. Though, this will work only for x8 chips. For x16
    chips two bytes must be checked. Since ELBC driver does not support x16
    NANDs (yet), we're safe for now.

    Signed-off-by: Anton Vorontsov
    Signed-off-by: David Woodhouse
    Signed-off-by: Scott Wood

    Anton Vorontsov
     

11 Sep, 2008

2 commits

  • 6644641d0   delta, zylonite: Update nand_oobinfo to nand_ecclayout. ... Browse Code »

    This is part of the switch to newer upstream MTD code.

    Signed-off-by: Scott Wood

    Scott Wood
     
  • 9b05aa788   ARM DaVinci: Fix broken HW ECC for large page NAND. ... Browse Code »

    Based on original patch by Bernard Blackham

    U-boot's HW ECC support for large page NAND on Davinci is completely
    broken. Some kernels, such as the 2.6.10 one supported by
    MontaVista for DaVinci, rely upon this broken behaviour as they
    share the same code for ECCs. In the existing scheme, error
    detection *might* work on large page, but error correction
    definitely does not. Small page ECC correction works, but the
    format is not compatible with the mainline git kernel.

    This patch adds ECC code that matches what is currently in the
    Davinci git repository (since NAND support was added in 2.6.24).
    This makes the ECC and OOB layout written by u-boot compatible with
    Linux for both small page and large page devices and fixes ECC
    correction for large page devices.

    The old behaviour can be restored by defining the macro
    CFG_DAVINCI_BROKEN_ECC, which is undefined by default.

    Signed-off-by: Hugo Villeneuve
    Acked-by: Sergey Kubushyn
    Signed-off-by: Scott Wood

    Hugo Villeneuve
     

10 Sep, 2008

18 commits

09 Sep, 2008

18 commits