22 Sep, 2017
14 commits
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This patch adds the support of reset and clock control
block (rcc) found on STM32 SoCs.
This driver is similar to a MFD linux driver.This driver supports currently STM32H7 only.
STM32F4 and STM32F7 will be migrated to this rcc MFD driver
in the future to uniformize all STM32 SoCs already upstreamed.Signed-off-by: Christophe Kerello
Signed-off-by: Patrice Chotard
Reviewed-by: Vikas Manocha
Reviewed-by: Simon Glass -
This driver is adapted from linux drivers/reset/reset-stm32.c
It's compatible with STM32 F4/F7/H7 SoCs.This driver doesn't implement .of_match as it's binded
by MFD RCC driver.To add support for each SoC family, a SoC's specific
include/dt-binfings/mfd/stm32xx-rcc.h file must be added.This patch only includes stm32h7-rcc.h dedicated for STM32H7 SoCs.
Other SoCs support will be added in the future.Signed-off-by: Patrice Chotard
Reviewed-by: Simon Glass -
This driver implements basic clock setup, only clock gating
is implemented.This driver doesn't implement .of_match as it's binded
by MFD RCC driver.Files include/dt-bindings/clock/stm32h7-clks.h and
doc/device-tree-bindings/clock/st,stm32h7-rcc.txt
will be available soon in a kernel tag, as all the
bindings have been acked by Rob Herring [1].[1] http://lkml.iu.edu/hypermail/linux/kernel/1704.0/00935.html
Signed-off-by: Patrice Chotard
Reviewed-by: Simon Glass -
STM32F7 and STM32H7 shares the same UART block, add
STM32H7 compatible string.Signed-off-by: Patrice Chotard
Reviewed-by: Simon Glass -
STM32H7 SoCs uses the same pinctrl block as found into
STM32F7 SoCsSigned-off-by: Patrice Chotard
Reviewed-by: Simon Glass
Reviewed-by: Vikas Manocha -
This patch adds the ST glue logic to manage the DWC3 HC
on STiH407 SoC family. It configures the internal glue
logic and syscfg registers.Part of this code been extracted from kernel.org driver
(drivers/usb/dwc3/dwc3-st.c)Signed-off-by: Patrice Chotard
Reviewed-by: Simon Glass -
This is the generic phy driver for the picoPHY ports
used by USB2/1.1 controllers. It is found on STiH407 SoC
family from STMicroelectronics.Signed-off-by: Patrice Chotard
Reviewed-by: Simon Glass -
Signed-off-by: Patrice Chotard
Reviewed-by: Jaehoon Chung
Reviewed-by: Simon Glass -
Use struct udevice* as input parameter. Previous
parameters are retrieved through plat and priv data.This to prepare to use the reset framework.
Signed-off-by: Patrice Chotard
Reviewed-by: Jaehoon Chung
Reviewed-by: Simon Glass -
'default n' is the default anyway so it doesn't need to be specified
explicitly, and the rest of the file doesn't specify it either anywhere.
Drop it.Signed-off-by: Tuomas Tynkkynen
Reviewed-by: Bin Meng -
This field is no longer used since the DM conversion. Drop it.
Signed-off-by: Tuomas Tynkkynen
Reviewed-by: Bin Meng -
This field is no longer used since the DM conversion. Drop it.
Signed-off-by: Tuomas Tynkkynen
Reviewed-by: Bin Meng -
This field has never been used as the driver has been DM-based since the
beginning. Drop it.Signed-off-by: Tuomas Tynkkynen
Reviewed-by: Bin Meng -
These take the 'struct udevice *' as an argument, not the
'struct xilinx_pcie *` which is a local variable. Fix the comments to
match the code.Signed-off-by: Tuomas Tynkkynen
Reviewed-by: Bin Meng
21 Sep, 2017
5 commits
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Support spi driver and can detect MX25U1635E flash on AE3XX board.
Verification:
sf probe 0:0 50000000 0
spi_flash_std_probe(sf_Probr.c)
spi_flash_probe_slave(sf_Probr.c)
SF: Detected mx25u1635e with page size 256 Bytes, erase size 4 KiB, total 2 MiB
NDS32 # sf test 0x100000 0x1000
SPI flash test:
0 erase: 34 ticks, 117 KiB/s 0.936 Mbps
1 check: 15 ticks, 266 KiB/s 2.128 Mbps
2 write: 21 ticks, 190 KiB/s 1.520 Mbps
3 read: 11 ticks, 363 KiB/s 2.904 Mbps
Test passed
0 erase: 34 ticks, 117 KiB/s 0.936 Mbps
1 check: 15 ticks, 266 KiB/s 2.128 Mbps
2 write: 21 ticks, 190 KiB/s 1.520 Mbps
3 read: 11 ticks, 363 KiB/s 2.904 MbpsSigned-off-by: rick
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To support MACRONIX MX25U1635E 16M-BIT flash.
Signed-off-by: rick
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After soft reset complete, write mac address immediately will fail.
Add delay to work around this problem.Signed-off-by: rick
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Add cache inval and flush when rx and tx.
Signed-off-by: rick
19 Sep, 2017
21 commits
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After Simon's patch, the dtoc can work with 64bit address,
so we need to fix reg number for it.
Depend on Simon's patch set:
https://patchwork.ozlabs.org/cover/807266/Signed-off-by: Kever Yang
Acked-by: Philipp Tomsich -
With the new 32/64bit-aware dtoc, the type of reg is fdt64_t and the
OF_PLATDATA structure layout changes. This adjusts the DMC driver for
the RK3368 to track these changes.For the time being (i.e. until regmap_init_mem_platdata works for the
64bit case), we won't use regmap_init_mem_platdata here and simply
access of_plat.reg[] directly.Signed-off-by: Philipp Tomsich
Acked-by: Philipp Tomsich
Reviewed-by: Simon Glass -
With dtoc emitting fdt64_t for addresses (and region sizes), the array
indices for accessing the reg[] array needs to be adjusted. This
adjusts the Rockchip DM timer driver to correctly handle OF_PLATDATA
given this new structure layout.Signed-off-by: Philipp Tomsich
Acked-by: Philipp Tomsich
Reviewed-by: Simon Glass -
With the dev_read_addr_ptr function available, we can change the
efuse driver to use it (and eliminate the explicit type-cast).Signed-off-by: Philipp Tomsich
Reviewed-by: Simon Glass -
Update the clock driver for the RK3399 to support a live device tree.
Signed-off-by: Philipp Tomsich
Reviewed-by: Simon Glass -
The generic ehci-driver (ehci-generic.c) will try to enable the clocks
listed in the DTSI. If this fails (e.g. due to clk_enable not being
implemented in a driver and -ENOSYS being returned by the clk-uclass),
the driver will bail our and print an error message.This implements a minimal clk_enable for the RK3399 and supports the
clocks mandatory for the EHCI controllers; as these are enabled by
default we simply return success.Signed-off-by: Philipp Tomsich
Reviewed-by: Simon Glass -
Remove a comment claiming that this driver only supports the RK3288,
as we also use it on the RK3368, RK3399 and (most likely) on other
variants.Signed-off-by: Philipp Tomsich
Reviewed-by: Simon Glass
Acked-by: Philipp TomsichVersion-changes: 2
- use the dev_read_addr_ptr function in rk_gpio.c -
Update the Rockchip GPIO-bank driver to support a live tree.
Signed-off-by: Philipp Tomsich
Reviewed-by: Simon Glass
Acked-by: Philipp TomsichVersion-changes: 2
- use the dev_read_addr_ptr function in rk_gpio.c -
Update the Rockchip I2C driver to support livetree.
Signed-off-by: Philipp Tomsich
Reviewed-by: Simon Glass
Acked-by: Philipp Tomsich
Acked-by: Heiko Schocher -
Remove header file includes that have been left over after the
conversion to livetree-support.Signed-off-by: Philipp Tomsich
Reviewed-by: Simon Glass
Acked-by: Philipp Tomsich -
Update the Rockchip SDHCI wrapper to support a live device tree.
Signed-off-by: Philipp Tomsich
Reviewed-by: Simon Glass
Acked-by: Philipp TomsichVersion-changes: 2
- use the dev_read_addr_ptr function in rockchip_sdhci.c -
Update the Rockchip SPI driver to support a live device tree.
Signed-off-by: Philipp Tomsich
Reviewed-by: Simon Glass
Reviewed-by: Jagan Teki
Acked-by: Philipp Tomsich -
Update the pinctrl driver for the RK3368 to support a live device tree.
Signed-off-by: Philipp Tomsich
Reviewed-by: Simon Glass
Acked-by: Philipp Tomsich -
Update the clock driver for the RK3368 to support a live device tree.
Signed-off-by: Philipp Tomsich
Reviewed-by: Simon Glass
Acked-by: Philipp TomsichVersion-changes: 2
- use the dev_read_addr_ptr function in clk_rk3368.c -
Update the Rockchip timer driver to support a live device tree.
Signed-off-by: Philipp Tomsich
Reviewed-by: Simon Glass
Acked-by: Philipp Tomsich -
To make the Rockchip DM timer driver useful for the timing of
bootstages, we need a few enhancements:
- This implements timer_get_boot_us.
- This avoids reinitialising the timer, if it has already been
set up (e.g. by our TPL and SPL stages). Now, we have a single
timebase ticking from TPL through the full U-Boot.
- This adds support for reading the timer even before the
device-model is ready: we find the timer via /chosen/tick-timer,
then read its address and clock-frequency, and finally read the
timeval directly).Signed-off-by: Philipp Tomsich
Reviewed-by: Simon Glass
Acked-by: Philipp Tomsich -
Update the Rockchip-specific wrapper for the Designware driver to
support a live device tree.Signed-off-by: Philipp Tomsich
Reviewed-by: Simon Glass
Acked-by: Philipp TomsichVersion-changes: 2
- use the dev_read_addr_ptr function in rockchip_dw_mmc.c -
Update the Micrel KSZ90x1 driver for a live tree.
Signed-off-by: Philipp Tomsich
Acked-by: Joe Hershberger
Reviewed-by: Simon Glass -
Update the Designware Ethernet MAC driver to support a live device
tree.Signed-off-by: Philipp Tomsich
Acked-by: Joe Hershberger
Reviewed-by: Simon Glass -
The dev_read_addr_ptr() mimics the behaviour of the devfdt_get_addr_ptr(),
retrieving the first address of the node's reg-property and returning
it as a pointer (or NULL on failure).Signed-off-by: Philipp Tomsich
Acked-by: Philipp Tomsich
Reviewed-by: Simon Glass
