15 Oct, 2013
6 commits
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Signed-off-by: Wolfgang Denk
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Signed-off-by: Wolfgang Denk
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Signed-off-by: Wolfgang Denk
[trini: Drop changes for PEP 4 following python tools]
Signed-off-by: Tom Rini -
Signed-off-by: Wolfgang Denk
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Add a MAC address create based on the OMAP die ID registers.
Then poplulate the ethaddr enviroment variable so that the device
tree alias can be updated prior to boot.Signed-off-by: Dan Murphy
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OMAP4 panda rev A6 is a 4430 es2.3 IC with an updated memory
part.The panda rev A6 uses Elpida 2x4Gb memory and no longer uses Micron
so the timings needs to be updatedSigned-off-by: Dan Murphy
08 Oct, 2013
5 commits
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Since SPI register access is so expensive, it is worth transferring data
a word at a time if we can. This complicates the driver unfortunately.Use the byte-swapping feature to avoid having to convert to/from big
endian in software.This change increases speed from about 2MB/s to about 4.5MB/s.
Signed-off-by: Simon Glass
Signed-off-by: Rajeshwari S Shinde
Reviewed-by: Jagannadha Sutradharudu Teki -
Adding System Manager driver which will configure the
pin mux for real hardware Cyclone V development kit
(not Virtual Platform)Signed-off-by: Chin Liang See
Reviewed-by: Pavel Machek
Acked-by: Dinh Nguyen
Cc: Wolfgang Denk
CC: Pavel Machek
Cc: Dinh Nguyen
Cc: Tom Rini
Cc: Albert Aribaud -
omap1510inn is orphan and has been for years now.
Reove it and, as it was the only arm925t target,
also remove arm925t support.
Update doc/README.scrapyard accordingly.Signed-off-by: Albert ARIBAUD
07 Oct, 2013
4 commits
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Clock requirement for qspi clk is 192 Mhz.
According to the below formulae,f dpll = f ref * 2 * m /(n + 1)
clockoutx2_Hmn = f dpll / (hmn+ 1)fref = 20 Mhz, m = 96, n = 4 gives f dpll = 768 Mhz
For clockoutx2_Hmn to be 768, hmn + 1 should be 4.Signed-off-by: Sourav Poddar
Reviewed-by: Jagannadha Sutradharudu Teki -
Add QSPI definitions and clock configuration support.
Signed-off-by: Matt Porter
Signed-off-by: Sourav Poddar
Reviewed-by: Jagannadha Sutradharudu Teki -
The original creation of arch/arm/cpu/armv7/{virt-v7.c,nonsec_virt.S}
predates the SPDX conversion, so the original elaborate license
statements sneaked in.
Fix this by replacing them with the proper abbreviation.Signed-off-by: Andre Przywara
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We can run the DDR at 400MHz, so update the timings for that purpose.
Signed-off-by: Enric Balletbo i Serra
Reviewed-by: Javier Martinez Canillas
05 Oct, 2013
1 commit
04 Oct, 2013
6 commits
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For the KVM and XEN hypervisors to be usable, we need to enter the
kernel in HYP mode. Now that we already are in non-secure state,
HYP mode switching is within short reach.While doing the non-secure switch, we have to enable the HVC
instruction and setup the HYP mode HVBAR (while still secure).The actual switch is done by dropping back from a HYP mode handler
without actually leaving HYP mode, so we introduce a new handler
routine in our new secure exception vector table.In the assembly switching routine we save and restore the banked LR
and SP registers around the hypercall to do the actual HYP mode
switch.The C routine first checks whether we are in HYP mode already and
also whether the virtualization extensions are available. It also
checks whether the HYP mode switch was finally successful.
The bootm command part only calls the new function after the
non-secure switch.Signed-off-by: Andre Przywara
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Currently the non-secure switch is only done for the boot processor.
To enable full SMP support, we have to switch all secondary cores
into non-secure state also.So we add an entry point for secondary CPUs coming out of low-power
state and make sure we put them into WFI again after having switched
to non-secure state.
For this we acknowledge and EOI the wake-up IPI, then go into WFI.
Once being kicked out of it later, we sanity check that the start
address has actually been changed (since another attempt to switch
to non-secure would block the core) and jump to the new address.The actual CPU kick is done by sending an inter-processor interrupt
via the GIC to all CPU interfaces except the requesting processor.
The secondary cores will then setup their respective GIC CPU
interface.
While this approach is pretty universal across several ARMv7 boards,
we make this function weak in case someone needs to tweak this for
a specific board.The way of setting the secondary's start address is board specific,
but mostly different only in the actual SMP pen address, so we also
provide a weak default implementation and just depend on the proper
address to be set in the config file.Signed-off-by: Andre Przywara
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To actually trigger the non-secure switch we just implemented, call
the switching routine from within the bootm command implementation.
This way we automatically enable this feature without further user
intervention.Signed-off-by: Andre Przywara
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The core specific part of the work is done in the assembly routine
in nonsec_virt.S, introduced with the previous patch, but for the full
glory we need to setup the GIC distributor interface once for the
whole system, which is done in C here.
The routine is placed in arch/arm/cpu/armv7 to allow easy access from
other ARMv7 boards.We check the availability of the security extensions first.
Since we need a safe way to access the GIC, we use the PERIPHBASE
registers on Cortex-A15 and A7 CPUs and do some sanity checks.
Boards not implementing the CBAR can override this value via a
configuration file variable.Then we actually do the GIC enablement:
a) enable the GIC distributor, both for non-secure and secure state
(GICD_CTLR[1:0] = 11b)
b) allow all interrupts to be handled from non-secure state
(GICD_IGROUPRn = 0xFFFFFFFF)The core specific GIC setup is then done in the assembly routine.
Signed-off-by: Andre Przywara
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While actually switching to non-secure state is one thing, another
part of this process is to make sure that we still have full access
to the interrupt controller (GIC).
The GIC is fully aware of secure vs. non-secure state, some
registers are banked, others may be configured to be accessible from
secure state only.
To be as generic as possible, we get the GIC memory mapped address
based on the PERIPHBASE value in the CBAR register. Since this
register is not architecturally defined, we check the MIDR before to
be from an A15 or A7.
For CPUs not having the CBAR or boards with wrong information herein
we allow providing the base address as a configuration variable.Now that we know the GIC address, we:
a) allow private interrupts to be delivered to the core
(GICD_IGROUPR0 = 0xFFFFFFFF)
b) enable the CPU interface (GICC_CTLR[0] = 1)
c) set the priority filter to allow non-secure interrupts
(GICC_PMR = 0xFF)Also we allow access to all coprocessor interfaces from non-secure
state by writing the appropriate bits in the NSACR register.The generic timer base frequency register is only accessible from
secure state, so we have to program it now. Actually this should be
done from primary firmware before, but some boards seems to omit
this, so if needed we do this here with a board specific value.
The Versatile Express board does not need this, so we remove the
frequency from the configuration file here.After having switched to non-secure state, we also enable the
non-secure GIC CPU interface, since this register is banked.Since we need to call this routine also directly from the smp_pen
later (where we don't have any stack), we can only use caller saved
registers r0-r3 and r12 to not mess with the compiler.Signed-off-by: Andre Przywara
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A prerequisite for using virtualization is to be in HYP mode, which
requires the CPU to be in non-secure state first.
Add a new file in arch/arm/cpu/armv7 to hold a monitor handler routine
which switches the CPU to non-secure state by setting the NS and
associated bits.
According to the ARM architecture reference manual this should not be
done in SVC mode, so we have to setup a SMC handler for this.
We create a new vector table to avoid interference with other boards.
The MVBAR register will be programmed later just before the smc call.Signed-off-by: Andre Przywara
03 Oct, 2013
1 commit
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armv7.h contains some useful constants, but also C prototypes.
To include it also in assembly files, protect the non-assembly
part appropriately.Signed-off-by: Andre Przywara
02 Oct, 2013
3 commits
27 Sep, 2013
2 commits
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This patch adds the pad to i.MX6DQ and changes the i.MX6DLS
declaration to match the Linux kernel declaration.Signed-off-by: Eric Nelson
Acked-by: Marek Vasut -
The value MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET that was used to initialize
the CCGR3 register caused an undefined value for CG0.Signed-off-by: Pierre Aubert
CC: Stefano Babic
Acked-by: Eric Nelson
24 Sep, 2013
7 commits
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Add RNDIS gadget support to test atmel usba udc driver
Signed-off-by: Bo Shen
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Correct the UDPHS name from UDHPS
Signed-off-by: Bo Shen
Acked-by: Marek Vasut -
Add atmel usba udc driver support, porting from Linux kernel
The original code in Linux Kernel information is as following
commit e01ee9f509a927158f670408b41127d4166db1c7
Author: Jingoo Han
Date: Tue Jul 30 17:00:51 2013 +0900usb: gadget: use dev_get_platdata()
Use the wrapper function for retrieving the platform data instead of
accessing dev->platform_data directly.Signed-off-by: Bo Shen
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This patch makes required changes to make use
of I2S0 channel instead of I2S1 channel on exynos5250.Signed-off-by: Dani Krishna Mohan
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This patch makes the necessary changes for making use of
I2S0 channel instead of I2S1 channel on smdk board. This
changes are done to maintain the uniformity to use I2S0 channel.Signed-off-by: Dani Krishna Mohan
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This patch enables default I2S0 channel.And I2S platform
parameter has been moved to a common file viz exynos5.dtsi.Signed-off-by: Dani Krishna Mohan
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To be more EABI compliant and as a preparation for building
with clang, use the platform-specific r9 register for gd
instead of r8.note: The FIQ is not updated since it is not used in u-boot,
and under discussion for the time being.The following checkpatch warning is ignored:
WARNING: Use of volatile is usually wrong: see
Documentation/volatile-considered-harmful.txtSigned-off-by: Jeroen Hofstee
cc: Albert ARIBAUD
23 Sep, 2013
4 commits
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r9 is a platform-specific register in ARM EABI and not per
definition a general purpose register. Do not use it while
relocating so it can be used for gd.cc: Albert ARIBAUD
Signed-off-by: Jeroen Hofstee -
Every ARM cpu config.mk (arch/arm/cpu/{CPUDIR}/config.mk) defines:
PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
So, this patch moves the common compiler options to arch/arm/config.mk.
Signed-off-by: Masahiro Yamada
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Reload address was written to the counter register
instead of load register.
The problem happens when timer expires but never
reload to ~0UL (it is downcount timer).Reported-by: Stephen MacMahon
Signed-off-by: Michal Simek -
The movt/movw instruction can be used to hardcode an
memory location in the instruction itself. The linker
starts complaining about this if the compiler decides
to do so: "relocation R_ARM_MOVW_ABS_NC against `a local
symbol' can not be used" and it is not support by U-boot
as well. Prevent their use by requiring word relocations.
This allows u-boot to be build at other optimalization
levels then -Os.Signed-off-by: Jeroen Hofstee
Cc: TigerLiu@viatech.com.cn
Cc: Albert ARIBAUD
Acked-by: Simon Glass
21 Sep, 2013
1 commit
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Writing magic bits into LDO SRAM was suggested only for OMAP5432
ES1.0. Now these are no longer applicable. Moreover these bits should
not be overwritten as they are loaded from EFUSE. So avoid
writing into these registers.Boot tested on OMAP5432 ES2.0
Signed-off-by: Lokesh Vutla
