21 Jul, 2019
15 commits
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Use LPDDR4-100 sdram timings dtsi for Rockpro64 board.
All these timings are processed during TPL stage of rockpro64 board,
bootchain. This make TPL would replace rockchip in house rkbin in
current bootchain.Bootchain after and before this change:
TPL -> SPL -> U-Boot proper
rkbin -> SPL -> U-Boot proper
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang -
Add sdram timings for LPDDR4-100 via rk3399-sdram-lpddr4-100.dtsi file.
all timings are dumped from rkbin/bin/rk33/rk3399_ddr_800MHz_v1.20.binAssociated LPDDR4 board -u-boot.dtsi can include this to make these
timings available during SPL or TPL stages.Signed-off-by: Jagan Teki
Signed-off-by: YouMin Chen
Reviewed-by: Kever Yang -
Due to foot-print issues, we have LPDDR4 code can be
marked as CONFIG_RAM_RK3399_LPDDR4.So, enable it for Rock-PI-4 board.
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang -
Due to foot-print issues, we have LPDDR4 code can be
marked as CONFIG_RAM_RK3399_LPDDR4.So, enable it for Rockpro64 board.
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang -
DDR set rate can be even required for lpddr4 and we
need to keep the lpddr4 code to compile only for relevant
boards which do support lpddr4.For this requirement, and for code readability handle
data training via sdram_rk3399_ops with .set_rate and
same will update in future while supporting lpddr4 code.Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang -
LPDDR4 initialization start with at board selected frequency
and then it switches into 400MHz and 800MHz simultaneously to
make the proper sequence work on each channel with associated
training.So, add LPDDR4-800 timings inc file in driver area so-that
these timings will take during LPDDR4 initialization phase.Signed-off-by: Jagan Teki
Signed-off-by: YouMin Chen
Reviewed-by: Kever Yang -
LPDDR4 initialization start with at board selected frequency
and then it switches into 400MHz and 800MHz simultaneously to
make the proper sequence work on each channel with associated
training.So, add LPDDR4-400 timings inc file in driver area so-that
these timings will take during LPDDR4 initialization phase.Signed-off-by: Jagan Teki
Signed-off-by: YouMin Chen
Reviewed-by: Kever Yang -
Add support for setting 400MHz ddr clock.
Signed-off-by: Jagan Teki
Signed-off-by: YouMin Chen
Reviewed-by: Kever Yang -
Add support for setting 50MHz ddr clock.
Signed-off-by: Jagan Teki
Signed-off-by: YouMin Chen
Reviewed-by: Kever Yang -
Add u-boot,dm-pre-reloc property for pmu in rk3399-u-boot.dtsi
so-that SPL can access pmu.Signed-off-by: Jagan Teki
Signed-off-by: YouMin Chen
Reviewed-by: Kever Yang -
Add pmu compatible with relevant U_BOOT_DRIVER for rk3399
via syscon rk3399 driver.Signed-off-by: Jagan Teki
Signed-off-by: YouMin Chen
Reviewed-by: Kever Yang -
Add pmu header file for rk3399 SoC, this will help
to configure pmu in sdram driver.Signed-off-by: Jagan Teki
Signed-off-by: YouMin Chen
Reviewed-by: Kever Yang -
Like data training in other sdram types, mr detection need
to taken care for lpddr4 with looped rank and associated
channel to make sure the proper configuration held.Once the mr detection successful for active and configured
rank with channel number, the same can later reused during
actual LPDDR4 initialization.So, add code to support for it.
Signed-off-by: Jagan Teki
Signed-off-by: YouMin Chen
Reviewed-by: Kever Yang -
data training can be even required for lpddr4 and we
need to keep the lpddr4 code to compile only for relevant
boards which do support lpddr4.For this requirement, and for code readability handle
data training via sdram_rk3399_ops and same will update
in future while supporting lpddr4 code.Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang -
data training is using chan_info as first argument with
channel number as second argument instead of that use
dram_info as first argument so-that we can get the
chan_info at data training definition.This was the argument handling is meaningful, readable
and it would help to add similar data training for
lpddr4 in future.Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
20 Jul, 2019
25 commits
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We needs SPL LIBCOMMON and LIBGENERIC for all boards,
so we can enable them by default and no need to define
in each board.Signed-off-by: Kever Yang
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There is no difference in rk3368 board use for SYS_MALLOC_F_LEN,
so we can use default value.Signed-off-by: Kever Yang
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There is no difference in rk3328 board use for SYS_MALLOC_F_LEN,
so we can use default value.Signed-off-by: Kever Yang
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There is no difference in rk3399 board use for SYS_MALLOC_F_LEN,
so we can use default value.Signed-off-by: Kever Yang
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There is no difference in rk3288 board use for SYS_MALLOC_F_LEN,
so we can use default value.Signed-off-by: Kever Yang
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There is no difference in rk322x board use for SYS_MALLOC_F_LEN,
so we can use default value.Signed-off-by: Kever Yang
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Rockchip SoCs have different ROCKCHIP_BOOT_MODE_REG value,
move it to SoC's own Kconfig, and add address for rk3128 and
rk3328 so that all SoCs have available address.Signed-off-by: Kever Yang
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Each SoC have its config setting and its Kconfig, move
the specific setting to its own Kconfig file.Signed-off-by: Kever Yang
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Each SoC have its config setting and its Kconfig, move
the specific setting to its own Kconfig file.Signed-off-by: Kever Yang
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Each SoC have its config setting and its Kconfig, move
the specific setting to its own Kconfig file.Signed-off-by: Kever Yang
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Each SoC have its config setting and its Kconfig, move
the specific setting to its own Kconfig file.Signed-off-by: Kever Yang
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Kconfig for board target select is choice option, fixup for
rk3036, rk3288 and rv1108.Signed-off-by: Kever Yang
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No code is using this header file, remove it.
Signed-off-by: Kever Yang
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The pinctrl will default init the io while driver is probe
with new pinctrl driver.Signed-off-by: Kever Yang
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The pinctrl will default init the io while driver is probe
with new pinctrl driver.Signed-off-by: Kever Yang
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The pinctrl will default init the io while driver is probe
with new pinctrl driver.Signed-off-by: Kever Yang
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Use LPDDR4-100 sdram timings dtsi for RockPI-4 board.
All these timings are processed during TPL stage of rock-pi-4 board,
bootchain. This make TPL would replace rockchip in house rkbin in
current bootchain.Bootchain after and before this change:
TPL -> SPL -> U-Boot proper
rkbin -> SPL -> U-Boot proper
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang -
Use DDR3-1866 2GB ddr timings dtsi for 1GB NanoPi Neo4 board.
Since sdram rk3399 support dynamic stride and rank detection it
can able to detect 1GB ddr eventough the timings are meant for
dual channel, 2GB size.Bootchain after and before this change are:
TPL -> SPL -> U-Boot proper
rkbin -> SPL -> U-Boot proper
This certainly fix the second channel data training initialization
since we have dynamic rank, stride where second channel capabilities
are clear or memset to 0.Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang -
Unlike rest of dram type chips, LPDDR4 initialization start
with at board selected frequency (say 50MHz) and then it
switches into 400MHz and 800MHz simultaneously to make the
proper sequence work on each channel with associated training.The lpddr4 set rate sequnce will follow by setting lpddr4
- dq out
- ca odt
- MR3
- MR12
- MR14
registers sets in sequential order.Here is sameple log about LPDDR4-100 init sequence in Rockpro64:
Channel 0: LPDDR4, 50MHz
BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
Channel 1: LPDDR4, 50MHz
BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
256B stride
channel 0 training pass
channel 1 training pass
change freq to 400 MHz 0, 1
channel 0 training pass
channel 1 training pass
change freq to 800 MHz 1, 0This patch add support to this init sequence via lpddr4 set rate
by taking sdram timing parameters from 400, 800 .inc files.Signed-off-by: Jagan Teki
Signed-off-by: YouMin Chen
Reviewed-by: Kever Yang
(Fix travis error, use one ret instead of ret[2] in set_ctrl)
Signed-off-by: Kever Yang -
Update vref_mode_ac for lpddr4 based on VDDQ/3/2=16.8%
Signed-off-by: Jagan Teki
Signed-off-by: YouMin Chen
Reviewed-by: Kever Yang -
The mode_sel on lpddr4 value is depending on IO settings
of rd_vref.Add support for it.
Signed-off-by: Jagan Teki
Signed-off-by: YouMin Chen -
The vref_mode_dq, vref_value_dq on lpddr4 value is depending
on IO settings of rd_vref.Add support for it.
Signed-off-by: Jagan Teki
Signed-off-by: YouMin Chen
Reviewed-by: Kever Yang -
For base.odt 1 the lpddr4 tsel_rd_en value is depending
on IO settings of rd_odt_en.Add support for it.
Signed-off-by: Jagan Teki
Signed-off-by: YouMin Chen
Reviewed-by: Kever Yang -
CTL 145, 146, 159, 160 registers are used to configure
soc odt on rk3399.These soc odt values are updated from CS0_MR22_VAL and
CS1_MR22_VAL and for lpddr4 these values ORed with
tsel_rd_select_n.Signed-off-by: Jagan Teki
Signed-off-by: YouMin Chen -
tsel contrl clock drives are required to configure PHY
929, 939 controls drive settings.Add support for these control clock for all dramtype
sdrams.Thse control clock drives are configure via tsel_ckcs_select_p
and tsel_ckcs_select_n variables.tsel_ckcs_select_n is PHY_DRV_ODT_34_3 value where as
tsel_ckcs_select_p is retrived from IO settings for lpddr4
and rest uses PHY_DRV_ODT_34_3.Signed-off-by: Jagan Teki
Signed-off-by: YouMin Chen
Reviewed-by: Kever Yang
