19 Jul, 2019
13 commits
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- Update SiFive Unleashed clock driver.
- Enables SiFive SPI driver and MMC SPI driver for SiFive Unleashed
board -
The GEMGXL clock driver is now directly part of Cadence MACB
ethernet driver in upstream Linux kernel. There is no separate
GEMGXL clock driver in upstream Linux kernel hence we drop
GEMGXL clock driver from U-Boot as well.Signed-off-by: Anup Patel
Reviewed-by: Bin Meng -
The DT bindings of SiFive clock driver in upstream Linux has
changes. As-per latest DT bindings, the clock driver takes two
parent clocks and compatible string has also changed.This patch sync-up SiFive clock driver implementation as-per
upstream Linux so that we now use latest DT bindings.Signed-off-by: Anup Patel
Reviewed-by: Bin Meng -
The location and license header of DT bindings header for SiFive
clock driver has changed in upstream Linux hence this patch.Signed-off-by: Anup Patel
Reviewed-by: Bin Meng -
Now that SiFive clock driver is merged in upstream Linux, we
sync-up WRPLL library used by SiFive clock driver with upstream
Linux sources.Signed-off-by: Anup Patel
Reviewed-by: Bin Meng -
To match SiFive clock driver with latest Linux, we factor-out PLL
library as separate module under drivers/clk/analogbits.Signed-off-by: Anup Patel
Reviewed-by: Bin Meng -
The designware eth driver registers an mdio bus during probe, but if no
PHY is found, this bus is never removed although probe failes and the
driver is shown as not probed in the dm tree.This later leads to errors when e.g. the mii or mdio commands try to
use available mdio buses because the mdio bus is still registered but
all corresponding data structures are invalid because probe failed.Fix this by unregistering the mdio bus on probe failure (just as it is
unregistered in the .remove callback, too).Signed-off-by: Simon Goldschmidt
Acked-by: Joe Hershberger -
Adds a test using a makeshift MDIO MUX. The test is based on the existing
MDIO test. It uses the last emulated PHY register to verify MUX selection.Signed-off-by: Alex Marginean
Acked-by: Joe Hershberger
Reviewed-by: Bin Meng -
This 2nd register is used by the follow-up MDIO MUX test.
Signed-off-by: Alex Marginean
Reviewed-by: Bin Meng
Acked-by: Joe Hershberger -
Adds a class for MDIO MUXes, which control access to a series of
downstream child MDIOs.
MDIO MUX drivers are required to implement a select function used to switch
between child buses.
MUX children are registered as MDIO buses and they can be used just like
regular MDIOs.Signed-off-by: Alex Marginean
Reviewed-by: Bin Meng
Acked-by: Joe Hershberger -
Current code fails to probe some C45 PHYs that also respond to C22 reads.
This is the case for PHYs like Aquantia AQR112, Marvell 88X2242 (as
previously posted on the u-boot list).
If the PHY ID reads all 0s just ignore it and try the next devad.Signed-off-by: Alex Marginean
Reviewed-By: Ramon Fried
Reviewed-by: Bin Meng
Acked-by: Joe Hershberger -
adds AQR112 and AQR412 to the list of supported PHYs using existing AQR
code.Signed-off-by: Alex Marginean
Reviewed-By: Ramon Fried
Acked-by: Joe Hershberger
18 Jul, 2019
6 commits
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- Various FS/disk related fixes with security implications.
- Proper fix for the pci_ep test.
- Assorted bugfixes
- Some MediaTek updates.
- 'env erase' support. -
barno was mistakely readed from the target structure,
resulting in undefined behavious depending on the previous memory
content. fix that.Fixes: bb413337826e ("pci_ep: add pci endpoint sandbox driver")
Signed-off-by: Ramon Fried
[trini: Drop unused bar_idx]
Signed-off-by: Tom Rini -
Some storage devices have multiple hw partitions and both address from
zero, for example eMMC.
However currently block cache invalidation only applies to block
write/erase.
This can cause a problem that data of current hw partition is cached
before switching to another hw partition. And the following read
operation of the latter hw partition will get wrong data when reading
from the addresses that have been cached previously.To solve this problem, invalidate block cache after a successful
select_hwpart operation.Signed-off-by: Weijie Gao
-
Drivers need to be able to enable regulators that may be implemented as
GPIO regulators. Example: fsl_esdhc enables the vqmmc supply which is
commonly implemented as a GPIO regulator in order to switch between I/O
voltage levels.Signed-off-by: Sven Schwermer
Reviewed-by: Lukasz Majewski -
In preparation of being able to enable/disable GPIO regulators, the
code that will be shared among the two kinds to regulators is factored
out into its own source files.Signed-off-by: Sven Schwermer
Reviewed-by: Lukasz Majewski -
Add an implementation of the ds3231 driver that uses the driver
model i2c APIs.Signed-off-by: Chuanhua Han
Reviewed-by: Lukasz Majewski
17 Jul, 2019
11 commits
-
K3 devices have I2C IP that is same as OMAP2+ family. Allow driver to be
compiled for ARCH_K3.Signed-off-by: Vignesh R
Signed-off-by: Andreas Dannenberg
Reviewed-by: Heiko Schocher
Reviewed-by: Lokesh Vutla -
We would like to use the driver even without power domains being
specified for cases such as during early boot when the required power
domains have already gotten enabled by the SoC's boot ROM and such
explicit initialization is not needed and possible.Signed-off-by: Andreas Dannenberg
Reviewed-by: Tom Rini -
Add a platform specific set_control_reg() callback to help switch to
UHS speed modes.Signed-off-by: Faiz Abbas
Reviewed-by: Tom Rini -
The HOST_CONTROL2 register is a part of SDHC v3.00 and not just specific
to arasan/zynq controllers. Add the same to sdhci.h.Also create a common API to set UHS timings in HOST_CONTROL2.
Signed-off-by: Faiz Abbas
Reviewed-by: Tom Rini -
Add support in the driver for handling phy specific registers.
Signed-off-by: Faiz Abbas
Reviewed-by: Tom Rini -
Make set_ios_post() return int to faciliate error handling in
platform drivers.Signed-off-by: Faiz Abbas
-
The am654_sdhci driver needs to switch the clock off
before disabling its phy dll and needs to re-enable
the clock before enabling the phy again.Therefore, make the sdhci_set_clock() function accessible
in the am654_sdhci driver.Signed-off-by: Faiz Abbas
Reviewed-by: Tom Rini -
Add Support for masking some bits in the capabilities
register of a host controller.Also remove the redundant readl() into caps1.
Signed-off-by: Faiz Abbas
Reviewed-by: Tom Rini -
In device nodes with more than one entry in the reg property,
it is sometimes useful to regmap only of the entries. Add an
API regmap_init_mem_index() to facilitate this.Signed-off-by: Faiz Abbas
Reviewed-by: Tom Rini -
The host controller works perfectly well without having to add any
quirks. Remove them.Signed-off-by: Faiz Abbas
Reviewed-by: Tom Rini -
Sync the sdhci0 node from kernel. This changes the compatible that is
required to be there in the driver. Change the same for the SD card node
which is not yet supported in kernel. This also syncs the main_pmx0 node
as a side effect.Also change the name of the driver to match the compatible in kernel.
Signed-off-by: Faiz Abbas
Reviewed-by: Tom Rini
16 Jul, 2019
10 commits
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- Beelink-x2 STB support (Marcus)
- H6 DDR3, LPDDR3 changes (Andre, Jernej)
- H6 pin controller, USB PHY (Andre) -
The USB PHY used in the Allwinner H6 SoC has some pecularities (as usual),
which require a small addition to the USB PHY driver:
In this case the second PHY is PHY3, not PHY1, so we need to skip number
1 and 2 in the code. Just use the respective code from Linux for that.Signed-off-by: Andre Przywara
Tested-by: Corentin Labbe # Pine-H64
Reviewed-by: Jagan Teki -
To enable USB support in U-Boot, add the required clock and reset gates
to the H6 clock driver. Once enabled, the generic EHCI/OCHI drivers will
pick them up from there automatically.Signed-off-by: Andre Przywara
Tested-by: Corentin Labbe # Pine-H64
Reviewed-by: Jagan Teki -
The Allwinner H6 pin controller is not really special, at least not when
it comes to normal GPIO operation.Add the H6 compatible strings to the list of recognised strings, to make
GPIOs work for H6 boards.Signed-off-by: Andre Przywara
Tested-by: Corentin Labbe # Pine-H64
Reviewed-by: Jagan Teki -
Probably for no particular reason SUNXI_GPIO was still defined the "old
way", in header files only.Introduce SUNXI_GPIO to the Kconfig file in drivers/gpio to remove
another line from our dreadful config_whitelist.txt.Signed-off-by: Andre Przywara
Tested-by: Corentin Labbe # Pine-H64
Reviewed-by: Jagan Teki -
Macb can be used with Xilinx PCS/PMA PHY in fpga which is a 1000-baseX
phy(lpa 0x41e0). This patch adds checks for LPA_1000XFULL and
LPA_1000XHALF bits.Signed-off-by: Radu Pirea
Acked-by: Joe Hershberger -
If macb is gem and is gigabit capable, lpa value is not read from
the right register(MII_LPA) and is read from MII_STAT1000. This patch
fixes reading of the lpa value.Signed-off-by: Radu Pirea
Acked-by: Joe Hershberger -
Add new driver for the TI AM65x SoC Gigabit Ethernet Switch subsystem (CPSW
NUSS). It has two ports and provides Ethernet packet communication for the
device and can be configured as an Ethernet switch. CPSW NUSS features: the
Reduced Gigabit Media Independent Interface (RGMII), Reduced Media
Independent Interface (RMII), and the Management Data Input/Output (MDIO)
interface for physical layer device (PHY) management. The TI AM65x SoC has
integrated two-port Gigabit Ethernet Switch subsystem into device MCU
domain named MCU_CPSW0. One Ethernet port (port 1) with selectable RGMII
and RMII interfaces and an internal Communications Port Programming
Interface (CPPI) port (Host port 0).Host Port 0 CPPI Packet Streaming Interface interface supports 8 TX
channels and on RX channels operating by TI am654 NAVSS Unified DMA
Peripheral Root Complex (UDMA-P) controller.Signed-off-by: Grygorii Strashko
Signed-off-by: Keerthy
Acked-by: Joe Hershberger -
Use phys_addr_t for mdio_base address to avoid build
warnings on arm64 and dra7. Cast it to uintprt_t before
assigning to regs.Signed-off-by: Grygorii Strashko
Signed-off-by: Keerthy
Reviewed-by: Tom Rini
Acked-by: Joe Hershberger
