21 Dec, 2018
1 commit
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FEC has some clock settings inside DSC GPR. Kernel configures them,
but u-boot not. So when doing partition reset, the GPR keeps the value
from kernel, and cause clock issue to u-boot FEC: kernel enables the
divclk in GPR and set the clock slice to 250Mhz, u-boot configures the
clock slice to 125Mhz, the divclk causes the RGMII TX CLK to 62.5Mhz.Fix the issue by aligning the GPR and clock slice settings with kernel
Signed-off-by: Ye Li
Reviewed-by: Fugang Duan
12 Dec, 2018
1 commit
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To support partition reboot, the u-boot has to enable clocks by LPCG.
The LPCG will reset to default value only when the subsystem is totally
power off and reset. However, the resources in one subsystem may belong
to different partitions, so the partition reboot may not reboot the entire
subsystem.
Powers, clocks/lpcg, GPR, IP may not reset depends on various cases and
HW design. Thus, AP software has to ensure everything is reset by SW
itself to support such above cases.Signed-off-by: Ye Li
09 Nov, 2018
1 commit
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According to SCFW API requirement, when setting the clock parent,
the clock must be disabled. Otherwise it will return ERR_BUSY.When using SPL booting on iMX8QXP, both SPL and regular u-boot will
init the USDHC clock. So the second one in regular u-boot will fail
if we don't disable the clock before setting the parent.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
28 Aug, 2018
1 commit
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Add "clocks" command to list clocks values for core and some peripherals
on QM/QXP.Signed-off-by: Ye Li
(cherry picked from commit c2c9b6487440946a52564ee20c2b1943a4085152)
06 Aug, 2018
1 commit
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Still meet DPLL unstable issue on iMX8QXP B0 when doing various stress tests.
So switch back to use AVPLL for usdhc on B0Signed-off-by: Ye Li
(cherry picked from commit 099ddce37cf3100d0aeb0964db7b24e5a59ee1d0)
23 May, 2018
1 commit
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8QXP B0 chip already fix the DPLL unstable issue, so we set back the
usdhc clock parent to PLL0 (DPLL) for B0 chip. A0 chip will remain use the
PLL1 (AVPLL).Signed-off-by: Ye Li
Reviewed-by: Peng Fan
(cherry picked from commit 6e60ea8430370334eea53c7c434c3b69d08c6ceb)
27 Apr, 2018
2 commits
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Implemented the clock enable and disable interfaces for CDNS3 USB
driver.Signed-off-by: Ye Li
Acked-by: Peter Chen
(cherry picked from commit 2f0dc4c503d8ac831fb809ec124e79712defae77) -
Add cpu, power, and clocks functions for support i.MX8QM and i.MX8QXP SoCs.
Signed-off-by: Ranjani Vaidyanathan
Signed-off-by: Nitin Garg
Signed-off-by: Anson Huang
Signed-off-by: Adrian Alonso
Signed-off-by: Peng Fan
Signed-off-by: Fugang Duan
Signed-off-by: Ye Li