21 Dec, 2018

1 commit

  • FEC has some clock settings inside DSC GPR. Kernel configures them,
    but u-boot not. So when doing partition reset, the GPR keeps the value
    from kernel, and cause clock issue to u-boot FEC: kernel enables the
    divclk in GPR and set the clock slice to 250Mhz, u-boot configures the
    clock slice to 125Mhz, the divclk causes the RGMII TX CLK to 62.5Mhz.

    Fix the issue by aligning the GPR and clock slice settings with kernel

    Signed-off-by: Ye Li
    Reviewed-by: Fugang Duan

    Ye Li
     

12 Dec, 2018

1 commit

  • To support partition reboot, the u-boot has to enable clocks by LPCG.
    The LPCG will reset to default value only when the subsystem is totally
    power off and reset. However, the resources in one subsystem may belong
    to different partitions, so the partition reboot may not reboot the entire
    subsystem.
    Powers, clocks/lpcg, GPR, IP may not reset depends on various cases and
    HW design. Thus, AP software has to ensure everything is reset by SW
    itself to support such above cases.

    Signed-off-by: Ye Li

    Ye Li
     

09 Nov, 2018

1 commit

  • According to SCFW API requirement, when setting the clock parent,
    the clock must be disabled. Otherwise it will return ERR_BUSY.

    When using SPL booting on iMX8QXP, both SPL and regular u-boot will
    init the USDHC clock. So the second one in regular u-boot will fail
    if we don't disable the clock before setting the parent.

    Signed-off-by: Ye Li
    Reviewed-by: Peng Fan

    Ye Li
     

28 Aug, 2018

1 commit


06 Aug, 2018

1 commit


23 May, 2018

1 commit


27 Apr, 2018

2 commits