29 Apr, 2017
3 commits
-
Copy the dts files from kernel for qwks boards for preparing
enabling the OF_CONTROL.Signed-off-by: Juan Gutierrez
-
Update mx6dqscm boards code and build configurations to enable
OF_CONTROL and DM drivers.1. Update GPIO codes for adding gpio request
2. Enable USB DM driver
3. Update PMIC and LDO by-pass codes for DM PMIC
4. Add spinor boot support
5. Add lpddr2 modes, sizes and boards on local Kconfig
6. Update license with NXP 2017
7. Add defconfigs for qwks boardsSigned-off-by: Juan Gutierrez
-
Move the scm mx6dqscm board generic support code from v2016.03
as the base for converting to use DTB OF_CONTROL.Signed-off-by: Juan Gutierrez
26 Apr, 2017
1 commit
-
Remove CONFIG_IS_ENABLED() macro in the driver, it seems the macro don't work
in the config build for mx6sxsabreauto_config platform.And CONFIG_IS_ENABLED(FOO) evaluates to
* 1 if CONFIG_SPL_BUILD is undefined and CONFIG_FOO is set to 'y' or 'm',
* 1 if CONFIG_SPL_BUILD is defined and CONFIG_SPL_FOO is set to 'y' or 'm'If enable CONFIG_SPL_BUILD, then CONFIG_FOO doesn't work.
Now remove the CONFIG_IS_ENABLED() in the driver.
Signed-off-by: Fugang Duan
25 Apr, 2017
1 commit
-
The compatible string "fsl,imx6sl-fec" is missed for i.mx6sl in
u-boot FEC driver, so that FEC can't be recognized.Signed-off-by: Ye Li
21 Apr, 2017
1 commit
-
VGEN3 and VGEN5 have been fused the right value in PF0100 on i.mx6qp board,
so software didn't need to change their voltage output anymore. Otherwise,
VGEN3 will be wrongly updated from 1.8v to 2.8v.Signed-off-by: Robin Gong
(cherry picked from commit 6f7f185664a401f03f6ce6c81b996c1f27fdbe73)
Signed-off-by: Ye Li
20 Apr, 2017
3 commits
-
For LPI2C IP, NACK is detected by the rising edge of the ninth clock.
In current uboot driver, once NACK is detected, it will reset and then
disable LPI2C master. As a result, we can never see the falling edge
of the ninth clock.Signed-off-by: Gao Pan
(cherry picked from commit dd139ee52b709c95af3e0c968bcbc3cf42cca408) -
Current USDHC driver will reset VSELECT to 0 (3.3v) during mmc init,
then set to 1 for 1.8v eMMC I/O. When booting from eMMC, since ROM has
already set VSELECT to 1.8v before running the u-boot. This reset in
USDHC driver causes a short 2.2v pulse on CMD pin.Fix this issue by not reset VSELECT to 0 when 1.8v flag is set.
Signed-off-by: Ye Li
(cherry picked from commit f01ebfdaa57b4c74ede32a6a40cf9cf9184ce049) -
Fix wrong usage of device_get_supply_regulator.
device_get_supply_regulator returns 0 on success.Signed-off-by: Peng Fan
14 Apr, 2017
2 commits
-
The new ROM patch will set DENOM and NUM of APLL and SPLL to 0 to
workaround PLL issue.
When DENOM is 0, the PLL rate calculation will divide 0 and raise a signal.raise: Signal # 8 caught
To avoid such problem, we change our calculation.
Signed-off-by: Ye Li
(cherry picked from commit f28cf489e1b3864bac6bae4944d8a73bab30ec32) -
The GPU uses APLL PFD2 as its clock parent (483.84Mhz) with divider set to 1.
This frequecy is out of ULP A0 spec. The MAX rate for GPU is 350Mhz.
So we simply configure the APLL PFD2 to 345.6Mhz (FRAC=28) to workaround the problem.
The correct fix should let GPU handle the clock rate in kernel.Signed-off-by: Ye Li
(cherry picked from commit e931d534fd68e0e639082766de17a20e705fd908)
06 Apr, 2017
9 commits
-
The tools/makefile will build a libfdt Python module if swig is available.
But actually it not only need swig but also need python libary. We will get
build break below when python is not installed. It is better to add more
check for python lib.Because applications may install some python libs, but not the full libpython-dev,
then the Python.h is missed. We check Python.h to instead checking libs.tools/libfdt_wrap.c:147:21: fatal error: Python.h: No such file or directory
Signed-off-by: Ye Li
-
The CONFIG_SYS_USE_NAND is not used in v2017.03. We have to replace it
by other NAND configurations, like CONFIG_CMD_NAND or CONFIG_NAND_MXS.Signed-off-by: Ye Li
-
To use keyboard on mx6slevk, some configurations are added in android header files.
Need adding them to config_whilelist.txtSigned-off-by: Ye Li
-
The button pad setting is missed during cherry-pick.
Signed-off-by: Ye Li
-
The CONFIG_USB_GADGET is duplicated set in defconfig and android header file.
Remove it from defconfigSigned-off-by: Ye Li
-
Missed to add eMMC dts file to Makefile
Signed-off-by: Ye Li
-
In Kconfig, the CONFIG_MXC_EPDC depends on CONFIG_LCD.
We can't only set the CONFIG_MXC_EPDC in defconfig and set CONFIG_LCD in header file.
This will cause the both two configs are not selected. So in fact the epdc codes
are not compiled.Signed-off-by: Ye Li
-
add splash screen feature for epdc.
it's tested on imx6sll arm2 board and evk board.Signed-off-by: Robby Cai
(cherry picked from commit c85c6f2a0f08dfc6c2859fe969b2021ab32b9370)
Signed-off-by: Ye Li -
The sparse image writing and boot image reading may have cache unaligned problem.
The u-boot v2017 will print warning at runtime. This patch fixes the
unaligned problem.Signed-off-by: Ye Li
05 Apr, 2017
20 commits
-
Since we need the setexpr command for m4 image loading, so enable
the CONFIG_CMD_SETEXPR for i.MX6SX defconfigs with m4 boot enabled.Signed-off-by: Ye Li
-
The endianness is not set at qspi driver initialization. So if we don't
boot from QSPI, we will get wrong endianness when accessing from AHB address
directly.Signed-off-by: Ye Li
-
Fix below build warning by declaring sata_get_dev the in the part.h
common/env_sata.c: In function 'saveenv':
common/env_sata.c:70:9: warning: implicit declaration of function 'sata_get_dev' [-Wimplicit-function-declaration]
sata = sata_get_dev(env_sata);
^
common/env_sata.c:70:7: warning: assignment makes pointer from integer without a cast [-Wint-conversion]
sata = sata_get_dev(env_sata);
^
common/env_sata.c: In function 'env_relocate_spec':
common/env_sata.c:116:7: warning: assignment makes pointer from integer without a cast [-Wint-conversion]
sata = sata_get_dev(env_sata);Signed-off-by: Ye Li
-
The wp-gpios property is used for gpio, if this is set, the WP pin is muxed
to gpio function, can't be used as internal WP checking.This patch changes to examine the "fsl,wp-controller" for using internal WP checking. And
wp-gpios for using gpio pin.Signed-off-by: Ye Li
-
The CONFIG_CMD_BOOTD is commented in the defconfig files, then the default boot
can't work. We need to uncomment it for auto boot.Signed-off-by: Ye Li
-
Since the u-boot size increases after using OF_CONTROL to including DTB,
we have to adjust ENV_OFFSET to 896K for SD/eMMC/FLASH/SATA.Signed-off-by: Ye Li
-
Change the i2c alias seq number to align with device index. So in lpi2c
driver we don't need to add 4 to get the device index. This codes may not
valid on other platforms.Signed-off-by: Ye Li
-
The MX6SL, SLL and ULL have DCP to replace CAAM in SoC. We have to
disable the CAAM driver for them.Signed-off-by: Ye Li
-
Modify the CONFIG_CSF_SIZE to 0x4000 to align with v2016.03. Also remove
the duplicated setting for CSF size.Signed-off-by: Ye Li
-
The num/denom is a float value, but in the calculation it is convert
to integer 0, and cause the result wrong.Signed-off-by: Ye Li
(cherry picked from commit 4a8f51499ca098637e9ee2036066374d34458865) -
According to the Cortex-A7 TRM, for ACTLR.SMP bit "You must ensure this bit
is set to 1 before the caches and MMU are enabled, or any cache and TLB
maintenance operations are performed".
ROM sets this bit in normal boot flow, but when in serial download mode, it is not set.
Here we add it in u-boot as a common flow for all i.MX cortex-a7 platforms,
including mx7d, mx6ul/ull and mx7ulp.Signed-off-by: Ye Li
(cherry picked from commit 14990af03450f3e1898135c86fd8b93328007617) -
To improve the performance, enable the bank interleave for DDR3. Update
the DDR3 settings to new script IMX7D_DDR3_533MHz_1GB_32bit_V2.0.dsChanges:
1. Enable bank interleave
2. Improve the drive strength for non-TO1.1 chips.
3. Updates ZQ_CON0 settings.
4. For 19x19 DDR3 ARM2 and 12x12 DDR3 ARM2, they are using old version scripts which
were not upgrade with SABRESD script. According to DDR owner suggestion, to use same version
script for all of them.File:
http://compass.freescale.net/livelink/livelink?func=ll&objid=233861153&objAction=browse&sort=name&viewType=1Test:
Passed stress test on one TO1.2 SABRESD, one TO1.1 SABRESD and one TO1.0 SABRESD.
Passed stress test on one 12x12 ddr3 ARM2.Signed-off-by: Ye Li
(cherry picked from commit 62e73b45c53e3302d869c373da72699199b90648) -
To improve the performance, enable the bank interleave for LPDDR3. Update
the LPDDR3 settings to new script IMX7D_LPDDR3_533MHz_2GB_32bit_V2.0.ds5.Changes:
1. Enable bank interleave
2. Improve the drive strength for non-TO1.1 chips.
3. Updates ZQ_CON0 settings.
4. Change to 0 for reserved bits.File:
http://compass.freescale.net/livelink/livelink?func=ll&objid=233861153&objAction=browse&sort=name&viewType=1Test:
Passed stress test on one 19x19 lpddr3 arm2 and one 12x12 lpddr3 arm2.
Passed LPSR test on one 12x12 lpddr3 arm2.Signed-off-by: Ye Li
(cherry picked from commit 9a4fa3f8d2762791a76fd90e83feec8c8c9235b0) -
Update lpddr2 settings to latest version
IMX6UL_LPDDR2_400MHz_16bit_V1.1.incUse pre-charge command 0x1 per DDR register programming aid
Signed-off-by: Adrian Alonso
(cherry picked from commit e7aa25c2c7313b00475e3e0ce394a2fbaa569fbd) -
Update lpddr2 settings to latest version
MX6SL_MMDC_LPDDR2_register_programming_aid_v0.9.incUse pre-charge command 0x1 per DDR register programming aid
Signed-off-by: Adrian Alonso
(cherry picked from commit 7c15f3afbd2cfa97b14a0013ef959e9e73fd2f1e) -
LPDDR2 script MX6SL_MMDC_LPDDR2_register_programming_aid_v0.9.inc
Updated to add Precharge all command per JEDEC
The memory controller may optionally issue a precharge-all command
prior to the MRW reset command
This is strongly recommended to ensure robust DRAM initializationSigned-off-by: Adrian Alonso
Signed-off-by: Ye Li
(cherry picked from commit 498f4a791593069220213c6d777527f4d899fb8a) -
- Adjust ZQ delay for MMDC clock frequency at 400MHz
- Precharge all commands per JEDEC
The memory controller may optionally issue a Precharge-All command
prior to the MRW Reset command, this is strongly recommended to ensure
a robust DRAM initializationDDR Calibration script:
http://sw-stash.freescale.net/projects/IMX/repos/ddr-scripts-rel/commits/a72e010a1fd8c7fe0fda7bdc4d058c478e94c3daSigned-off-by: Adrian Alonso
(cherry picked from commit 03cc626df73d6c2bb36daf280b1cd43170c298a0) -
Add fastboot and recovery mode support for mx6qarm
Signed-off-by: Adrian Alonso
(cherry picked from commit 505e899ce582118da28ca1f4487ce7f179225bd7) -
Add Android support for mx6qarm2 lpddr2 pop target
Signed-off-by: Adrian Alonso
(cherry picked from commit 6356f2b420f3571493755f6b3a307a66a539b60c) -
1. pass androidboot.storage_type to android, 'init' use it to parse
different init.freescale.storage.rc.
2. store new ptable with gpt partition.
3. we use the last LBA as backup gpt table, there is many warning log
when boot, change print to debugChange-Id: I84070735e9d4c2741b0e240bc1c61b357dabc5b8
Signed-off-by: Sanshan Zhang
(cherry picked from commit da0ce2787256a323371641b0764266d386d767a5)
Signed-off-by: Ye Li
