19 Jul, 2017
1 commit
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we set gpt image in the last lba for sd boot.
complete the gpt header, gpt entry and protective MBR according
the last lba gpt rule.Change-Id: Icc356a66f82ad359c0243245ab9fdfaea3bccd4f
Signed-off-by: zhang sanshan
11 Jul, 2017
1 commit
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…e when booting from NAND
uboot can't get the correct misc info.
nand_info[0] is the info of mtd in v2016 or more older version.
nand_info[0] hold the pointer of mtd info in v2017.Change-Id: I6b336efeafeed1e0f4e3224f738e72b83f1e09df
Signed-off-by: zhang sanshan <sanshan.zhang@nxp.com>
10 Jul, 2017
5 commits
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…s no valid gpt partition
add command "fastboot 0"
Change-Id: Ibad6dcab5213d815ac968034aeef5ff5a0be3b1b
Signed-off-by: zhang sanshan <sanshan.zhang@nxp.com> -
* add board support for android and android things.
mx6ul_nxpu_iopb, pico-6ul, pico-imx7d, aquila-6ul
reorganize the Kconfig, and fix the redefine issue.
* add android configure into configure-while
* add a common file mx_android_common.h
it will be included by android and android things.
defconfig only include ANDROID_THINGS_SUPPORT or ANDROID_SUPPORT
* move partition_table_valid into f_fastboot.c.
it's a common code.
* add invalidate_dcache_range in fixed order.
It will have salt invalid issue if we do not add it in order
* add display for pico-7d.Change-Id: I6f8a4876c2f8bbd098034d1e3f53033109300bca
Signed-off-by: zhang sanshan -
* Add CONFIG_SYSTEM_RAMDISK_SUPPORT to support system's ramdisk
* Normal boot: cmdline to bypass ramdisk in boot.img,
but use Recovery boot: Use the ramdisk in boot.img
* commandline is larger than 512, system can't bootup sometime for commandline issue.
* support fastboot getvar.
* Support "fastboot erase" command for emmc device.
TODO: uboot community have api to operate flash, we can unify this part
* support "fastboot flash" even on damaged gptChange-Id: I080c25d6569d6cab56ff025601cd3b8df21cf3dd
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Fix issue for API changed from v2017.
porting below patch from v2016.
commit 44834fd12f60a090e3d10ab6f84a75460894d49dChange-Id: Ifaf0b86dd29648f9150646f00f54502676df9013
Signed-off-by: zhang sanshan -
boot_addr_start for booti should be the addr of Image rather than
boot.img, so need read Image into hdr->kernel_addr.
change the offset for bootloader.
booti do not call android_image_get_kernel to init android env.
booti can't load boot.img, so it can't init android env.
init android env through android_image_get_kernel.Change-Id: Ifb990ee9c5710ce7bd5fa9a0d4221dcb0e52d341
Signed-off-by: sanshan zhang
21 Jun, 2017
3 commits
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Fix compile error when enable CONFIG_NAND_BOOT.
Fix data abort issue in uboot.Change-Id: If41a7fafa40a2c851882c723a201ac5cdf31284f
Signed-off-by: zhang sanshan -
Fix compile error for api change.
Porting below patches from v2015.o4:
MA-7875 Enable CAAM for i.MX6
MA-7875-1 Support fastboot lock&unlock in u-boot
MA-7875-2 Support fastboot lock/unlock in i.MX6 platform
MA-7875-3 Support fastboot lock/unlock in i.MX6UL
MA-8425 fastboot: return OKAY in fastboot erase
MA-8418 fix return value check for get_device_and_partition
MA-8622 - [brillo] fix uboot compile warnings and code style warningsChange-Id: I2370c3e5851cc1f92aaa93c200e6c079f7929af2
Signed-off-by: zhang sanshan -
* Add API to read\write MISC partition.
* get the boot mode from BCB command when boot up.
* get the boot up tactics from bootctrl.Change-Id: Icbba6340e10983dddc1b04804ecc012a3a3c57d0
Signed-off-by: zhang sanshan
24 May, 2017
1 commit
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The reset_sata should reset the sata device info and free the probe_ent
memory. Otherwise, it will cause memory leak if we init the sata again.Signed-off-by: Ye Li
(cherry picked from commit 39c9261fd057b0fa98f9dfdee7d368aa029ff736)
12 May, 2017
1 commit
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i.MX6UL/ULL evk board net get the wrong MAC address from fuse, exp,
eth1 get MAC0 address, eth0 get MAC1 address from fuse. Set the
priv->dev_id to device->seq as the real net interface alias id then
.fec_get_hwaddr() read the related MAC address from fuse.Signed-off-by: Fugang Duan
11 May, 2017
3 commits
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Fix coverity:392391 392382 392385 Unsigned compared against 0
Signed-off-by: Peng Fan
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The device managed API actually not free the memory, so need
to use devm_kfree to free the memory to avoid leakage.Coverity: 392384 resource leak
Signed-off-by: Peng Fan
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There are two problems in enabling DDR mode in this new driver:
1. The TDH bits in FLSHCR register should be set to 1. Otherwise, the TX DDR delay logic
won't be enabled. Since u-boot driver does not have DDR commands in LUT. So this won't
cause explicit problem.
2. When doing read/write/readid/erase operations, the MCR register is overwritten, the bits
like DDR_EN are cleared during these operations. When we using DDR mode QSPI boot, the TDH bit
is set to 1 by ROM. if the DDR_EN is cleared, there is no clk2x output for TX data shift.
So these operations will fail.
The explicit problem is users may get "SF: unrecognized JEDEC id bytes: ff, ff, ff" error
after using DDR mode QSPI boot on 6UL/ULL EVK boards.Signed-off-by: Ye Li
25 Apr, 2017
1 commit
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The compatible string "fsl,imx6sl-fec" is missed for i.mx6sl in
u-boot FEC driver, so that FEC can't be recognized.Signed-off-by: Ye Li
20 Apr, 2017
3 commits
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For LPI2C IP, NACK is detected by the rising edge of the ninth clock.
In current uboot driver, once NACK is detected, it will reset and then
disable LPI2C master. As a result, we can never see the falling edge
of the ninth clock.Signed-off-by: Gao Pan
(cherry picked from commit dd139ee52b709c95af3e0c968bcbc3cf42cca408) -
Current USDHC driver will reset VSELECT to 0 (3.3v) during mmc init,
then set to 1 for 1.8v eMMC I/O. When booting from eMMC, since ROM has
already set VSELECT to 1.8v before running the u-boot. This reset in
USDHC driver causes a short 2.2v pulse on CMD pin.Fix this issue by not reset VSELECT to 0 when 1.8v flag is set.
Signed-off-by: Ye Li
(cherry picked from commit f01ebfdaa57b4c74ede32a6a40cf9cf9184ce049) -
Fix wrong usage of device_get_supply_regulator.
device_get_supply_regulator returns 0 on success.Signed-off-by: Peng Fan
06 Apr, 2017
1 commit
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The sparse image writing and boot image reading may have cache unaligned problem.
The u-boot v2017 will print warning at runtime. This patch fixes the
unaligned problem.Signed-off-by: Ye Li
05 Apr, 2017
20 commits
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The endianness is not set at qspi driver initialization. So if we don't
boot from QSPI, we will get wrong endianness when accessing from AHB address
directly.Signed-off-by: Ye Li
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The wp-gpios property is used for gpio, if this is set, the WP pin is muxed
to gpio function, can't be used as internal WP checking.This patch changes to examine the "fsl,wp-controller" for using internal WP checking. And
wp-gpios for using gpio pin.Signed-off-by: Ye Li
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Change the i2c alias seq number to align with device index. So in lpi2c
driver we don't need to add 4 to get the device index. This codes may not
valid on other platforms.Signed-off-by: Ye Li
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1. pass androidboot.storage_type to android, 'init' use it to parse
different init.freescale.storage.rc.
2. store new ptable with gpt partition.
3. we use the last LBA as backup gpt table, there is many warning log
when boot, change print to debugChange-Id: I84070735e9d4c2741b0e240bc1c61b357dabc5b8
Signed-off-by: Sanshan Zhang
(cherry picked from commit da0ce2787256a323371641b0764266d386d767a5)
Signed-off-by: Ye Li -
Integrate the FSL android fastboot features into community's fastboot.
1. Use USB gadget g_dnl driver
2. Integrate the FSL SD/SATA/NAND flash operations, since the GPT and
EFI partitions are not support by i.MX.
3. Add FDT support to community's android image.
4. Add a new boot command "boota" for android image boot. The boota
implements to load ramdisk and fdt to their loading addresses
specified in boot.img header, while bootm won't do it for android image.
5. Support the authentication of boot.img at the "load_addr" for
both SD and NAND.
6. We use new configuration CONFIG_FSL_FASTBOOT for Freescale's fastboot
with relevant header file "fsl_fastboot.h". While disabling the
configuration, the community fastboot is used.
7. Overwrite the cmdline in boot.img by using bootargs saved in local environment.
8. Add recovery and reboot-bootloader support.Signed-off-by: Ye Li
(cherry picked from commit 23d63ff185929fff5e392efc853d69b606ba081a) -
The i.MX6SL EVK needs this driver in android fastboot support. Add
this driver to u-boot.To use the driver, user must define:
CONFIG_MXC_KPD Enable the driver
CONFIG_MXC_KEYMAPPING Key mapping matrix
CONFIG_MXC_KPD_COLMAX The column size of key mapping matrix
CONFIG_MXC_KPD_ROWMAX The row size of the key mapping matrixSigned-off-by: Ye Li
(cherry picked from commit 5096e572667ff41217deb4ba9b1bd15e93fa6b59) -
Add MT35XU512ABA parameters to NOR flash parameters array. Since the
manufactory ID is changed to 0x2C, add it for micron and using it for
relevant settings.The MT35XU512ABA only supports 1 bit mode and 8 bits. It can't support
dual and quad. Because the 8 bits is not support by u-boot framework and
driver. We only use 1 bit mode for this flash.Signed-off-by: Ye Li
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The LCDIF provides video source for MIPI DSI host at DPI-2 interface.
When the LCDIF Framebuffer driver is enabled, it uses the panel
parameters setup by environments to create a panel device and register
it to DSI host driver and then enable the DSI host.Signed-off-by: Ye Li
(cherry picked from commit 85659ea5ee975fa2d5fa7215e17a01f7006c39bf) -
Add the mipi dsi panel driver for device HX8363 from kernel. The panel
driver needs work with mipi_dsi_northwest driver.Signed-off-by: Ye Li
(cherry picked from commit 0c6d0f4202bae7f61d38ecff1c9d255261f022f2) -
Add the host driver base from kernel for MIPI DSI controller on i.MX7ULP.
The controller provides a DPI-2 interface for LCDIF video stream, and a APB interface
for packet transmission.The driver provides APIs to register a MIPI panel device and its driver. The panel
driver can use the write packet function provided by the host driver to send control
packets to panel device via APB interface.MIPI DSI has its PHY and dedicated PLL. The driver will setup them when enabling the DSI
host.Signed-off-by: Ye Li
(cherry picked from commit e02115dd1c5d36ec06eabcb5a0b8e09aaf0f29a0) -
The i.MX7ulp EVK board uses GPIO to detect ID for USB OTG0,
but when using DM USB driver, it is hard coded to use OTG ID pin.
Add a board override function that when extcon property is provided,
the function can check the GPIO to get ID.Signed-off-by: Ye Li
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In mx7ulp pinctrl driver, we should create two info instances for
iomuxc0 and iomuxc1 respective, otherwise they will share the same
info instance, and cause problem in get base address... etc.Signed-off-by: Ye Li
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when using SHARE_MUX_CONF_REG, wrong mask is used for writing config value.
which causes mux value is cleared.Signed-off-by: Ye Li
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On i.MX7ULP, the fuse words (except bank 0 and 1) only supports to write once,
because they use ECC mode. Multiple writes may damage the ECC value and cause a
wrong fuse value decoded when reading.
This patch adds a checking before the fuse word programming, only can write
when the word value is 0.Signed-off-by: Ye Li
(cherry picked from commit e8447d649a631ec98120d84fab124ca29fbe39f0) -
On mx7ulp EVK board, we use MX25R6435F NOR flash, add its parameters
and IDs to flash parameter array. Otherwise, the flash probe will fails.Signed-off-by: Ye Li
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The mx7ulp has small TX/RX FIFO (64Bytes) and AHB buffer size (128Bytes)
than other i.MX. Change some parameters for it.Also found when the DDR_EN bit is set, sometime the page programming will fail
during large data programming. The 64 bytes data is not programmed into flash.
But when DDR_EN is clear, there is no such issue. Suspect this is a IC issue.
We have disable the DDR_EN for mx7ulp.Signed-off-by: Ye Li
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When doing port reset, the PR bit of PORTSC1 will be automatically
cleared by our IP, but standard EHCI needs explicit clear by software. The
EHCI-HCD driver follow the EHCI specification, so after 50ms wait, it
clear the PR bit by writting to the PORTSC1 register with value loaded before
setting PR.This sequence is ok for our IP when the delay time is exact. But when the timer
is slower, some bits like PE, PSPD have been set by controller automatically
after the PR is automatically cleared. So the writing to the PORTSC1 will overwrite
these bits set by controller. And eventually the driver gets wrong status.We implement the powerup_fixup operation which delays 50ms and will check
the PR until it is cleared by controller. And will update the reg value which is written
to PORTSC register by EHCI-HCD driver. This is much safer than depending on the delay
time to be accurate and aligining with controller's behaiver.Signed-off-by: Ye Li
(cherry picked from commit 8dfdf83abaff44efb487f801cd1757a729d427c5) -
The ULP has two USB controllers. These two controllers have similar NC
registers layout as i.MX7D. But OTG0 uses UTMI PHY simliar as i.MX6, not
the integrated PHY on i.MX7D. The OTG1 needs off-chip HSIC PHY or ULPI PHY
to work.This patch only supports OTG0 with UTMI PHY.
Signed-off-by: Ye Li
(cherry picked from commit 1ac22cabb96a14ac4ca58df60ae2025fb5e94db6) -
Add compatible property for i.MX7ULP.
Add a weak init_usdhc_clk function, i.MX7ULP use this to init the clock.Signed-off-by: Peng Fan
Reviewed-by: Jaehoon Chung
Reviewed-by : Stefano Babic -
Add i.MX7ULP support.
The buadrate calculation on i.MX7ULP is different,so add a new setbrg
function for i.MX7ULP.
Add a enum lpuart_devtype for runtime check for different platforms.Signed-off-by: Peng Fan
Cc: Stefano Babic
Cc: Bhuvanchandra DV
Cc: York Sun
Cc: Shaohui Xie
Cc: Alison Wang