24 May, 2019
11 commits
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We have initialized pre_div, so no need to override it. And
it will break those have pre_div initialized as 2.Signed-off-by: Peng Fan
Reviewed-by: Ye Li
(cherry picked from commit 94ec725e440da10c04b5e7f1c9e59b47112c1dd0) -
Secure Storage service in Trusty OS will compute
the encrypted mmc frame and the rpmb proxy inject the frame
to driver directly. So that need to export RPMB related
interface for Secure Storage proxy use.Change-Id: I7f69831a20a440f597d323b610fa615fd4344d05
Signed-off-by: Haoran.Wang
(cherry picked from commit 4d2c1873ce8221e35874265e41dc42a6df169659)
(cherry picked from commit ce4e9dc35ff89a2429224ae6d0ffb4109cb42e28) -
Add the fuse checking in drivers, when the module is disabled in fuse,
the driver will not work.Changed drivers: BEE, GPMI, APBH-DMA, ESDHC, FEC, QSPI, ECSPI, I2C,
USB-EHCI, GIS, LCDIF and EPDC.Signed-off-by: Ye Li
(cherry picked from commit 1704e116f9b39aeb99201919a18bc2b1e19a980e)
(cherry picked from commit 2d3b5df8530cd5ef883750378838dea7c40259af)
(cherry picked from commit 6e8c9ae136bee8ec0121c1db4b935510caad09db) -
The wp-gpios property is used for gpio, if this is set, the WP pin is muxed
to gpio function, can't be used as internal WP checking.This patch changes to examine the "fsl,wp-controller" for using internal WP checking. And
wp-gpios for using gpio pin.Signed-off-by: Ye Li
(cherry picked from commit 733a7fde6fea35d6f2ea18c7759a06904b655e54)
(cherry picked from commit 9da605be6d73b8fca627cdd272fce51bdc4c0b6d) -
Should use CONFIG_IS_ENABLED not IS_ENABLED for CLK driver, so it will
check the CONFIG_SPL_CLK when building SPLMove init_clk_usdhc to non-clk driver case, since assigned-clocks properties
will initialize the clocks by clk driver.Signed-off-by: Ye Li
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After the commit b9a2a0e2e9c0 ("mmc: Add support for downgrading
HS200/HS400 to HS mode"), it add a parameter in mmc_set_card_speed()
which indicates that the HS200/HS400 to HS downgrade is happening.During the HS400 initialization, first select to HS200, and config
the related clock rate, then downgrade to HS mode. So here also need
to config the downgrade value to be true, make sure in the function
mmc_set_card_speed(), after switch to HS mode, first config the
clock rate, then read the EXT_CSD. Otherwise read EXT_CSD in HS mode
at wrong clock rate, e.g. 200MHz, may lead to uncertain result.Test on i.MX8QM MEK board, some Micron eMMC will stuck in transfer
mode in this case, and USDHC will never get data transfer complete
status, cause the uboot hang.Signed-off-by: Haibo Chen
(cherry picked from commit 0ba8e1c6efa2e9c34c9b54105d6c50ee293ec1d7) -
Flash system partition with fastboot will earse the partition firstly
The 1.2s timeout will fail on some SD Card.
Enlarge it to 5s to make it works for most of sdcardChange-Id: I285df411c7a07025251fd19f4c8e8b549bee2421
Signed-off-by: guoyin.chen
(cherry picked from commit 642d77fb6d6412095faa6584eeef7bb0132cae57)
(cherry picked from commit 49ae851ccd00a027d122338d7b39402135041ad8) -
Update for HS400 ES and enable iMX8QM/QXP for HS400 and HS400 ES.
Signed-off-by: Ye Li
(cherry picked from commit 0768f229e824120c53d40a1c0d062c1f49384100) -
The eMMC 5.1 supports the HS400 Enhanced Strobe mode, add this
support to mmc.Signed-off-by: Ye Li
(cherry picked from commit 0972a7219faefcae27e7c39a9c84f46145148913) -
600ms is not enough to erase erase_grp_size for some sdcard.
enlarge to to 1200ms.Change-Id: Ic980794fa3064f92b479b87380e694f853f83c6a
Signed-off-by: zhang sanshan
(cherry picked from commit 4a1db2cd700ea434e25c0692c545e571f5841a00)
(cherry picked from commit 3f4f3e0519c8415409d6186a7e775c9556864001) -
When sd/mmc work at DDR mode, like HS400/HS400ES/DDR52/DDR50 mode,
the actual clock rate is just half of the expected clock.This patch set the DDR_EN bit first for DDR mode, hardware divide
the usdhc clock automatically, then follow the original sdr clock
setting method.Signed-off-by: Haibo Chen
Signed-off-by: Ye Li
(cherry picked from commit 2a8a0cf0f5d2fcb06d217e3d026219532fed5eb7)
29 Mar, 2019
1 commit
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After the commit b9a2a0e2e9c0 ("mmc: Add support for downgrading
HS200/HS400 to HS mode"), it add a parameter in mmc_set_card_speed()
which indicates that the HS200/HS400 to HS downgrade is happening.During the HS400 initialization, first select to HS200, and config
the related clock rate, then downgrade to HS mode. So here also need
to config the downgrade value to be true for two reasons. First,
make sure in the function mmc_set_card_speed(), after switch to HS
mode, first config the clock rate, then read the EXT_CSD, avoid
receiving data of EXT_CSD in HS mode at 200MHz. Second, after issue
the MMC_CMD_SWITCH command, it need to wait a bit then switch bus
properties.Test on i.MX8QM MEK board, some Micron eMMC will stuck in transfer
mode in this case, and USDHC will never get data transfer complete
status, cause the uboot hang.Signed-off-by: Haibo Chen
Acked-by: Marek Vasut
27 Mar, 2019
1 commit
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- Various fixes for bugs found by u-boot test.py
26 Mar, 2019
2 commits
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On 16bit variants of the TMIO SD IP, the SECCNT register can only be
programmed to 16bit values, while on the 32bit and 64bit variants it
can be programmed to 32bit values. The SECCNT register indicates the
maximum number of blocks in a continuous transfer. Hence, limit the
maximum continuous transfer block count to 65535 blocks on 16bit
variants of the TMIO IP and to BIT(32)-1 blocks on 32bit and 64bit
variants.Signed-off-by: Marek Vasut
Cc: Masahiro Yamada -
Set MMCIF clock rate to 97.5 MHz, which is the default according
to Gen2 datasheet.Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
Cc: Jaehoon Chung
25 Mar, 2019
1 commit
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The tiny printf implementation only supports %x format specifier,
it does not support %X . Since it makes little difference whether
the debug output prints hex numbers in capitals or not, change it
to %x and make the MMC_TRACE output work with tiny printf too.Signed-off-by: Marek Vasut
Cc: Jaehoon Chung
Cc: Simon Glass
25 Feb, 2019
2 commits
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According to latest specification rev.0026 and after confirmation with
HW engineer, the DTCNTL register TAPNUM field must be set to 8 even on
H3 ES2.0 SoC. Make it so.Signed-off-by: Marek Vasut
Cc: Masahiro Yamada -
According to latest specification rev.0026, when HOST_MODE bit 0
(WMODE) is not set, HOST_MODE bit 8 (BUSWIDTH) is ignored. Clear
HOST_MODE bit 8 in such case and align the code with Linux and
avoid possible unforeseen issues.Signed-off-by: Marek Vasut
Cc: Masahiro Yamada
19 Feb, 2019
1 commit
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- Misc Gen5 fixes
- stratix10 bugfix
- dwmmc bugfix
18 Feb, 2019
1 commit
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Poll for iDMAC TX/RX interrupt before disable DMA.
This to prevent disable DMA before data is transfer
completed.Signed-off-by: Ley Foon Tan
17 Feb, 2019
4 commits
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- Various MMC fixes
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The DT2FF register must be configured differently for HS400 mode
and for HS200/SDR104 mode. Configure the DT2FF register according
to the recommended datasheet settings for each mode.Signed-off-by: Marek Vasut
Cc: Masahiro Yamada -
Set the HOST_MODE register WMODE bit according to the SDHI bus width,
that is 0 for 64bit bus and 1 for 16/32bit bus.Signed-off-by: Marek Vasut
Cc: Masahiro Yamada -
Older kernel versions or systems which do not connect eMMC reset line
properly may not be able to handle situations where either the eMMC
is left in HS200/HS400 mode or SD card in UHS modes by the bootloader
and may misbehave. Downgrade the eMMC to HS/HS52 mode and/or SD card
to non-UHS mode before booting the kernel to allow such older kernels
to work with modern U-Boot.Signed-off-by: Marek Vasut
Cc: Tom Rini
16 Feb, 2019
1 commit
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Since the fsl_esdhc will also be used by SPL, make the
preprocessor switches more generic to allow any kind of build.Signed-off-by: Abel Vesa
Reviewed-by: Fabio Estevam
Reviewed-by: Lukasz Majewski
10 Feb, 2019
4 commits
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- SD/MMC fixes and ext4 memory leak fix
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Samsung sound patches (applied for Samsung maintainer)
Common sound support
buildman environment support
of-platdata documentation improvements -
Use regulator_set_enable_if_allowed() api instead of regulator_set_enable()
while enabling io regulators. This way the driver doesn't see an error
when disabling an always-on regulator and when enabling is not supported.Reviewed-by: Simon Glass
Signed-off-by: Lokesh Vutla -
Now that these boards use driver model we can drop the old code. At
present s5p_mmc_init() is still used by goni and smdkv310 so cannot be
removed unless we remove those boards.Signed-off-by: Simon Glass
Reviewed-by: Lukasz Majewski
Reviewed-by: Minkyu Kang
09 Feb, 2019
4 commits
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Errata i929 in certain OMAP5/DRA7XX/AM57XX silicon revisions
(SPRZ426D - November 2014 - Revised February 2018 [1]) mentions
unexpected tuning pattern errors. A small failure band may be present
in the tuning range which may be missed by the current algorithm.
Furthermore, the failure bands vary with temperature leading to
different optimum tuning values for different temperatures.As suggested in the related Application Report (SPRACA9B - October 2017
- Revised July 2018 [2]), tuning should be done in two stages.
In stage 1, assign the optimum ratio in the maximum pass window for the
current temperature. In stage 2, if the chosen value is close to the
small failure band, move away from it in the appropriate direction.References:
[1] http://www.ti.com/lit/pdf/sprz426
[2] http://www.ti.com/lit/pdf/SPRACA9Signed-off-by: Faiz Abbas
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When using CMD6 to switch eMMC card timing from HS200/HS400 to HS/legacy,
do not poll for the completion status using CMD13, but rather wait 50mS.Once the card receives the CMD6 and starts executing it, the bus is in
undefined state until both the card finishes executing the command and
until the controller switches the bus to matching timing configuration.
During this time, it is not possible to transport any commands or data
across the bus, which includes the CMD13.Signed-off-by: Marek Vasut
Cc: Jaehoon Chung -
The internal DMAC asserts DMA transfer end bit too early on older
version of the TMIO IPs which use bit 17 for DTRAEND. Add 1uS
delay after the completion of DMA transfer and before invalidating
the cache to let the DMAC fully complete the transfer. Otherwise,
it could happen that the last few bytes of a transferred data are
not available.A test case to trigger this behavior is the following command, ran
on the U-Boot command line, with Sandisk 16 GiB UHS-I card inserted
into SDHI slot 0 and with first partition being of type FAT:
=> while true ; do mmc rescan ; fstype mmc 0:1 ; doneSigned-off-by: Marek Vasut
Cc: Masahiro Yamada -
Different versions of the SDHI core use either bit 17 or bit 20 for the
DTRAEND indication, which can differ even between SoC revisions. Make
the DTRAEND bit position part of the driver private data, so that the
probe function can set this accordingly. Set this to 20 on Socionext
SoCs and either 17 or 20 on Renesas SoCs, depending on the SoC.Signed-off-by: Marek Vasut
Cc: Masahiro Yamada
31 Jan, 2019
1 commit
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- Enable DM_MMC support
30 Jan, 2019
6 commits
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For 2019.04
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If a board DT describes a cd-gpios property, but also marks the storage
as non-removable, we must ignore the GPIO (as Linux does).Teach the DM_MMC part of the Allwinner MMC driver about the
non-removable DT property, to fix DM_MMC access on the SoPine and
Pine64-LTS board.Signed-off-by: Andre Przywara
Acked-by: Jagan Teki -
Now that we have the gate clocks and the reset gates in our new
Allwinner clock driver, let's make use of them in the MMC driver, when
DM_MMC is defined.
We treat the reset device as optional now, as the older SoCs don't
implement it.Signed-off-by: Andre Przywara
Reviewed-by: Jagan Teki -
A80 gates clock already be part of CLK framework, so just
add mod_clk offset with A80 compatible string.Cc: Rask Ingemann Lambertsen
Cc: Jaehoon Chung
Signed-off-by: Jagan Teki
Reviewed-by: Andre Przywara -
Unlike other Allwinner SoC's, H6 uses a different MMC mod clock offset.
Connect that with the respective compatible string.Signed-off-by: Jagan Teki
Reviewed-by: Andre Przywara
Signed-off-by: Andre Przywara -
Add MMC compatible strings for A83T, A64, H5.
Signed-off-by: Jagan Teki
Reviewed-by: Andre Przywara
Signed-off-by: Andre Przywara
