27 Apr, 2018

1 commit

  • Add fsl_fspi driver for flexspi controller. This driver supports:
    1. DDR Quad output
    2. Prefetch function for improve read performance.
    3. Fast read and Quad read for one line read mode.
    4. Read flash FSR register.
    5. DM.

    Signed-off-by: Han Xu
    Signed-off-by: Ye Li
    (cherry picked from commit ae4e80b7b0debd2ad868781aaeb28ca4f2d9a8aa)

    Ye Li
     

14 Feb, 2018

8 commits


26 Jan, 2018

1 commit


24 Jan, 2018

2 commits


23 Jan, 2018

1 commit


30 Nov, 2017

1 commit


21 Sep, 2017

1 commit

  • Support spi driver and can detect MX25U1635E flash on AE3XX board.

    Verification:

    sf probe 0:0 50000000 0
    spi_flash_std_probe(sf_Probr.c)
    spi_flash_probe_slave(sf_Probr.c)
    SF: Detected mx25u1635e with page size 256 Bytes, erase size 4 KiB, total 2 MiB
    NDS32 # sf test 0x100000 0x1000
    SPI flash test:
    0 erase: 34 ticks, 117 KiB/s 0.936 Mbps
    1 check: 15 ticks, 266 KiB/s 2.128 Mbps
    2 write: 21 ticks, 190 KiB/s 1.520 Mbps
    3 read: 11 ticks, 363 KiB/s 2.904 Mbps
    Test passed
    0 erase: 34 ticks, 117 KiB/s 0.936 Mbps
    1 check: 15 ticks, 266 KiB/s 2.128 Mbps
    2 write: 21 ticks, 190 KiB/s 1.520 Mbps
    3 read: 11 ticks, 363 KiB/s 2.904 Mbps

    Signed-off-by: rick

    rick
     

13 Aug, 2017

1 commit


09 Jul, 2017

1 commit


07 Jul, 2017

1 commit

  • AVR32 is gone. It's already more than two years for no support in Buildroot,
    even longer there is no support in GCC (last version is heavily patched 4.2.4).

    Linux kernel v4.12 got rid of it (and v4.11 didn't build successfully).

    There is no good point to keep this support in U-Boot either.

    Reviewed-by: Simon Glass
    Reviewed-by: Tom Rini
    Reviewed-by: Heiko Schocher
    Signed-off-by: Andy Shevchenko

    Andy Shevchenko
     

18 May, 2017

1 commit


29 Jan, 2017

1 commit


29 Oct, 2016

1 commit


27 Sep, 2016

1 commit

  • The SPI IP core in the Marvell Armada 3700 is similar to the one in the
    other Armada SoCs. But the differences are big enough that it makes
    sense to introduce a new driver instead of cluttering the old
    kirkwood driver with #ifdef's.

    Signed-off-by: Stefan Roese
    Cc: Nadav Haklai
    Cc: Kostya Porotchkin
    Cc: Wilson Ding
    Cc: Victor Gu
    Cc: Hua Jing
    Cc: Terry Zhou
    Cc: Hanna Hawa
    Cc: Haim Boot
    Reviewed-by: Jagan Teki

    Stefan Roese
     

22 Sep, 2016

1 commit


10 Jun, 2016

1 commit

  • This driver implements SPI protocol in master mode to communicate
    with the SPI device connected on SPI bus. It handles /CS explicitly
    by controlling respective pin as gpio ('cs-gpios' property in dt node)
    and uses PIO mode for SPI transaction. It is configurable based
    on driver-model only.

    Cc: Jagan Teki
    Signed-off-by: Purna Chandra Mandal
    Reviewed-by: Daniel Schwierzeck

    Purna Chandra Mandal
     

21 May, 2016

1 commit


15 Mar, 2016

1 commit

  • After this conversion the driver will able to support both dm and non-dm
    and code is more extensible like we can remove the non-dm part simply
    without touching anycode if all the boards which are using this driver
    become dm driven.

    Cc: Tom Rini
    Reviewed-by: Simon Glass
    Acked-by: Christophe Ricard
    Tested-by: Christophe Ricard
    Signed-off-by: Jagan Teki
    [Set priv->wordlen, Add Kconfig entry and file credit for dm conversion]
    Signed-off-by: Christophe Ricard

    Jagan Teki
     

12 Dec, 2015

1 commit


13 Nov, 2015

1 commit

  • This is the normal Tegra SPI driver modified to work with the
    QSPI controller in Tegra210. It does not do 2x/4x transfers
    or any other QSPI protocol.

    Signed-off-by: Yen Lin
    Signed-off-by: Tom Warren
    Reviewed-by: Jagan Teki

    Tom Warren
     

25 Oct, 2015

1 commit


23 Oct, 2015

1 commit


03 Sep, 2015

1 commit


02 Jul, 2015

9 commits