19 Dec, 2014
6 commits
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There are new microcode revisions available. Update them. Also change
the format so that the first 48 bytes are not omitted from the device tree
data.Signed-off-by: Simon Glass
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We might end up with a few of these, so put them in their own directory.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
Some Intel CPUs use an 'FSP' binary blob which provides an inflexible
means of starting up the CPU. One result is that microcode updates can only
be done before RAM is available and therefore parsing of the device tree
is impracticle.Worse, the addess of the microcode update must be stored in ROM since a
pointer to its start address and size is passed to the 'FSP' blob. It is
not possible to perform any calculations to obtain the address and size.To work around this, ifdtool is enhanced to work out the address and size of
the first microcode update it finds in the supplied device tree. It then
writes these into the correct place in the ROM. U-Boot can then start up
the FSP correctly.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
Rather than two independent arrays, use a single array of a suitable
structure. Also add a 'type' member since we will shortly add additional
types.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
When a file is missing it helps to know which file. Update the error message
to print this information.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
This is missing a parameter. Fix it to avoid a warning when debug is
enabled.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
18 Dec, 2014
5 commits
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Signed-off-by: Masahiro Yamada
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Now UniPhier platform is only supported with SPL.
Signed-off-by: Masahiro Yamada
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The normal image is working on DRAM. It is better to use DRAM also
for init stack than L2 cache.Signed-off-by: Masahiro Yamada
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init_page_table is only set on SPL.
Signed-off-by: Masahiro Yamada
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The property name of the "aliases" node should be "serial*"
to assign a desired number for the device sequence number.Signed-off-by: Masahiro Yamada
17 Dec, 2014
1 commit
16 Dec, 2014
15 commits
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Add proper error checking into the PHY tuning patch. Make the PHY tunning only
happen in case the KSZ9021 PHY is enabled in config. Call the config callback
after the tuning finished.Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Tom Rini
Cc: Pavel Machek -
A new interface is introduced to support generic board structure.
Converts it to use new interface.Signed-off-by: Tang Yuantian
Reviewed-by: York Sun -
Deep sleep for generic board is supported now, modify qe
deep-sleep code to adapt it.Signed-off-by: Zhao Qiang
Reviewed-by: York Sun -
Offsets were overlaping, causing pamu access violations in
hypervised scenarios.Signed-off-by: Cristian Sovaiala
Signed-off-by: Laurentiu Tudor
Reviewed-by: York Sun -
Corrected the order of arguments in memset in run_descriptor
function. Wrong order of argumnets led to improper initialization
of members of struct type result. This resulted in RNG instantiation
error.Signed-off-by: Gaurav Rana
Reviewed-by: York Sun -
Following boards has incorrect number of portals defined.
powerpc/T102xQDS
powerpc/T102xRDB
powerpc/T1040QDS
powerpc/T104xRDBSigned-off-by: Jeffrey Ladouceur
Reviewed-by: York Sun -
Not all portals might be managed and therefore visible.
Set the isdr register so that the corresponding isr register
won't be set. This is required when supporting power management.Signed-off-by: Jeffrey Ladouceur
Reviewed-by: York Sun -
we need to differentiate dual-role MACs into two types: MACs with
10GEC enumeration consistent with DTSEC enumeration(defined by
CONFIG_FSL_FM_10GEC_REGULAR_NOTATION) and other MACs without
CONFIG_FSL_FM_10GEC_REGULAR_NOTATION defined.Signed-off-by: Shengzhou Liu
Reviewed-by: York Sun -
Commit f29f804a93e87c17670607641d120f431a3b0633 generalized the TLB
mapping function, but made the DDR mapping leftover size to zero,
causing the message not printed.Signed-off-by: York Sun
CC: Alexander Graf
CC: Scott Wood -
For DDR controller version 4.7 or newer, MRC_CYC (mode register set
cycle time) is max(tMRD, tMOD). tMRD is 4nCK, or 8nCK (RDIMM). tMOD
is max(12nCK, 15ns) according to JEDEC spec.DDR4 is not affected by this change.
Signed-off-by: York Sun
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Add following configs in header file:
CONFIG_SYS_GENERIC_BOARD
CONFIG_DISPLAY_BOARDINFOSigned-off-by: Shaohui Xie
Reviewed-by: York Sun -
Signed-off-by: Chunhe Lan
Reviewed-by: York Sun -
Signed-off-by: Harninder Rai
Reviewed-by: York Sun
15 Dec, 2014
2 commits
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Use asmlinkage defined in include/linux/linkage.h if necessary.
Actually no ARM board uses asmlinkage, so this commit has no impact.Signed-off-by: Masahiro Yamada
Cc: Albert ARIBAUD -
Commit 65dd74a674d6 (x86: ivybridge: Implement SDRAM init) introduced
x86-specific asmlinkage into arch/x86/include/asm/config.h.Commit ed0a2fbf14f7 (x86: Add a definition of asmlinkage) added the
same macro define again, this time, into include/common.h.
(Please do not add arch-specific stuff to include/common.h any more;
it is already too cluttered.)The generic asmlinkage is defined in . If you want
to override it with an arch-specific one, the best way is to add it
to like Linux Kernel.Signed-off-by: Masahiro Yamada
Cc: Simon Glass
Tested-by: Simon Glass
14 Dec, 2014
11 commits
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FSP builds a series of data structures called the Hand-Off-Blocks
(HOBs) as it progresses through initializing the silicon. These data
structures conform to the HOB format as described in the Platform
Initialization (PI) specification Volume 3 Shared Architectual
Elements specification, which is part of the UEFI specification.Create a simple command to parse the HOB list to display the HOB
address, type and length in bytes.Signed-off-by: Bin Meng
Acked-by: Simon Glass -
Per Intel FSP architecture specification, FSP provides 3 routines
for bootloader to call. The first one is the TempRamInit (aka
Cache-As-Ram initialization) and the second one is the FspInit
which does the memory bring up (like MRC for other x86 targets)
and chipset initialization. Those two routines have to be called
before U-Boot jumping to board_init_f in start.S.The FspInit() will return several memory blocks called Hand Off
Blocks (HOBs) whose format is described in Platform Initialization
(PI) specification (part of the UEFI specication) to the bootloader.
Save this HOB address to the U-Boot global data for later use.Signed-off-by: Bin Meng
Acked-by: Simon Glass -
Signed-off-by: Bin Meng
Acked-by: Simon Glass -
Use inline assembly codes to call FspNotify() to make sure parameters
are passed on the stack as required by the FSP calling convention.Signed-off-by: Bin Meng
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This is the initial import from Intel FSP release for Queensbay
platform (Tunnel Creek processor and Topcliff Platform Controller
Hub), which can be downloaded from Intel website.For more details, check http://www.intel.com/fsp.
Note: U-Boot coding convention was applied to these codes, so it
looks completely different from the original Intel release.
Also update FSP support codes license header to use SPDX ID.Signed-off-by: Bin Meng
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Add Intel Tunnel Creek SPI controller support which is an ICH7
compatible device.Signed-off-by: Bin Meng
Acked-by: Simon Glass -
Signed-off-by: Bin Meng
Acked-by: Simon Glass -
On most x86 boards, the legacy serial ports (io address 0x3f8/0x2f8)
are provided by a superio chip connected to the LPC bus. We must
program the superio chip so that serial ports are available for us.Signed-off-by: Bin Meng
Acked-by: Simon Glass -
Signed-off-by: Bin Meng
Acked-by: Simon Glass -
Movie setup_pch_gpios() in the ich6-gpio driver to the board support
codes, so that the driver does not need to know any platform specific
stuff (ie: include the platform specifc chipset header file).Signed-off-by: Bin Meng
Acked-by: Simon Glass -
Move GD_BIST from lib/asm-offsets.c to arch/x86/lib/asm-offsets.c
as it is x86 arch specific stuff. Also remove GENERATED_GD_RELOC_OFF
which is not referenced anymore.Signed-off-by: Bin Meng
Acked-by: Simon Glass
