Eric Lee / smarc-uboot

13 Aug, 2014

1 commit

  • cf8ddacff   powerpc/t1042RDB: Add Video - HDMI support ... Browse Code »

    T1042 has internal display interface unit (DIU) for driving video.
    T1042RDB supports video mode via
    -LCD using TI enconder
    -HDMI type interface via HDMI encoder

    Chrontel, CH7301C encoder which is I2C programmable is used
    as HDMI connector on T1042RDB.
    This patch add support to
    -enable Video interface for T1042RDB
    -route qixis multiplexing to enable DIU-HDMI interface on board
    -program DIU pixel clock gerenartor for T1042
    -program HDMI encoder via I2C on board

    This patch refer to the upstream diu patch
    (337b0c52b3296f371d04aef71a833e09110e0e6b) for T1040qds.

    Signed-off-by: Jason Jin
    Signed-off-by: Wang Dongsheng
    [York Sun: resolve conflict and move changes to T104xRDB.h]
    Reviewed-by: York Sun

    Jason Jin
     

23 Apr, 2014

2 commits

  • 18c014454   board/t104xrdb: Add support of NAND, SD, SPI boot for T104xRDB ... Browse Code »

    Add support of 2 stage NAND, SD, SPI boot loader using SPL framework.
    here, PBL initialise the internal SRAM and copy SPL(160KB). This further
    initialise DDR using SPD and environment and copy u-boot(768 KB) from NAND to DDR.
    Finally SPL transer control to u-boot.

    Initialise/create followings required for SPL framework
    - Add spl.c which defines board_init_f, board_init_r
    - update tlb and ddr accordingly

    Signed-off-by: Prabhakar Kushwaha
    Reviewed-by: York Sun

    Prabhakar Kushwaha
     
  • 55153d6c3   board/t104xrdb: Add support of CPLD ... Browse Code »

    T1040RDB and T1042RDB_PI has CPLD. Here CPLD controls board mux/features.

    This support of CPLD includes
    - files and register defintion
    - Commands to swtich alternate bank and default bank

    Signed-off-by: Prabhakar Kushwaha
    Reviewed-by: York Sun

    Prabhakar Kushwaha
     

04 Feb, 2014

1 commit

  • 714fd406d   powerpc/t104xrdb: Add basic ethernet support ... Browse Code »

    This covers only non-L2 switch ethernet interfaces i.e.
    RGMII and SGMII interface for both T1040RDB and T1042RDB_PI

    T1040RDB is configured as serdes protocol 0x66 which can
    support following interfaces
    2 RGMIIS on DTSEC4, DTSEC5
    1 SGMII on DTSEC3

    T1042RDB_PI is configured as serdes protocol 0x06 which can
    support following interfaces
    2 RGMIIS on DTSEC4, DTSEC5

    Signed-off-by: Poonam Aggrwal
    Signed-off-by: Priyanka Jain
    [York Sun: Minor change in commit message]
    Signed-off-by: York Sun

    Priyanka Jain
     

14 Nov, 2013

1 commit

  • 062ef1a66   powerpc/t104xrdb: Add T1040RDB board support ... Browse Code »

    T1040RDB is Freescale Reference Design Board supporting
    the T1040 QorIQ Power Architecture™ processor.

    T1040RDB board Overview
    -----------------------
    - Four e5500 cores, each with a private 256 KB L2 cache
    - 256 KB shared L3 CoreNet platform cache (CPC)
    - Interconnect CoreNet platform
    - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
    support
    - Data Path Acceleration Architecture (DPAA) incorporating acceleration
    for the following functions:
    - Packet parsing, classification, and distribution
    - Queue management for scheduling, packet sequencing, and congestion
    management
    - Cryptography Acceleration
    - RegEx Pattern Matching Acceleration
    - IEEE Std 1588 support
    - Hardware buffer management for buffer allocation and deallocation
    - Ethernet interfaces
    - Integrated 8-port Gigabit Ethernet switch
    - Four 1 Gbps Ethernet controllers
    - SERDES Connections, 8 lanes supporting:
    - PCI
    - SGMII
    - QSGMII
    - SATA 2.0
    - DDR Controller 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and
    Interleaving
    -IFC/Local Bus
    - NAND flash: 1GB 8-bit NAND flash
    - NOR: 128MB 16-bit NOR Flash
    - Ethernet
    - Two on-board RGMII 10/100/1G ethernet ports.
    - PHY #0 remains powered up during deep-sleep
    - CPLD
    - Clocks
    - System and DDR clock (SYSCLK, “DDRCLK”)
    - SERDES clocks
    - Power Supplies
    - USB
    - Supports two USB 2.0 ports with integrated PHYs
    - Two type A ports with 5V@1.5A per port.
    - SDHC
    - SDHC/SDXC connector
    - SPI
    - On-board 64MB SPI flash
    - I2C
    - Devices connected: EEPROM, thermal monitor, VID controller
    - Other IO
    - Two Serial ports
    - ProfiBus port

    Signed-off-by: Poonam Aggrwal
    Signed-off-by: Prabhakar Kushwaha
    Signed-off-by: Priyanka Jain
    [York Sun: fixed Makefile]
    Acked-by: York Sun

    Priyanka Jain