04 Oct, 2017
1 commit
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U-Boot widely uses error() as a bit noisier variant of printf().
This macro causes name conflict with the following line in
include/linux/compiler-gcc.h:# define __compiletime_error(message) __attribute__((error(message)))
This prevents us from using __compiletime_error(), and makes it
difficult to fully sync BUILD_BUG macros with Linux. (Notice
Linux's BUILD_BUG_ON_MSG is implemented by using compiletime_assert().)Let's convert error() into now treewide-available pr_err().
Done with the help of Coccinelle, excluing tools/ directory.
The semantic patch I used is as follows:
//
@@@@
-error
+pr_err
(...)
//Signed-off-by: Masahiro Yamada
Reviewed-by: Simon Glass
[trini: Re-run Coccinelle]
Signed-off-by: Tom Rini
22 Sep, 2017
1 commit
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This field is no longer used since the DM conversion. Drop it.
Signed-off-by: Tuomas Tynkkynen
Reviewed-by: Bin Meng
29 Jul, 2017
1 commit
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Update the tegra pci driver to support a live device tree. Fix the check
for nvidia,num-lanes so that an error will actually be detected.Tested-by: Marcel Ziswiler
Tested-on: Beaver, Jetson-TK1
Signed-off-by: Simon Glass
Tested-by: Stephen Warren
08 Feb, 2017
1 commit
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At present devices use a simple integer offset to record the device tree
node associated with the device. In preparation for supporting a live
device tree, which uses a node pointer instead, refactor existing code to
access this field through an inline function.Signed-off-by: Simon Glass
14 Oct, 2016
1 commit
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The signature for this macro has changed. Bring in the upstream version and
adjust U-Boot's usages to suit.Signed-off-by: Simon Glass
Update to drivers/power/pmic/palmas.c:
Signed-off-by: KeerthyChange-Id: I6cc9021339bfe686f9df21d61a1095ca2b3776e8
16 Aug, 2016
1 commit
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Tegra186 supports the new standard clock, reset, and power domain APIs.
Older Tegra SoCs still use custom APIs. Enhance the Tegra PCIe driver so
that it can operate with either set of APIs.On Tegra186, the BPMP handles all aspects of PCIe PHY (UPHY) programming.
Consequently, this logic is disabled too.Signed-off-by: Stephen Warren
Reviewed-by: Simon Glass
Signed-off-by: Tom Warren
06 Jul, 2016
2 commits
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On recent SoCs, tegra_pcie_phy_enable() isn't called; but instead
tegra_pcie_enable_controller() calls tegra_xusb_phy_enable(). However,
part of tegra_pcie_phy_enable() needs to happen in all cases. Move that
code to tegra_pcie_port_enable() instead.For reference, NVIDIA's downstream Linux kernel performs this operation
in tegra_pcie_enable_rp_features(), which is called immediately after
tegra_pcie_port_enable(). Since that function doesn't exist in the U-Boot
driver, we'll just add it to the tail of tegra_pcie_port_enable() instead.Signed-off-by: Stephen Warren
Signed-off-by: Tom Warren -
The value that should be programmed into the PADS_REFCLK register varies
per SoC. Fix the Tegra PCIe driver to program the correct values. Future
SoCs will require different values in cfg0/1, so the two values are stored
separately in the per-SoC data structures.For reference, the values are all documented in NV bug 1771116 comment 20.
The Tegra210 value doesn't match the current TRM, but I've filed a bug to
get the TRM fixed. Earlier TRMs don't document the value this register
should contain, but the ASIC team has validated all these values, except
for the Tegra20 value which is simply left unchanged in this patch.Signed-off-by: Stephen Warren
Signed-off-by: Tom Warren
05 May, 2016
1 commit
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Tegra20's PCIe controller has a couple of quirks. There are workarounds in
the driver for these, but they don't work after the DM conversion:1) The PCI_CLASS value is wrong in HW.
This is worked around in pci_tegra_read_config() by patching up the value
read from that register. Pre-DM, the PCIe core always read this via a
16-bit access to the 16-bit offset 0xa. With DM, 32-bit accesses are used,
so we need to check for offset 0x8 instead. Mask the offset value back to
32-bit alignment to make this work in all cases.2) Accessing devices other than dev 1 causes a data abort.
Pre-DM, this was worked around in pci_skip_dev(), which the PCIe core code
called during enumeration while iterating over a bus. The DM PCIe core
doesn't use this function. Instead, enhance tegra_pcie_conf_address() to
validate the bdf being accessed, and refuse to access invalid devices.
Since pci_skip_dev() isn't used, delete it.I've also validated that both these WARs are only needed for Tegra20, by
testing on Tegra30/Cardhu and Tegra124/Jetson TKx. So, compile them in
conditionally.Fixes: e81ca88451cf ("dm: tegra: pci: Convert tegra boards to driver model for PCI")
Signed-off-by: Stephen Warren
Reviewed-by: Thierry Reding
Reviewed-by: Simon Glass
Signed-off-by: Tom Warren
29 Jan, 2016
1 commit
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This function can fail, so be sure to report any errors that occur.
Signed-off-by: Simon Glass
Reviewed-by: Joe Hershberger
01 Dec, 2015
1 commit
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Adjust the Tegra PCI driver to support driver model and move all boards over
at the same time. This can make use of some generic driver model code, such
as the range-decoding logic.Signed-off-by: Simon Glass
Tested-by: Stephen Warren
13 Nov, 2015
5 commits
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This needs a separate compatible value from Tegra124 since the new HW
version has bugs that would prevent a driver for previous HW versions
from operating at all.Signed-off-by: Stephen Warren
Signed-off-by: Tom Warren -
The board PCI setup code may control regulators that are required simply
to bring up the PCI controller itself (or PLLs, IOs, ... it uses). Move
the call to this function earlier so that all board-provided resources
are ready early enough for everything to work.Signed-off-by: Stephen Warren
Signed-off-by: Tom Warren -
Tegra210's PCIe controller has a bug that requires the PCA (performance
counter) feature to be enabled. If this isn't done, accesses to device
configuration space will hang the chip for tens of seconds. Implement
the workaround.Signed-off-by: Stephen Warren
Signed-off-by: Tom Warren -
The number of cells used by each entry in the DT ranges property is
determined by the #address-cells/#size-cells properties. Fix the code
to respect this.Signed-off-by: Stephen Warren
Signed-off-by: Tom Warren -
Tegra peripherals can generally access a 32-bit physical address space,
and I believe this applies to PCIe. Clip the PCI region that refers to
DRAM so it fits into 32-bits to avoid issues.Signed-off-by: Stephen Warren
Signed-off-by: Tom Warren
06 Aug, 2015
1 commit
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fdt_addr_t is changed to phys_addr_t. The format in debug should be updated
to %pa to match the type.Signed-off-by: York Sun
CC: Simon Glass
24 Jan, 2015
1 commit
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commit a62e84d7b1824a202dd incorrectly changed the tegra pci code to the
new fdtdec pci helpers. To get the device index of the root port, the
"reg" property should be parsed from the dtb (as was previously the
case).With this patch i can successfully network boot my jetson tk1
Signed-off-by: Sjoerd Simons
Tested-by: Thierry Reding
Acked-by: Thierry Reding
13 Jan, 2015
1 commit
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This commit adds several APIs to decode PCI device node according to
the Open Firmware PCI bus bindings, including:
- fdtdec_get_pci_addr() for encoded pci address
- fdtdec_get_pci_vendev() for vendor id and device id
- fdtdec_get_pci_bdf() for pci device bdf triplet
- fdtdec_get_pci_bar32() for pci device register barSigned-off-by: Bin Meng
Acked-by: Simon Glass
Signed-off-by: Simon Glass
(Include in fdtdec.h and adjust tegra to fix build error)
19 Dec, 2014
1 commit
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Add support for the PCIe controller found on some generations of Tegra.
Tegra20 has 2 root ports with a total of 4 lanes, Tegra30 has 3 root
ports with a total of 6 lanes and Tegra124 has 2 root ports with a total
of 5 lanes.This is based on the Linux kernel driver, originally submitted upstream
by Mike Rapoport.Signed-off-by: Mike Rapoport
Signed-off-by: Thierry Reding
Signed-off-by: Simon Glass
Signed-off-by: Tom Warren
