25 May, 2013

2 commits

  • Debug trace buffers are memory mapped in DCSR space beyond 4M.

    Signed-off-by: Stephen George
    Signed-off-by: Andy Fleming

    Stephen George
     
  • Allow VDD voltage overriding with a command. This is an add-on feasture of
    VID. To override VDD, use command vdd_override with the value of voltage
    in mV, for example

    vdd_override

    The above example will set the VDD to 1.050 volt. Any wrong value out of
    range of 0.8188 to 1.2125 volt or invalid string is ignored.

    In addition to the command, if overriding VDD is needed earlier in booting
    process, save an variable and reboot:

    setenv t4240qds_vdd_mv
    saveenv

    Signed-off-by: York Sun
    Signed-off-by: Andy Fleming

    York Sun
     

23 Oct, 2012

1 commit

  • The T4240QDS is a high-performance computing evaluation, development and
    test platform supporting the T4240 QorIQ Power Architecture™ processor.

    SERDES Connections
    32 lanes grouped into four 8-lane banks
    Two “front side” banks dedicated to Ethernet
    Two “back side” banks dedicated to other protocols
    DDR Controllers
    Three independant 64-bit DDR3 controllers
    Supports rates up to 2133 MHz data-rate
    Supports two DDR3/DDR3LP UDIMM/RDIMMs per controller
    QIXIS System Logic FPGA

    Each DDR controller has two DIMM slots. The first slot of each controller
    has up to 4 chip selects to support single-, dual- and quad-rank DIMMs.
    The second slot has only 2 chip selects to support single- and dual-rank
    DIMMs. At any given time, up to total 4 chip selects can be used.

    Detail information can be found in doc/README.t4qds

    Signed-off-by: York Sun
    Signed-off-by: Andy Fleming
    Signed-off-by: Kumar Gala
    Signed-off-by: Prabhakar Kushwaha
    Signed-off-by: Shengzhou Liu
    Signed-off-by: Roy Zang
    Signed-off-by: Andy Fleming

    York Sun