23 Oct, 2012

1 commit

• ffd06e023   powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1 ... Browse Code »

  Move spin table to cached memory to comply with ePAPR v1.1.
  Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined.

  'M' bit is set for DDR TLB to maintain cache coherence.

  See details in doc/README.mpc85xx-spin-table.

  Signed-off-by: York Sun
  Signed-off-by: Andy Fleming

  York Sun

  2012-10-23 03:31:32 +0800