24 Sep, 2016

1 commit


07 Sep, 2016

1 commit

  • Currently MX6 SPL DDR initialization hardcodes the REF_SEL and
    REFR fields of the MDREF register as 1 and 7, respectively for
    DDR3 and 0 and 3 for LPDDR2.

    Looking at the MDREF initialization done via DCD we see that
    boards do need to initialize these fields differently:

    $ git grep 0x021b0020 board/
    board/bachmann/ot1200/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800
    board/ccv/xpress/imximage.cfg:DATA 4 0x021b0020 0x00000800 /* MMDC0_MDREF */
    board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x7800
    board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x00005800
    board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800
    board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800
    board/freescale/mx6qsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00005800
    board/freescale/mx6qsabreauto/mx6dl.cfg:DATA 4 0x021b0020 0x00005800
    board/freescale/mx6qsabreauto/mx6qp.cfg:DATA 4 0x021b0020 0x00005800
    board/freescale/mx6sabresd/mx6dlsabresd.cfg:DATA 4 0x021b0020 0x00005800
    board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800
    board/freescale/mx6slevk/imximage.cfg:DATA 4 0x021b0020 0x00001800
    board/freescale/mx6sxsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00000800
    board/freescale/mx6sxsabresd/imximage.cfg:DATA 4 0x021b0020 0x00000800
    board/warp/imximage.cfg:DATA 4 0x021b0020 0x00001800

    So introduce a mechanism for users to be able to configure
    REFSEL and REFR fields as needed.

    Keep all the mx6 SPL users in their current REF_SEL and REFR values,
    so no functional changes for the existing users.

    Signed-off-by: Fabio Estevam
    Reviewed-by: Eric Nelson

    Fabio Estevam
     

28 Jul, 2016

8 commits


13 Jun, 2016

1 commit


31 May, 2016

12 commits


28 May, 2016

1 commit


24 May, 2016

2 commits


06 Feb, 2016

1 commit

  • Correct spelling of "U-Boot" shall be used in all written text
    (documentation, comments in source files etc.).

    Signed-off-by: Bin Meng
    Reviewed-by: Heiko Schocher
    Reviewed-by: Simon Glass
    Reviewed-by: Minkyu Kang

    Bin Meng
     

01 Dec, 2015

1 commit

  • The following patch changed the PFUZE100 swbst register bit definitions
    and broke PMIC configuration on multiple boards, at least on the novena
    and gw_ventana. This patch fixes it.

    commit 8fa46350a4c7dca7710362f6c871098557b934ad
    Author: Peng Fan
    Date: Fri Aug 7 16:43:45 2015 +0800

    power: regulator: add pfuze100 support

    Signed-off-by: Marek Vasut
    Cc: Fabio Estevam
    Cc: Peng Fan
    Cc: Przemyslaw Marczak
    Cc: Stefano Babic
    Cc: Tim Harvey
    Cc: Vagrant Cascadian
    Reviewed-by: Przemyslaw Marczak
    Tested-by: Vagrant Cascadian
    Reviewed-by: Peng Fan
    Acked-by: Tim Harvey

    Marek Vasut
     

13 Nov, 2015

1 commit


13 Sep, 2015

1 commit

  • Remove duplicated SYS_SOC Kconfig entry from board Kconfig,
    because we have this entry in arch/arm/cpu/armv7/mx6/Kconfig.

    Signed-off-by: Peng Fan
    Cc: Stefano Babic
    Cc: Heiko Schocher
    Cc: Christian Gmeiner
    Cc: Stefan Roese
    Cc: Troy Kisky
    Cc: Nikita Kiryanov
    Cc: "Eric Bénard"
    Cc: Fabio Estevam
    Cc: Tim Harvey
    Cc: Marek Vasut
    Cc: Markus Niebel
    Cc: Otavio Salvador
    Acked-by: Stefan Roese
    Acked-by: Marek Vasut
    Acked-by: Christian Gmeiner
    Acked-by: Markus Niebel
    Acked-by: Troy Kisky
    Acked-by: Igor Grinberg

    Peng Fan
     

02 Sep, 2015

1 commit

  • To i.MX6, DDR3 and LPDDR2 is supported, so rename function mx6_dram_cfg
    to mx6_ddr3_cfg and the original mx6_dram_cfg function only is a wrapper.
    The new reimplemented function mx6_dram_cfg only invokes mx6_ddr3_cfg
    when ddr_type is for DDR3. Later we can use ddr_type to initialize
    MMDC for LPDDR2.

    Initialize ddr_type for different boards which enable SPL.

    Signed-off-by: Peng Fan
    Cc: Stefano Babic
    Cc: Tim Harvey
    Cc: Stefan Roese
    Cc: Fabio Estevam
    Reviewed-by: Stefan Roese

    Peng Fan
     

01 Jun, 2015

5 commits


26 May, 2015

2 commits


22 May, 2015

1 commit


19 May, 2015

1 commit