10 Apr, 2019
1 commit
04 Dec, 2018
1 commit
28 Nov, 2018
1 commit
02 Apr, 2018
1 commit
-
This converts the following to Kconfig:
CONFIG_CMD_BLOBSigned-off-by: Simon Glass
[trini: Add imply CMD_BLOB under CHAIN_OF_TRUST]
Signed-off-by: Tom Rini
[Breno: Backported to v2017.03]
Signed-off-by: Breno Lima
Reviewed-by: Ye Li(cherry picked from commit 921eb14d54c612680c3e73d9ddf9e1b9f526905f)
19 Mar, 2018
1 commit
-
All iMX8QM/iMX8QXP MEK ARM2 boards have typec port for CDNS3 USB. This patch
addes board level codes to init and clean up CDNS3 USB gadget driver.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
13 Mar, 2018
1 commit
-
On i.MX7ULP B0, the DDR clock target is increased from 320Mhz to 380Mhz.
We update DDR clock relevant settings to approach the target. But since the
limitation on LCDIF pix clock for HDMI output
(refer commit dba948539edd4611610d9f1fc3711d1d922262ae), we set DDR clock to
352.8Mhz (25.2Mhz * 14) by using the clock path:APLL PFD0 -> DDR CLK -> NIC0 -> NIC1 -> LCDIF clock
To reduce the impact to entire system, the NIC0_DIV and NIC1_DIV are kept,
so the divider 14 is calculated as:
14 = (NIC0_DIV + 1) * (NIC1_DIV + 1) * (LCDIF_PCC_DIV + 1)NIC0_DIV: 1
NIC1_DIV: 0
LCDIF_PCC_DIV: 6APLL and APLL PFD0 settings:
PFD0 FRAC: 27
APLL MULT: 22
APLL NUM: 1
APLL DENOM: 20This patch applies the new settings for both DCD and plugin.
There is no DDR script change on this new frequency.
Overnight memtester is passed.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
24 Feb, 2018
2 commits
-
On i.MX8MQ EVK board, the u-boot only supports the USB host mode on
USB3 port. This patch adds the host support for typec port.
So the typec port now can support both host and device mode.Signed-off-by: Ye Li
Acked-by: Jun Li -
Add a interface to set UFP mode, so when running as device mode, the
board level codes can use it to configure the TCPC port to UFP mode.Since we have supported PD charge for dead battery, so add check before
applying UFP or DFP mode.Signed-off-by: Ye Li
Acked-by: Jun Li
13 Feb, 2018
3 commits
-
On i.MX8MQ EVK board, the SW3A is used for VDD_DRAM supply,
when system enter DSM mode, the DDR is put into retention mode,
the VDD_DRAM supply can be power off to reduce the leakage
current to save power. Set the SW3A mode to APM_OFF mode to power
off the SW3A when PMIC enters standby mode.Signed-off-by: Bai Ping
Reviewed-by: Anson Huang -
Update the lpddr4 training flow on imx8mq evk board.
1. the phy firmware version used is 201709.
2. the PIE image is updated to 201711 version.
3. remove the 400mts and 100mts frequency set point.
4. add the 667mts frequency set point.
5. the ddrc config is also updated accordingly.Signed-off-by: Bai Ping
Reviewed-by: Ye Li -
Adding basic display support for splash screen.
Signed-off-by: Oliver Brown
11 Feb, 2018
1 commit
-
In the board common directory, the CONFIG_TRUST_OF_CHAIN is automatically
enabled once the CONFIG_SECURE_BOOT is set. Since we don't support this
trust chain on all i.MX8 platforms, modify the Kconfig to disable it.Signed-off-by: Ye Li
25 Jan, 2018
2 commits
-
Add board support imx7d multa
Change-Id: I5c50363681d7cb1d93bf8d8a14d93496bd152bcb
Signed-off-by: fang hui -
Write 1 to bit5 of PMIC SW3MODE(0x3f) register to change sw3 mode to avoid DDR
power off. It will avoid DRAM lose data when reset or reboot.This feature is essental for pstore/ramoops work normally.
Change-Id: I92a1e198d57d77ae117d0d49675fc8afffec9656
Signed-off-by: Zhang Bo
17 Jan, 2018
2 commits
-
Since kernel enables both ENET0 and ENET1, so change to reset ENET1
PHY and MAX7322 as well even the configuration is set to use ENET0
in u-boot.Signed-off-by: Ye Li
-
Load HDMI firmware from u-boot.bin instead of
/system partition.Change-Id: I8945940cfe14db50c95a56b8bff2a94990a7fbaf
Signed-off-by: Haoran.Wang
16 Jan, 2018
1 commit
-
Some power delivery source send the source capability by 2 stages:
1st stage send the source capability message with only basic 5V
PDO, after the 5V power session setup, 2nd stage it will send full
source capabilities with all PDOs it can support, in this case, we
should go on to process the following PD source cap to have a new
power session setup.Signed-off-by: Li Jun
10 Jan, 2018
3 commits
-
Enable the TCPC driver for i.MX8MQ EVK board. When booting with dead battery,
the TCPC driver will setup USB PD connection to negotiate the power with PD
power charger.Signed-off-by: Ye Li
Acked-by: Jun Li -
Since the TCPC driver is updated, change the QM/QXP MEK board level codes
accordingly to use new interfaces.
Because the typec circuit on iMX8QM/QXP MEK boards only support power role
as source, so set the CONFIG_USB_TCPC_PD_SINK_DISABLE.Signed-off-by: Ye Li
Acked-by: Jun Li -
To add support for power sink when booting in dead battery, we
have to setup PD connection with PD source and send/receive PD messages
to negotiate a proper voltage and current.This patch refactors the TCPC driver with this new function and also
keep DFP mode support for USB host.Signed-off-by: Ye Li
Acked-by: Jun Li
29 Dec, 2017
2 commits
-
Fix ENET1 build and enablement.
Signed-off-by: Peng Fan
-
Fix build error.
Correct ENET1 enablement, Define CONFIG_FEC_ENET_DEV 1, to enable
ENET1 on Base board.Signed-off-by: Peng Fan
18 Dec, 2017
1 commit
-
Since SCFW switches off the base board at default, we need to turn on it
in u-boot, so that perpherals on base board can work.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
15 Dec, 2017
1 commit
-
ATF will power off all PUs at default, so for USB, we enable
its PU power for both host and device modes in board_usb_init and
disable the power when usb is stop in board_usb_cleanup.Signed-off-by: Ye Li
Reviewed-by: Li Jun
13 Dec, 2017
2 commits
-
Due to the APLL out glitch issue TKT332232, the APLLCFG PLLS bit must be set
to select SCG1 APLL PFD for generating system clock to align with the design.Signed-off-by: Ye Li
Acked-by: Peng Fan -
When using SPL NAND boot, the required malloc memory is larger than SD/eMMC boot.
Since we have used out OCRAM (for ATF) and OCRAM_S, there is no enough memory could be
allocated.The solution is moving the malloc memory pool to DDR. The malloc pool is initialized in
board_init_r, so we moved the VDD_DRAM adjustment and DDR init to board_init_f. Then the DDR
can setup before memory pool initialization. Because the i2c and PMIC driver needs to malloc
data, this change has to enable malloc_f pool by setting CONFIG_MALLOC_F_ADDR to previous
malloc address on OCRAM_S.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
12 Dec, 2017
1 commit
-
Add support for DDR4 board in u-boot.
Main changes are the SD card slot and ddr
typeSigned-off-by: Teo Hall
08 Dec, 2017
3 commits
-
Add board codes, configurations, DTS and DDR initialization codes for the
DDR3L and DDR4 ARM2 boards.Supported modules
- DDR3L ARM2: Two RANK DDR3L, QSPI B, eMMC/SD, RMII ENET, UART.
- DDR4 ARM2: Two RANK DDR4, SD, NAND, RGMII ENET, UART.
NAND read/write/erase is ok in u-boot, NAND SPL boot will be tested later
when tool is ready.Signed-off-by: Ye Li
Acked-by: Peng Fan -
Add 400Mhz, 600Mhz and 800Mhz frequencies for dram pll init function to
support DDR3L/DDR4/LPDDR4.Signed-off-by: Ye Li
-
Due to RGMII interface timing requirement for imx8qm/qxp mek and arm2
board, it needs to enable RX clock delay.It should not depend on HW default status since kernel may clear the
bit only on imx8qm/qxp platforms, then reboot test will cause uboot
networking failed.Signed-off-by: Fugang Duan
05 Dec, 2017
2 commits
-
Add defconfig for tee support;
Enable the TZASC support;
Add env config for tee support.Signed-off-by: Bai Ping
Reviewed-by: Peng Fan -
Add different defconfig for optee;
Enable the TZASC support;
Add env config for tee support.Signed-off-by: Bai Ping
Reviewed-by: Peng Fan
04 Dec, 2017
1 commit
-
1. With this change, no flickering when LCDIF + MIPI-DSI
in 720p60 single display case
2. With this change, no flickering when DCSS in 4kp60
while running 4x memtester at the same timeside effect:
GPU resolve performance downgrade ~20%, no obvious impact
to non-resolve GPU cases.Signed-off-by: Jian Li
01 Dec, 2017
1 commit
-
The EVK board does not use external pull up resistor for SD CD pin, it requires
the pad to be configured as pull up, otherwise the signal level is always low even
the card is not inserted.This patch configures the pad of CD and RESET to pull up to align with kernel,
although there is already a external pull up for RESET.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
20 Nov, 2017
1 commit
-
Add back LPDDR4 performance register settings
Signed-off-by: Peng Fan
10 Nov, 2017
5 commits
-
Support DDR3 ARM2 board.
Most parts are same as LPDDR4 ARM2 board, so share code
with LPDDR4 ARM2.
The DRAM size is 1GB on DDR3 ARM2 board.Signed-off-by: Peng Fan
-
Change to use more generic name for DDR files and public functions used in SPL,
not specified to LPDDR4.Signed-off-by: Ye Li
-
Add different defconfigs.
Enable Trustzone.
Update env to runtime boot OP-TEE.
mx7d arm2 board not supported now.Signed-off-by: Peng Fan
-
Add different defconfigs.
Enable Trustzone.
Update env to runtime boot OP-TEE.Signed-off-by: Peng Fan
-
Add different defconfigs.
Enable Trustzone.
Update env to runtime boot OP-TEE.Signed-off-by: Peng Fan