10 Aug, 2009
22 commits
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Update CHANGELOG
Signed-off-by: Wolfgang Denk
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Signed-off-by: Wolfgang Denk
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tftp.c:294: warning: pointer targets in passing argument 1 of 'strlen'
differ in signednessThis was only visible for the utx8245 board which seems to have DEBUG
enabled.Signed-off-by: Wolfgang Denk
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Remove bogus config.mk entry, fix newline and remove redundant
omap3/config.mkSigned-off-by: Dirk Behme
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Applying two indepenent OMAP3 patches resulted in missing
GPMC_CONFIG_CS0_BASE. Patch "omap3: embedd gpmc_cs into gpmc
config struct" removes GPMC_CONFIG_CS0_BASE, independent patch
"omap3: bug fix for NOR boot support" introduces it's usage.
Re-introduce GPMC_CONFIG_CS0_BASE.Signed-off-by: Dirk Behme
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This is a port of Linux driver for SDHC host controller hardware
found on Freescale's MX2 and MX3 processors. Uses new generic MMC
framework (CONFIG_GENERIC_MMC) and it looks like there are some
problems with a framework (at least on LE cpus). Some of these
problems are addressed in the following patches.Signed-off-by: Ilya Yanok
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Signed-off-by: Alessandro Rubini
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This chip is used in a number of boards manufactured by Calao-Systems
which should be supported soon. This driver provides the necessary
spi_read and spi_write functions necessary to communicate with the chip.Signed-off-by: Albin Tonnerre
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It is recommended to define the macro CONFIG_SYS_64BIT_VSPRINTF
for NAND specific warning removal, same is done in this patchSigned-off-by: Prafulla Wadaskar
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It was brought to our attention that U-Boot contains code derived from the
IBM OpenBIOS source code originally provided with some of the older PowerPC
4xx development boards. As a result, the original license of this code has
been carried in the various files for a number of years in the U-Boot project.IBM is dual-licensing the IBM code contributions already present in U-Boot
under either the terms of the GNU General Public License version 2, or the
original code license already present.Signed-off-by: Josh Boyer
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If the size of a region equal to 4G it can't be represnted in a 32-bit
BAR so we should have marked that case as MEM64.Additionally bump the number of inbound windows up to 4 to handle the
fact that Freescale PPCs that have an implicit window for CCSRBAR.Signed-off-by: Kumar Gala
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The ARM EABI defines new names for GCC helper functions,
and GCC seems to need some new functions as well.This patch is a minimal-invasive approach to fix problems with EABI
conformant tool chains (to be used with "USE_PRIVATE_LIBGCC=yes").Signed-off-by: Wolfgang Denk
Tested-by: Dirk Behme -
An off-by-one error in hush.c resulted in an unintentional free() call
every time a command was executedSigned-off-by: Peter Tyser
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Signed-off-by: Detlev Zundel
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While at it, remove initialization of variables which will be set
before usage in all cases.Signed-off-by: Detlev Zundel
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Add mtc state subcommand description to the
help of mtc command.Remove some newlines in description of commands
for proper help formating.Signed-off-by: Anatolij Gustschin
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Signed-off-by: Grzegorz Bernacki
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Remove bogus newline character that got added to the .name field of
the disk_partition_t structure.Signed-off-by: Wolfgang Denk
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Signed-off-by: Luigi 'Comio' Mantellini
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Signed-off-by: Jens Scharsig
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The only environment type that uses this variable is spi flash, and that is
only because it is reimplementing the common set_default_env() function.
So fix the spi flash code and kill off the default_environment_size in the
process.Signed-off-by: Mike Frysinger
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While we're here, fix the broken #ifdef handling in _exports.h.
Signed-off-by: Mike Frysinger
08 Aug, 2009
10 commits
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This patch provides bug fix, when omap3 uses nor boot.
Signed-off-by: Penda Naveen Kumar
Acked-by: Dirk Behme -
The attached patch corrects an error in the examples/Makefile which
causes the applications in the examples directory to hang on OMAP3
based boards. The current Makefile sets -Ttext during linking to
0x0c100000 which is outside of addressable SDRAM memory. The script
corrects the existing ifeq...else...endif logic to look at the VENDOR
tag rather than the CPU tag.The patch affects the following configs: omap3_beagle_config,
omap3_overo_config, omap3_evm_config, omap3_pandora_config,
omap3_zoom1_config and omap3_zoom2_config.Signed-off-by: Michael Evans
Edited commit message.
Signed-off-by: Wolfgang Denk -
replace variable types in ctrl_structs for omap3 by those with
fixed size (u8, u16, u32).
Additional ifndef-protection is needed by examples which do not
compile when including asm/types.hSigned-off-by: Matthias Ludwig
Signed-off-by: Dirk Behme -
Signed-off-by: Matthias Ludwig
Signed-off-by: Dirk Behme -
Signed-off-by: Matthias Ludwig
Signed-off-by: Dirk Behme -
Based on Intel PRO/1000 Network Driver 7.3.20-k2
Add Intel E1000 PCIE card support. The following cards are added:
INTEL_82571EB_COPPER
INTEL_82571EB_FIBER,
INTEL_82571EB_SERDES
INTEL_82571EB_QUAD_COPPER
INTEL_82571PT_QUAD_COPPER
INTEL_82571EB_QUAD_FIBER
INTEL_82571EB_QUAD_COPPER_LOWPROFILE
INTEL_82571EB_SERDES_DUAL
INTEL_82571EB_SERDES_QUAD
INTEL_82572EI_COPPER
INTEL_82572EI_FIBER
INTEL_82572EI_SERDES
INTEL_82572EI
INTEL_82573E
INTEL_82573E_IAMT
INTEL_82573L
INTEL_82546GB_QUAD_COPPER_KSP3
INTEL_80003ES2LAN_COPPER_DPT
INTEL_80003ES2LAN_SERDES_DPT
INTEL_80003ES2LAN_COPPER_SPT
INTEL_80003ES2LAN_SERDES_SPT82571EB_COPPER dual ports,
82572EI single port,
82572EI_COPPER single port PCIE cards
and
82545EM_COPPER,
82541GI_LF
pci cards are tested on both P2020 board
and MPC8544DS board.Signed-off-by: Roy Zang
Signed-off-by: Ben Warren
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In the previous enetaddr refactoring, the assumption with commit 56b555a644
was that the eth layer would handle the env -> device enetaddr syncing.
This was not the case as eth_initialize() is called only once and the sync
occurs there. So make sure the eth_init() function does the env -> device
sync with every network init.Reported-by: Andrzej Wolski
Signed-off-by: Mike Frysinger
Signed-off-by: Ben Warren -
Minor ./net cleanups - no functional changes
- change #ifdef DEBUG printf(); #endif to just debug()
- changed __FUNCTION__ to __func__
- got rid of extra whitespace between function and opening brace
- removed unnecessary braces on if statementsgcc dead code elimination should make this functionally/size equivalent
when DEBUG is not defined. (confirmed on Blackfin, with gcc 4.3.3).Signed-off-by: Robin Getz
Signed-off-by: Ben Warren
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Embedd chip select configuration into struct for gpmc config
instead of having it completely separated as suggested by
Wolfgang Denk on
http://lists.denx.de/pipermail/u-boot/2009-May/052247.htmlSigned-off-by: Matthias Ludwig
05 Aug, 2009
1 commit
03 Aug, 2009
1 commit
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For some reason the AT91rm9200 lowlevel init writes to a bunch of
reserved or read-only addresses. All the boards seem to define the
value-to-be-written values as zero ... but they shouldn't actually
be writing *anything* there.No documented erratum justifies these accesses. It looks like maybe
some pre-release BDI-2000 setup code has been carried along by cargo
cult programming since at least late 2004 (per GIT history).Here's a patch disabling what seems to be bogosity. Tested on a
csb337; there were no behavioral changes.Signed-off-by: David Brownell
on RM9200ek
Tested-by: Jean-Christophe PLAGNIOL-VILLARD
01 Aug, 2009
2 commits
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Fix a typo in the GCDR(x) macro. It's a good thing no one was using it.
Signed-off-by: David Hunter
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Needed for AT91SAM9260 NOR Boot on Eukrea's CPU9260.
Signed-off-by: Eric Benard
30 Jul, 2009
4 commits
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Signed-off-by: Dirk Eibach
Signed-off-by: Stefan Roese -
This patch is based on a diff created by Phong Vo from AMCC.
Signed-off-by: Phong Vo
Signed-off-by: Stefan Roese -
This patch is based on a diff created by Phong Vo from AMCC.
Signed-off-by: Phong Vo
Signed-off-by: Stefan Roese -
Some Canyonlands boards are equipped with different SODIMM's. This is no
problem with the "normal" NOR booting Canyonlands U-Boot, since it
automatically detects the SODIMM's via SPD data and correctly configures
them. But the NAND booting version is different. Here we only have 4k
of image size to completely setup the hardware, including DDR2 setup.
So we need to use a fixed DDR2 setup here. This doesn't work for different
SODIMM's right now.Currently only this Crucial SODIMM is support:
CT6464AC667.8FB (dual ranked)Now some boards are shipped with this SODIMM:
CT6464AC667.4FE (single ranked)This patch now supports both SODIMM's by configuring first for the dual
ranked DIMM. A quick shows, if this module is really installed. If this test
fails, the DDR2 controller is re-configured for the single
ranked SODIMM.Tested with those SODIMM's:
CT6464AC667.8FB (dual ranked)
CT6464AC667.4FE (single ranked)Signed-off-by: Stefan Roese
