23 Dec, 2010
1 commit
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Signed-off-by: Wolfgang Denk
21 Dec, 2010
1 commit
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It can be optimised out by the compiler otherwise resulting
in obscure errors like a board not booting.This has been documented in README since 2006 when these were
first fixed up for GCC 4.x.Signed-off-by: John Rigby
Fix some additional places.
Signed-off-by: Wolfgang Denk
Acked-By: Albert ARIBAUD
19 Dec, 2010
8 commits
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Convert the variable omap3_evm_version to u32 to work around
some broken linkers from older tool chains. E.g. CodeSourcery's
2009q1-203 ld 2.19.51.20090205. Without this, these linkers
stop linking 'omap3_evm' or at least issue a warning. Likearm-none-linux-gnueabi-ld: section .bss [8003f5e0 -> 8007e337] overlaps section .rel.dyn [8003f5e0 -> 80044e57]
arm-none-linux-gnueabi-ld: section .dynsym [80044e58 -> 80044ef7] overlaps section.bss [8003f5e0 -> 8007e337]
arm-none-linux-gnueabi-ld: u-boot: section .bss vma 0x8003f5e0 overlaps previous sectionsCC: Sanjeev Premi
Signed-off-by: Dirk Behme -
The current code use all the voltage range support by the host
controller to do the validation. This will cause problem when
the host supports Low Voltage Range. Change the validation
voltage to be based on board setup.Signed-off-by: Li Yang
Tested-by: Stefano Babic
Signed-off-by: Kumar Gala -
The max clock of MMC is 52MHz
Signed-off-by: Jerry Huang
Tested-by: Stefano Babic
Signed-off-by: Kumar Gala -
After booting the u-boot, and first using some SD card (such as Sandisk 2G SD
card), because the field 'clock' of struct mmc is zero, this will cause
the read transfer is always active and SDHC DATA line is always active,
therefore, driver can't handle the next command.Therefore, we use mmc_set_clock to setup both the data structure and HW
to the initial clock speed of 400000Hz.Signed-off-by: Jerry Huang
Tested-by: Stefano Babic
Signed-off-by: Kumar Gala -
The current code use all the voltage range support by the host
controller to do the validation. This will cause problem when
the host supports Low Voltage Range. Change the validation
voltage to be based on board setup.Signed-off-by: Li Yang
Tested-by: Stefano Babic
Signed-off-by: Kumar Gala -
The max clock of MMC is 52MHz
Signed-off-by: Jerry Huang
Tested-by: Stefano Babic
Signed-off-by: Kumar Gala -
After booting the u-boot, and first using some SD card (such as Sandisk 2G SD
card), because the field 'clock' of struct mmc is zero, this will cause
the read transfer is always active and SDHC DATA line is always active,
therefore, driver can't handle the next command.Therefore, we use mmc_set_clock to setup both the data structure and HW
to the initial clock speed of 400000Hz.Signed-off-by: Jerry Huang
Tested-by: Stefano Babic
Signed-off-by: Kumar Gala
18 Dec, 2010
3 commits
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Fix clock divider for COM57H5M10XRC display.
The previous setting caused flicker.Tested on Qong (EVBLite with COM57H5M10XRC).
Signed-off-by: Stefano Babic
Acked-by: Wolfgang Denk
Acked-by: Anatolij Gustschin
17 Dec, 2010
19 commits
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Signed-off-by: Wolfgang Denk
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Signed-off-by: Wolfgang Denk
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Add ARM Relocation Support
Signed-off-by: Sandeep Paulraj
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Add ARM Relocation Support
Signed-off-by: Sandeep Paulraj
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Add ARM Relocation Support
Signed-off-by: Sandeep Paulraj
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Add ARM Relocation Support
Signed-off-by: Sandeep Paulraj
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Some DaVinci boards are using flags that are no longer valid
So remove them.Signed-off-by: Sandeep Paulraj
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Signed-off-by: Guido Classen
Signed-off-by: Reinhard Meyer -
Signed-off-by: Reinhard Meyer
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Signed-off-by: Asen Dimov
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Signed-off-by: Asen Dimov
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Signed-off-by: Asen Dimov
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Signed-off-by: Asen Dimov
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Signed-off-by: Asen Dimov
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Signed-off-by: Asen Dimov
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Recent GCC (4.4+) performs out-of-line epilogues in some cases, when
optimizing for size. It causes a link error for _restgpr_30_x (and similar)
if libgcc is not linked.It actually increases size with very small binaries, due to the fixed size
of the out-of-line code, and not having any functions that actually need to
restore more than 2 or 3 registers. But I don't see a way to turn it off,
other than asking GCC to optimize for speed -- which may also increase
size for some boards.Signed-off-by: Scott Wood
Acked-by: Kim Phillips
Acked-by: Wolfgang Denk
15 Dec, 2010
1 commit
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This patch fixes the acadia_nand and kilauea_nand linker scripts
which have been missing in commit ee8028b7 [ppc4xx: Cleanup for
partial linking and --gc-sections]Signed-off-by: Stefan Roese
Cc: Bernhard Weirich
14 Dec, 2010
5 commits
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Make code build with older tool chains.
Signed-off-by: Wolfgang Denk
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This patch fix a problem for the pcie enumeration for mpc83xx cpus. Without
this we will not get correct value in hose->regions[...].The pointer *reg in function mpc83xx_pcie_init_bus() shall not be changed.
Because we will use this pointer as a parameter to call function
mpc83xx_pcie_register_hose().Signed-off-by: Baidu Boy
Signed-off-by: Kim Phillips -
On the P1022, the pins which drive the video display (DIU) are muxed with the
local bus controller (LBC), so if the DIU is active, the pins need to be
temporarily muxed to LBC whenever accessing NOR flash.The code which handled this transition is checking and changing the wrong
bits in PMUXCR.Also add a follow-up read after a write to NOR flash if we're going to
mux back to DIU after the write, as described in the P1022 RM.Signed-off-by: Timur Tabi
Signed-off-by: Kumar Gala
13 Dec, 2010
2 commits
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eSDHC host controller reset results in clearing of snoop bit also.
This patch sets the SNOOP bit after the completion of host controller reset.
Without this patch mmc reads are not consistent.Signed-off-by: P.V.Suresh
Signed-off-by: Kumar Gala -
According to Freescale reference manuals (eg section "13.4.4.2
Programming the UPMs" of the P4080 Reference Manual):"Since the result of any update to the MxMR/MDR register must be in
effect before the dummy read or write to the UPM region, a write to
MxMR/MDR should be followed immediately by a read of MxMR/MDR."The UPM on a custom P4080-based board did not work without performing
a read of MxMR/MDR after a write.Signed-off-by: John Schmoller
Signed-off-by: Peter Tyser
Acked-by: Scott Wood
Signed-off-by: Kumar Gala
