Commit 0e9a60101d689b7c923cadb510bf8d785e9a41fe
Committed by
Jacob Stiffler
1 parent
39f6cde27d
Exists in
smarc-ti-linux-3.14.y
and in
1 other branch
DRA7: IVA: Add IVA OPP_HIGH config support
Enable IVA OPP_HIGH as default opp instead of OPP_NOM based on a menuconfig option (CONFIG_IVA_OPP_HIGH). menuconfig entry: -> Device Drivers -> Common Clock Framework Signed-off-by: Ravikumar Kattekola <rk@ti.com> Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
Showing 2 changed files with 15 additions and 0 deletions Side-by-side Diff
drivers/clk/Kconfig
... | ... | @@ -99,6 +99,8 @@ |
99 | 99 | depends on ARM64 |
100 | 100 | ---help--- |
101 | 101 | Sypport for the APM X-Gene SoC reference, PLL, and device clocks. |
102 | + This driver supports TI Palmas devices 32KHz output KG and KG_AUDIO | |
103 | + using common clock framework. | |
102 | 104 | |
103 | 105 | config COMMON_CLK_KEYSTONE |
104 | 106 | tristate "Clock drivers for Keystone based SOCs" |
... | ... | @@ -108,6 +110,13 @@ |
108 | 110 | a power sleep control module that gate the clock to the IPs and PLLs. |
109 | 111 | |
110 | 112 | source "drivers/clk/qcom/Kconfig" |
113 | + | |
114 | +config IVA_OPP_HIGH | |
115 | + bool "IVA DPLL lock for HIGH_OPP" | |
116 | + depends on SOC_DRA7XX | |
117 | + default n | |
118 | + help | |
119 | + Lock IVA DPLL for HIGH OPP (532 MHz) | |
111 | 120 | |
112 | 121 | endmenu |
113 | 122 |
drivers/clk/ti/clk-7xx.c
... | ... | @@ -22,8 +22,14 @@ |
22 | 22 | #define DRA7_DPLL_DSP_GFCLK_NOMFREQ 600000000 |
23 | 23 | #define DRA7_DPLL_EVE_GCLK_NOMFREQ 400000000 |
24 | 24 | #define DRA7_ATL2_DEFFREQ 5644800 |
25 | + | |
26 | +#ifdef CONFIG_IVA_OPP_HIGH | |
27 | +#define DRA7_DPLL_IVA_DEFFREQ 1064000000 | |
28 | +#define DRA7_DPLL_IVA_GFCLK_NOMFREQ 532000000 | |
29 | +#else | |
25 | 30 | #define DRA7_DPLL_IVA_DEFFREQ 776666666 |
26 | 31 | #define DRA7_DPLL_IVA_GFCLK_NOMFREQ 388333333 |
32 | +#endif | |
27 | 33 | |
28 | 34 | #define DRA7_ATL_DEFFREQ 5644800 |
29 | 35 | #define DRA7_DPLL_USB_DEFFREQ 960000000 |