Commit 7322a1dde616aa0e031192fc98a1c6e85bcef424
Committed by
Greg Kroah-Hartman
1 parent
4199f74e53
ARM: dts: zynq: Enable PL clocks for Parallella
commit 92c9e0c780e61f821ab8a08f0d4d4fd33ba1197c upstream. The Parallella board comes with a U-Boot bootloader that loads one of two predefined FPGA bitstreams before booting the kernel. Both define an AXI interface to the on-board Epiphany processor. Enable clocks FCLK0..FCLK3 for the Programmable Logic by default. Otherwise accessing, e.g., the ESYSRESET register freezes the board, as seen with the Epiphany SDK tools e-reset and e-hw-rev, using /dev/mem. Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Olof Johansson <olof@lixom.net> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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