Eric Lee / smarc-ti-linux-kernel

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Commit 7f5dada0d5890fd3c4eee140f9489ef32f1a3ae6

Authored by Andi Kleen
Committed by Greg Kroah-Hartman
1 parent 78a458e361

perf/x86/uncore/hsw-ep: Handle systems with only two SBOXes 

commit 5306c31c5733cb4a79cc002e0c3ad256fd439614 upstream.

There was another report of a boot failure with a #GP fault in the
uncore SBOX initialization. The earlier work around was not enough
for this system.

The boot was failing while trying to initialize the third SBOX.

This patch detects parts with only two SBOXes and limits the number
of SBOX units to two there.

Stable material, as it affects boot problems on 3.18.

Tested-by: Andreas Oehler <andreas@oehler-net.de>
Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Yan, Zheng <zheng.z.yan@intel.com>
Link: http://lkml.kernel.org/r/1420583675-9163-1-git-send-email-andi@firstfloor.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

Showing 2 changed files with 18 additions and 1 deletions Side-by-side Diff

arch/x86/kernel/cpu/perf_event_intel_uncore.h
Diff comments   View file @ 7f5dada
... ... @@ -17,7 +17,7 @@
17 17 #define UNCORE_PCI_DEV_TYPE(data) ((data >> 8) & 0xff)
18 18 #define UNCORE_PCI_DEV_IDX(data) (data & 0xff)
19 19 #define UNCORE_EXTRA_PCI_DEV 0xff
20   -#define UNCORE_EXTRA_PCI_DEV_MAX 2
  20 +#define UNCORE_EXTRA_PCI_DEV_MAX 3
21 21  
22 22 /* support up to 8 sockets */
23 23 #define UNCORE_SOCKET_MAX 8
arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c
Diff comments   View file @ 7f5dada
... ... @@ -887,6 +887,7 @@
887 887 enum {
888 888 SNBEP_PCI_QPI_PORT0_FILTER,
889 889 SNBEP_PCI_QPI_PORT1_FILTER,
  890 + HSWEP_PCI_PCU_3,
890 891 };
891 892  
892 893 static int snbep_qpi_hw_config(struct intel_uncore_box *box, struct perf_event *event)
... ... @@ -2022,6 +2023,17 @@
2022 2023 {
2023 2024 if (hswep_uncore_cbox.num_boxes > boot_cpu_data.x86_max_cores)
2024 2025 hswep_uncore_cbox.num_boxes = boot_cpu_data.x86_max_cores;
  2026 +
  2027 + /* Detect 6-8 core systems with only two SBOXes */
  2028 + if (uncore_extra_pci_dev[0][HSWEP_PCI_PCU_3]) {
  2029 + u32 capid4;
  2030 +
  2031 + pci_read_config_dword(uncore_extra_pci_dev[0][HSWEP_PCI_PCU_3],
  2032 + 0x94, &capid4);
  2033 + if (((capid4 >> 6) & 0x3) == 0)
  2034 + hswep_uncore_sbox.num_boxes = 2;
  2035 + }
  2036 +
2025 2037 uncore_msr_uncores = hswep_msr_uncores;
2026 2038 }
2027 2039  
... ... @@ -2278,6 +2290,11 @@
2278 2290 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f96),
2279 2291 .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV,
2280 2292 SNBEP_PCI_QPI_PORT1_FILTER),
  2293 + },
  2294 + { /* PCU.3 (for Capability registers) */
  2295 + PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fc0),
  2296 + .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV,
  2297 + HSWEP_PCI_PCU_3),
2281 2298 },
2282 2299 { /* end: all zeroes */ }
2283 2300 };