Commit ae8f5041a5422016ae21d6f9d0bfa2caa839590f
Exists in
ti-lsk-linux-4.1.y
and in
10 other branches
Merge tag 'mvebu-fixes-3.18' of git://git.infradead.org/linux-mvebu into fixes
Merge "mvebu fixes for v3.18" from Jason Cooper: - Armada XP - Generalize i2c quirk - orion - Fix irq storm caused by specific sequence of request_irq * tag 'mvebu-fixes-3.18' of git://git.infradead.org/linux-mvebu: ARM: orion: Fix for certain sequence of request_irq can cause irq storm ARM: mvebu: armada xp: Generalize use of i2c quirk
Showing 2 changed files Side-by-side Diff
arch/arm/mach-mvebu/board-v7.c
... | ... | @@ -188,7 +188,7 @@ |
188 | 188 | |
189 | 189 | static void __init mvebu_dt_init(void) |
190 | 190 | { |
191 | - if (of_machine_is_compatible("plathome,openblocks-ax3-4")) | |
191 | + if (of_machine_is_compatible("marvell,armadaxp")) | |
192 | 192 | i2c_quirk(); |
193 | 193 | if (of_machine_is_compatible("marvell,a375-db")) { |
194 | 194 | external_abort_quirk(); |
arch/arm/plat-orion/gpio.c
... | ... | @@ -497,6 +497,34 @@ |
497 | 497 | #define orion_gpio_dbg_show NULL |
498 | 498 | #endif |
499 | 499 | |
500 | +static void orion_gpio_unmask_irq(struct irq_data *d) | |
501 | +{ | |
502 | + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
503 | + struct irq_chip_type *ct = irq_data_get_chip_type(d); | |
504 | + u32 reg_val; | |
505 | + u32 mask = d->mask; | |
506 | + | |
507 | + irq_gc_lock(gc); | |
508 | + reg_val = irq_reg_readl(gc->reg_base + ct->regs.mask); | |
509 | + reg_val |= mask; | |
510 | + irq_reg_writel(reg_val, gc->reg_base + ct->regs.mask); | |
511 | + irq_gc_unlock(gc); | |
512 | +} | |
513 | + | |
514 | +static void orion_gpio_mask_irq(struct irq_data *d) | |
515 | +{ | |
516 | + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
517 | + struct irq_chip_type *ct = irq_data_get_chip_type(d); | |
518 | + u32 mask = d->mask; | |
519 | + u32 reg_val; | |
520 | + | |
521 | + irq_gc_lock(gc); | |
522 | + reg_val = irq_reg_readl(gc->reg_base + ct->regs.mask); | |
523 | + reg_val &= ~mask; | |
524 | + irq_reg_writel(reg_val, gc->reg_base + ct->regs.mask); | |
525 | + irq_gc_unlock(gc); | |
526 | +} | |
527 | + | |
500 | 528 | void __init orion_gpio_init(struct device_node *np, |
501 | 529 | int gpio_base, int ngpio, |
502 | 530 | void __iomem *base, int mask_offset, |
... | ... | @@ -565,8 +593,8 @@ |
565 | 593 | ct = gc->chip_types; |
566 | 594 | ct->regs.mask = ochip->mask_offset + GPIO_LEVEL_MASK_OFF; |
567 | 595 | ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW; |
568 | - ct->chip.irq_mask = irq_gc_mask_clr_bit; | |
569 | - ct->chip.irq_unmask = irq_gc_mask_set_bit; | |
596 | + ct->chip.irq_mask = orion_gpio_mask_irq; | |
597 | + ct->chip.irq_unmask = orion_gpio_unmask_irq; | |
570 | 598 | ct->chip.irq_set_type = gpio_irq_set_type; |
571 | 599 | ct->chip.name = ochip->chip.label; |
572 | 600 | |
... | ... | @@ -575,8 +603,8 @@ |
575 | 603 | ct->regs.ack = GPIO_EDGE_CAUSE_OFF; |
576 | 604 | ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; |
577 | 605 | ct->chip.irq_ack = irq_gc_ack_clr_bit; |
578 | - ct->chip.irq_mask = irq_gc_mask_clr_bit; | |
579 | - ct->chip.irq_unmask = irq_gc_mask_set_bit; | |
606 | + ct->chip.irq_mask = orion_gpio_mask_irq; | |
607 | + ct->chip.irq_unmask = orion_gpio_unmask_irq; | |
580 | 608 | ct->chip.irq_set_type = gpio_irq_set_type; |
581 | 609 | ct->handler = handle_edge_irq; |
582 | 610 | ct->chip.name = ochip->chip.label; |