Eric Lee / smarc-ti-linux-kernel

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Commit bc5c48b656b5000536340c403b42ea52f5965ccf

Authored by Vincent Minet
Committed by Greg Kroah-Hartman
1 parent 1c28f6e997
Exists in ti-linux-3.14.y and in 2 other branches processor-sdk-linux-01.00.00, smarc-ti-linux-3.14.y

intel_pstate: Set CPU number before accessing MSRs 

commit 179e8471673ce0249cd4ecda796008f7757e5bad upstream.

Ensure that cpu->cpu is set before writing MSR_IA32_PERF_CTL during CPU
initialization. Otherwise only cpu0 has its P-state set and all other
cores are left with their values unchanged.

In most cases, this is not too serious because the P-states will be set
correctly when the timer function is run.  But when the default governor
is set to performance, the per-CPU current_pstate stays the same forever
and no attempts are made to write the MSRs again.

Signed-off-by: Vincent Minet <vincent@vincent-minet.net>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

Showing 1 changed file with 1 additions and 2 deletions Side-by-side Diff

drivers/cpufreq/intel_pstate.c
Diff comments   View file @ bc5c48b
... ... @@ -709,9 +709,8 @@
709 709  
710 710 cpu = all_cpu_data[cpunum];
711 711  
712   - intel_pstate_get_cpu_pstates(cpu);
713   -
714 712 cpu->cpu = cpunum;
  713 + intel_pstate_get_cpu_pstates(cpu);
715 714  
716 715 init_timer_deferrable(&cpu->timer);
717 716 cpu->timer.function = intel_pstate_timer_func;