Eric Lee / smarc-ti-linux-kernel

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Commit c5ed98b6ae79545284b7855a07ded32934865a6d

Authored by Russell King
1 parent 45da7b0451
Exists in master and in 13 other branches dlt-processor-sdk-linux-03.00.00.04, processor-sdk-linux-02.00.01, smarc-ti-linux-3.15.y, smarc-ti-lsk-linux-4.1.y, smarct3x-processor-sdk-04.01.00.06, smarct3x-processor-sdk-linux-02.00.01, smarct3x-processor-sdk-linux-03.00.00.04, smarct4x-800-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-04.01.00.06, smarct4x-processor-sdk-linux-02.00.01, smarct4x-processor-sdk-linux-03.00.00.04, ti-linux-3.15.y, ti-lsk-linux-4.1.y

dmaengine: omap-dma: provide register read/write functions 

Provide a pair of channel register accessors, and a pair of global
accessors for non-channel specific registers.

Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

Showing 1 changed file with 61 additions and 41 deletions Side-by-side Diff

drivers/dma/omap-dma.c
Diff comments   View file @ c5ed98b
... ... @@ -170,12 +170,32 @@
170 170 kfree(container_of(vd, struct omap_desc, vd));
171 171 }
172 172  
  173 +static void omap_dma_glbl_write(struct omap_dmadev *od, unsigned reg, unsigned val)
  174 +{
  175 + od->plat->dma_write(val, reg, 0);
  176 +}
  177 +
  178 +static unsigned omap_dma_glbl_read(struct omap_dmadev *od, unsigned reg)
  179 +{
  180 + return od->plat->dma_read(reg, 0);
  181 +}
  182 +
  183 +static void omap_dma_chan_write(struct omap_chan *c, unsigned reg, unsigned val)
  184 +{
  185 + c->plat->dma_write(val, reg, c->dma_ch);
  186 +}
  187 +
  188 +static unsigned omap_dma_chan_read(struct omap_chan *c, unsigned reg)
  189 +{
  190 + return c->plat->dma_read(reg, c->dma_ch);
  191 +}
  192 +
173 193 static void omap_dma_clear_csr(struct omap_chan *c)
174 194 {
175 195 if (dma_omap1())
176   - c->plat->dma_read(CSR, c->dma_ch);
  196 + omap_dma_chan_read(c, CSR);
177 197 else
178   - c->plat->dma_write(~0, CSR, c->dma_ch);
  198 + omap_dma_chan_write(c, CSR, ~0);
179 199 }
180 200  
181 201 static void omap_dma_start(struct omap_chan *c, struct omap_desc *d)
182 202  
183 203  
184 204  
... ... @@ -183,17 +203,17 @@
183 203 struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device);
184 204  
185 205 if (__dma_omap15xx(od->plat->dma_attr))
186   - c->plat->dma_write(0, CPC, c->dma_ch);
  206 + omap_dma_chan_write(c, CPC, 0);
187 207 else
188   - c->plat->dma_write(0, CDAC, c->dma_ch);
  208 + omap_dma_chan_write(c, CDAC, 0);
189 209  
190 210 omap_dma_clear_csr(c);
191 211  
192 212 /* Enable interrupts */
193   - c->plat->dma_write(d->cicr, CICR, c->dma_ch);
  213 + omap_dma_chan_write(c, CICR, d->cicr);
194 214  
195 215 /* Enable channel */
196   - c->plat->dma_write(d->ccr | CCR_ENABLE, CCR, c->dma_ch);
  216 + omap_dma_chan_write(c, CCR, d->ccr | CCR_ENABLE);
197 217 }
198 218  
199 219 static void omap_dma_stop(struct omap_chan *c)
200 220  
201 221  
202 222  
203 223  
204 224  
205 225  
... ... @@ -202,27 +222,27 @@
202 222 uint32_t val;
203 223  
204 224 /* disable irq */
205   - c->plat->dma_write(0, CICR, c->dma_ch);
  225 + omap_dma_chan_write(c, CICR, 0);
206 226  
207 227 omap_dma_clear_csr(c);
208 228  
209   - val = c->plat->dma_read(CCR, c->dma_ch);
  229 + val = omap_dma_chan_read(c, CCR);
210 230 if (od->plat->errata & DMA_ERRATA_i541 && val & CCR_TRIGGER_SRC) {
211 231 uint32_t sysconfig;
212 232 unsigned i;
213 233  
214   - sysconfig = c->plat->dma_read(OCP_SYSCONFIG, c->dma_ch);
  234 + sysconfig = omap_dma_glbl_read(od, OCP_SYSCONFIG);
215 235 val = sysconfig & ~DMA_SYSCONFIG_MIDLEMODE_MASK;
216 236 val |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE);
217   - c->plat->dma_write(val, OCP_SYSCONFIG, c->dma_ch);
  237 + omap_dma_glbl_write(od, OCP_SYSCONFIG, val);
218 238  
219   - val = c->plat->dma_read(CCR, c->dma_ch);
  239 + val = omap_dma_chan_read(c, CCR);
220 240 val &= ~CCR_ENABLE;
221   - c->plat->dma_write(val, CCR, c->dma_ch);
  241 + omap_dma_chan_write(c, CCR, val);
222 242  
223 243 /* Wait for sDMA FIFO to drain */
224 244 for (i = 0; ; i++) {
225   - val = c->plat->dma_read(CCR, c->dma_ch);
  245 + val = omap_dma_chan_read(c, CCR);
226 246 if (!(val & (CCR_RD_ACTIVE | CCR_WR_ACTIVE)))
227 247 break;
228 248  
229 249  
230 250  
231 251  
... ... @@ -237,23 +257,23 @@
237 257 "DMA drain did not complete on lch %d\n",
238 258 c->dma_ch);
239 259  
240   - c->plat->dma_write(sysconfig, OCP_SYSCONFIG, c->dma_ch);
  260 + omap_dma_glbl_write(od, OCP_SYSCONFIG, sysconfig);
241 261 } else {
242 262 val &= ~CCR_ENABLE;
243   - c->plat->dma_write(val, CCR, c->dma_ch);
  263 + omap_dma_chan_write(c, CCR, val);
244 264 }
245 265  
246 266 mb();
247 267  
248 268 if (!__dma_omap15xx(od->plat->dma_attr) && c->cyclic) {
249   - val = c->plat->dma_read(CLNK_CTRL, c->dma_ch);
  269 + val = omap_dma_chan_read(c, CLNK_CTRL);
250 270  
251 271 if (dma_omap1())
252 272 val |= 1 << 14; /* set the STOP_LNK bit */
253 273 else
254 274 val &= ~CLNK_CTRL_ENABLE_LNK;
255 275  
256   - c->plat->dma_write(val, CLNK_CTRL, c->dma_ch);
  276 + omap_dma_chan_write(c, CLNK_CTRL, val);
257 277 }
258 278 }
259 279  
... ... @@ -273,11 +293,11 @@
273 293 cxfi = CSFI;
274 294 }
275 295  
276   - c->plat->dma_write(sg->addr, cxsa, c->dma_ch);
277   - c->plat->dma_write(0, cxei, c->dma_ch);
278   - c->plat->dma_write(0, cxfi, c->dma_ch);
279   - c->plat->dma_write(sg->en, CEN, c->dma_ch);
280   - c->plat->dma_write(sg->fn, CFN, c->dma_ch);
  296 + omap_dma_chan_write(c, cxsa, sg->addr);
  297 + omap_dma_chan_write(c, cxei, 0);
  298 + omap_dma_chan_write(c, cxfi, 0);
  299 + omap_dma_chan_write(c, CEN, sg->en);
  300 + omap_dma_chan_write(c, CFN, sg->fn);
281 301  
282 302 omap_dma_start(c, d);
283 303 }
284 304  
... ... @@ -305,9 +325,9 @@
305 325 */
306 326 mb();
307 327  
308   - c->plat->dma_write(d->ccr, CCR, c->dma_ch);
  328 + omap_dma_chan_write(c, CCR, d->ccr);
309 329 if (dma_omap1())
310   - c->plat->dma_write(d->ccr >> 16, CCR2, c->dma_ch);
  330 + omap_dma_chan_write(c, CCR2, d->ccr >> 16);
311 331  
312 332 if (d->dir == DMA_DEV_TO_MEM) {
313 333 cxsa = CSSA;
... ... @@ -319,11 +339,11 @@
319 339 cxfi = CDFI;
320 340 }
321 341  
322   - c->plat->dma_write(d->dev_addr, cxsa, c->dma_ch);
323   - c->plat->dma_write(0, cxei, c->dma_ch);
324   - c->plat->dma_write(d->fi, cxfi, c->dma_ch);
325   - c->plat->dma_write(d->csdp, CSDP, c->dma_ch);
326   - c->plat->dma_write(d->clnk_ctrl, CLNK_CTRL, c->dma_ch);
  342 + omap_dma_chan_write(c, cxsa, d->dev_addr);
  343 + omap_dma_chan_write(c, cxei, 0);
  344 + omap_dma_chan_write(c, cxfi, d->fi);
  345 + omap_dma_chan_write(c, CSDP, d->csdp);
  346 + omap_dma_chan_write(c, CLNK_CTRL, d->clnk_ctrl);
327 347  
328 348 omap_dma_start_sg(c, d, 0);
329 349 }
330 350  
331 351  
... ... @@ -437,12 +457,12 @@
437 457 dma_addr_t addr;
438 458  
439 459 if (__dma_omap15xx(od->plat->dma_attr))
440   - addr = c->plat->dma_read(CPC, c->dma_ch);
  460 + addr = omap_dma_chan_read(c, CPC);
441 461 else
442   - addr = c->plat->dma_read(CSAC, c->dma_ch);
  462 + addr = omap_dma_chan_read(c, CSAC);
443 463  
444 464 if (od->plat->errata & DMA_ERRATA_3_3 && addr == 0)
445   - addr = c->plat->dma_read(CSAC, c->dma_ch);
  465 + addr = omap_dma_chan_read(c, CSAC);
446 466  
447 467 if (!__dma_omap15xx(od->plat->dma_attr)) {
448 468 /*
449 469  
450 470  
... ... @@ -450,14 +470,14 @@
450 470 * not been started (no data has been transferred so far).
451 471 * Return the programmed source start address in this case.
452 472 */
453   - if (c->plat->dma_read(CDAC, c->dma_ch))
454   - addr = c->plat->dma_read(CSAC, c->dma_ch);
  473 + if (omap_dma_chan_read(c, CDAC))
  474 + addr = omap_dma_chan_read(c, CSAC);
455 475 else
456   - addr = c->plat->dma_read(CSSA, c->dma_ch);
  476 + addr = omap_dma_chan_read(c, CSSA);
457 477 }
458 478  
459 479 if (dma_omap1())
460   - addr |= c->plat->dma_read(CSSA, c->dma_ch) & 0xffff0000;
  480 + addr |= omap_dma_chan_read(c, CSSA) & 0xffff0000;
461 481  
462 482 return addr;
463 483 }
464 484  
465 485  
466 486  
467 487  
... ... @@ -468,27 +488,27 @@
468 488 dma_addr_t addr;
469 489  
470 490 if (__dma_omap15xx(od->plat->dma_attr))
471   - addr = c->plat->dma_read(CPC, c->dma_ch);
  491 + addr = omap_dma_chan_read(c, CPC);
472 492 else
473   - addr = c->plat->dma_read(CDAC, c->dma_ch);
  493 + addr = omap_dma_chan_read(c, CDAC);
474 494  
475 495 /*
476 496 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
477 497 * read before the DMA controller finished disabling the channel.
478 498 */
479 499 if (!__dma_omap15xx(od->plat->dma_attr) && addr == 0) {
480   - addr = c->plat->dma_read(CDAC, c->dma_ch);
  500 + addr = omap_dma_chan_read(c, CDAC);
481 501 /*
482 502 * CDAC == 0 indicates that the DMA transfer on the channel has
483 503 * not been started (no data has been transferred so far).
484 504 * Return the programmed destination start address in this case.
485 505 */
486 506 if (addr == 0)
487   - addr = c->plat->dma_read(CDSA, c->dma_ch);
  507 + addr = omap_dma_chan_read(c, CDSA);
488 508 }
489 509  
490 510 if (dma_omap1())
491   - addr |= c->plat->dma_read(CDSA, c->dma_ch) & 0xffff0000;
  511 + addr |= omap_dma_chan_read(c, CDSA) & 0xffff0000;
492 512  
493 513 return addr;
494 514 }