Eric Lee / smarc-ti-linux-kernel | Embedian Git Server

Commit e3db2217f3cdabf170ed2131831b42aa0878a0ac

Authored by Olof Johansson 2015-01-09 06:43:00 +0800

Exists in ti-lsk-linux-4.1.y and in 10 other branches

Merge tag 'omap-for-v3.19/fixes-rc1' of git://git.kernel.org/pub/scm/linux/kerne…

…l/git/tmlind/linux-omap into fixes

Merge "omap fixes against v3.19-rc1" from Tony Lindgren:

Fixes for omaps mostly to deal with dra7 timer issues
and hypervisor mode. The other fixes are minor fixes for
various boards. The summary of the fixes is:

- Fix real-time counter rate typos for some frequencies
- Fix counter frequency drift for am572x
- Fix booting of secondary CPU in HYP mode
- Fix n900 board name for legacy user space
- Fix cpufreq in omap2plus_defconfig after Kconfig change
- Fix dra7 qspi partitions

And also, let's re-enable smc91x on some n900 boards that
we have sitting in a few test boot systems after the boot
loader dependencies got fixed.

* tag 'omap-for-v3.19/fixes-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: dts: Revert disabling of smc91x for n900
  ARM: dts: dra7-evm: fix qspi device tree partition size
  ARM: omap2plus_defconfig: use CONFIG_CPUFREQ_DT
  ARM: OMAP2+: Fix n900 board name for legacy user space
  ARM: omap5/dra7xx: Enable booting secondary CPU in HYP mode
  ARM: dra7xx: Fix counter frequency drift for AM572x errata i856
  ARM: omap5/dra7xx: Fix frequency typos

Signed-off-by: Olof Johansson <olof@lixom.net>

Showing 9 changed files Inline Diff

arch/arm/boot/dts/dra7-evm.dts
arch/arm/boot/dts/omap3-n900.dts
arch/arm/configs/omap2plus_defconfig
arch/arm/mach-omap2/board-generic.c
arch/arm/mach-omap2/common.h
arch/arm/mach-omap2/control.h
arch/arm/mach-omap2/omap-headsmp.S
arch/arm/mach-omap2/omap-smp.c
arch/arm/mach-omap2/timer.c

arch/arm/boot/dts/dra7-evm.dts

Diff comments View file @ e3db221

1	/*	1	/*
2	* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/	2	* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3	*	3	*
4	* This program is free software; you can redistribute it and/or modify	4	* This program is free software; you can redistribute it and/or modify
5	* it under the terms of the GNU General Public License version 2 as	5	* it under the terms of the GNU General Public License version 2 as
6	* published by the Free Software Foundation.	6	* published by the Free Software Foundation.
7	*/	7	*/
8	/dts-v1/;	8	/dts-v1/;
9		9
10	#include "dra74x.dtsi"	10	#include "dra74x.dtsi"
11	#include <dt-bindings/gpio/gpio.h>	11	#include <dt-bindings/gpio/gpio.h>
12		12
13	/ {	13	/ {
14	model = "TI DRA742";	14	model = "TI DRA742";
15	compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";	15	compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
16		16
17	memory {	17	memory {
18	device_type = "memory";	18	device_type = "memory";
19	reg = <0x80000000 0x60000000>; /* 1536 MB */	19	reg = <0x80000000 0x60000000>; /* 1536 MB */
20	};	20	};
21		21
22	mmc2_3v3: fixedregulator-mmc2 {	22	mmc2_3v3: fixedregulator-mmc2 {
23	compatible = "regulator-fixed";	23	compatible = "regulator-fixed";
24	regulator-name = "mmc2_3v3";	24	regulator-name = "mmc2_3v3";
25	regulator-min-microvolt = <3300000>;	25	regulator-min-microvolt = <3300000>;
26	regulator-max-microvolt = <3300000>;	26	regulator-max-microvolt = <3300000>;
27	};	27	};
28		28
29	vtt_fixed: fixedregulator-vtt {	29	vtt_fixed: fixedregulator-vtt {
30	compatible = "regulator-fixed";	30	compatible = "regulator-fixed";
31	regulator-name = "vtt_fixed";	31	regulator-name = "vtt_fixed";
32	regulator-min-microvolt = <1350000>;	32	regulator-min-microvolt = <1350000>;
33	regulator-max-microvolt = <1350000>;	33	regulator-max-microvolt = <1350000>;
34	regulator-always-on;	34	regulator-always-on;
35	regulator-boot-on;	35	regulator-boot-on;
36	enable-active-high;	36	enable-active-high;
37	gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;	37	gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
38	};	38	};
39	};	39	};
40		40
41	&dra7_pmx_core {	41	&dra7_pmx_core {
42	pinctrl-names = "default";	42	pinctrl-names = "default";
43	pinctrl-0 = <&vtt_pin>;	43	pinctrl-0 = <&vtt_pin>;
44		44
45	vtt_pin: pinmux_vtt_pin {	45	vtt_pin: pinmux_vtt_pin {
46	pinctrl-single,pins = <	46	pinctrl-single,pins = <
47	0x3b4 (PIN_OUTPUT \| MUX_MODE14) /* spi1_cs1.gpio7_11 */	47	0x3b4 (PIN_OUTPUT \| MUX_MODE14) /* spi1_cs1.gpio7_11 */
48	>;	48	>;
49	};	49	};
50		50
51	i2c1_pins: pinmux_i2c1_pins {	51	i2c1_pins: pinmux_i2c1_pins {
52	pinctrl-single,pins = <	52	pinctrl-single,pins = <
53	0x400 (PIN_INPUT \| MUX_MODE0) /* i2c1_sda */	53	0x400 (PIN_INPUT \| MUX_MODE0) /* i2c1_sda */
54	0x404 (PIN_INPUT \| MUX_MODE0) /* i2c1_scl */	54	0x404 (PIN_INPUT \| MUX_MODE0) /* i2c1_scl */
55	>;	55	>;
56	};	56	};
57		57
58	i2c2_pins: pinmux_i2c2_pins {	58	i2c2_pins: pinmux_i2c2_pins {
59	pinctrl-single,pins = <	59	pinctrl-single,pins = <
60	0x408 (PIN_INPUT \| MUX_MODE0) /* i2c2_sda */	60	0x408 (PIN_INPUT \| MUX_MODE0) /* i2c2_sda */
61	0x40c (PIN_INPUT \| MUX_MODE0) /* i2c2_scl */	61	0x40c (PIN_INPUT \| MUX_MODE0) /* i2c2_scl */
62	>;	62	>;
63	};	63	};
64		64
65	i2c3_pins: pinmux_i2c3_pins {	65	i2c3_pins: pinmux_i2c3_pins {
66	pinctrl-single,pins = <	66	pinctrl-single,pins = <
67	0x288 (PIN_INPUT \| MUX_MODE9) /* gpio6_14.i2c3_sda */	67	0x288 (PIN_INPUT \| MUX_MODE9) /* gpio6_14.i2c3_sda */
68	0x28c (PIN_INPUT \| MUX_MODE9) /* gpio6_15.i2c3_scl */	68	0x28c (PIN_INPUT \| MUX_MODE9) /* gpio6_15.i2c3_scl */
69	>;	69	>;
70	};	70	};
71		71
72	mcspi1_pins: pinmux_mcspi1_pins {	72	mcspi1_pins: pinmux_mcspi1_pins {
73	pinctrl-single,pins = <	73	pinctrl-single,pins = <
74	0x3a4 (PIN_INPUT \| MUX_MODE0) /* spi1_sclk */	74	0x3a4 (PIN_INPUT \| MUX_MODE0) /* spi1_sclk */
75	0x3a8 (PIN_INPUT \| MUX_MODE0) /* spi1_d1 */	75	0x3a8 (PIN_INPUT \| MUX_MODE0) /* spi1_d1 */
76	0x3ac (PIN_INPUT \| MUX_MODE0) /* spi1_d0 */	76	0x3ac (PIN_INPUT \| MUX_MODE0) /* spi1_d0 */
77	0x3b0 (PIN_INPUT_SLEW \| MUX_MODE0) /* spi1_cs0 */	77	0x3b0 (PIN_INPUT_SLEW \| MUX_MODE0) /* spi1_cs0 */
78	0x3b8 (PIN_INPUT_SLEW \| MUX_MODE6) /* spi1_cs2.hdmi1_hpd */	78	0x3b8 (PIN_INPUT_SLEW \| MUX_MODE6) /* spi1_cs2.hdmi1_hpd */
79	0x3bc (PIN_INPUT_SLEW \| MUX_MODE6) /* spi1_cs3.hdmi1_cec */	79	0x3bc (PIN_INPUT_SLEW \| MUX_MODE6) /* spi1_cs3.hdmi1_cec */
80	>;	80	>;
81	};	81	};
82		82
83	mcspi2_pins: pinmux_mcspi2_pins {	83	mcspi2_pins: pinmux_mcspi2_pins {
84	pinctrl-single,pins = <	84	pinctrl-single,pins = <
85	0x3c0 (PIN_INPUT \| MUX_MODE0) /* spi2_sclk */	85	0x3c0 (PIN_INPUT \| MUX_MODE0) /* spi2_sclk */
86	0x3c4 (PIN_INPUT_SLEW \| MUX_MODE0) /* spi2_d1 */	86	0x3c4 (PIN_INPUT_SLEW \| MUX_MODE0) /* spi2_d1 */
87	0x3c8 (PIN_INPUT_SLEW \| MUX_MODE0) /* spi2_d1 */	87	0x3c8 (PIN_INPUT_SLEW \| MUX_MODE0) /* spi2_d1 */
88	0x3cc (PIN_INPUT_SLEW \| MUX_MODE0) /* spi2_cs0 */	88	0x3cc (PIN_INPUT_SLEW \| MUX_MODE0) /* spi2_cs0 */
89	>;	89	>;
90	};	90	};
91		91
92	uart1_pins: pinmux_uart1_pins {	92	uart1_pins: pinmux_uart1_pins {
93	pinctrl-single,pins = <	93	pinctrl-single,pins = <
94	0x3e0 (PIN_INPUT_SLEW \| MUX_MODE0) /* uart1_rxd */	94	0x3e0 (PIN_INPUT_SLEW \| MUX_MODE0) /* uart1_rxd */
95	0x3e4 (PIN_INPUT_SLEW \| MUX_MODE0) /* uart1_txd */	95	0x3e4 (PIN_INPUT_SLEW \| MUX_MODE0) /* uart1_txd */
96	0x3e8 (PIN_INPUT \| MUX_MODE3) /* uart1_ctsn */	96	0x3e8 (PIN_INPUT \| MUX_MODE3) /* uart1_ctsn */
97	0x3ec (PIN_INPUT \| MUX_MODE3) /* uart1_rtsn */	97	0x3ec (PIN_INPUT \| MUX_MODE3) /* uart1_rtsn */
98	>;	98	>;
99	};	99	};
100		100
101	uart2_pins: pinmux_uart2_pins {	101	uart2_pins: pinmux_uart2_pins {
102	pinctrl-single,pins = <	102	pinctrl-single,pins = <
103	0x3f0 (PIN_INPUT \| MUX_MODE0) /* uart2_rxd */	103	0x3f0 (PIN_INPUT \| MUX_MODE0) /* uart2_rxd */
104	0x3f4 (PIN_INPUT \| MUX_MODE0) /* uart2_txd */	104	0x3f4 (PIN_INPUT \| MUX_MODE0) /* uart2_txd */
105	0x3f8 (PIN_INPUT \| MUX_MODE0) /* uart2_ctsn */	105	0x3f8 (PIN_INPUT \| MUX_MODE0) /* uart2_ctsn */
106	0x3fc (PIN_INPUT \| MUX_MODE0) /* uart2_rtsn */	106	0x3fc (PIN_INPUT \| MUX_MODE0) /* uart2_rtsn */
107	>;	107	>;
108	};	108	};
109		109
110	uart3_pins: pinmux_uart3_pins {	110	uart3_pins: pinmux_uart3_pins {
111	pinctrl-single,pins = <	111	pinctrl-single,pins = <
112	0x248 (PIN_INPUT_SLEW \| MUX_MODE0) /* uart3_rxd */	112	0x248 (PIN_INPUT_SLEW \| MUX_MODE0) /* uart3_rxd */
113	0x24c (PIN_INPUT_SLEW \| MUX_MODE0) /* uart3_txd */	113	0x24c (PIN_INPUT_SLEW \| MUX_MODE0) /* uart3_txd */
114	>;	114	>;
115	};	115	};
116		116
117	qspi1_pins: pinmux_qspi1_pins {	117	qspi1_pins: pinmux_qspi1_pins {
118	pinctrl-single,pins = <	118	pinctrl-single,pins = <
119	0x4c (PIN_INPUT \| MUX_MODE1) /* gpmc_a3.qspi1_cs2 */	119	0x4c (PIN_INPUT \| MUX_MODE1) /* gpmc_a3.qspi1_cs2 */
120	0x50 (PIN_INPUT \| MUX_MODE1) /* gpmc_a4.qspi1_cs3 */	120	0x50 (PIN_INPUT \| MUX_MODE1) /* gpmc_a4.qspi1_cs3 */
121	0x74 (PIN_INPUT \| MUX_MODE1) /* gpmc_a13.qspi1_rtclk */	121	0x74 (PIN_INPUT \| MUX_MODE1) /* gpmc_a13.qspi1_rtclk */
122	0x78 (PIN_INPUT \| MUX_MODE1) /* gpmc_a14.qspi1_d3 */	122	0x78 (PIN_INPUT \| MUX_MODE1) /* gpmc_a14.qspi1_d3 */
123	0x7c (PIN_INPUT \| MUX_MODE1) /* gpmc_a15.qspi1_d2 */	123	0x7c (PIN_INPUT \| MUX_MODE1) /* gpmc_a15.qspi1_d2 */
124	0x80 (PIN_INPUT \| MUX_MODE1) /* gpmc_a16.qspi1_d1 */	124	0x80 (PIN_INPUT \| MUX_MODE1) /* gpmc_a16.qspi1_d1 */
125	0x84 (PIN_INPUT \| MUX_MODE1) /* gpmc_a17.qspi1_d0 */	125	0x84 (PIN_INPUT \| MUX_MODE1) /* gpmc_a17.qspi1_d0 */
126	0x88 (PIN_INPUT \| MUX_MODE1) /* qpmc_a18.qspi1_sclk */	126	0x88 (PIN_INPUT \| MUX_MODE1) /* qpmc_a18.qspi1_sclk */
127	0xb8 (PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */	127	0xb8 (PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */
128	0xbc (PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_cs3.qspi1_cs1 */	128	0xbc (PIN_INPUT_PULLUP \| MUX_MODE1) /* gpmc_cs3.qspi1_cs1 */
129	>;	129	>;
130	};	130	};
131		131
132	usb1_pins: pinmux_usb1_pins {	132	usb1_pins: pinmux_usb1_pins {
133	pinctrl-single,pins = <	133	pinctrl-single,pins = <
134	0x280 (PIN_INPUT_SLEW \| MUX_MODE0) /* usb1_drvvbus */	134	0x280 (PIN_INPUT_SLEW \| MUX_MODE0) /* usb1_drvvbus */
135	>;	135	>;
136	};	136	};
137		137
138	usb2_pins: pinmux_usb2_pins {	138	usb2_pins: pinmux_usb2_pins {
139	pinctrl-single,pins = <	139	pinctrl-single,pins = <
140	0x284 (PIN_INPUT_SLEW \| MUX_MODE0) /* usb2_drvvbus */	140	0x284 (PIN_INPUT_SLEW \| MUX_MODE0) /* usb2_drvvbus */
141	>;	141	>;
142	};	142	};
143		143
144	nand_flash_x16: nand_flash_x16 {	144	nand_flash_x16: nand_flash_x16 {
145	/* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch	145	/* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch
146	* So NAND flash requires following switch settings:	146	* So NAND flash requires following switch settings:
147	* SW5.9 (GPMC_WPN) = LOW	147	* SW5.9 (GPMC_WPN) = LOW
148	* SW5.1 (NAND_BOOTn) = HIGH */	148	* SW5.1 (NAND_BOOTn) = HIGH */
149	pinctrl-single,pins = <	149	pinctrl-single,pins = <
150	0x0 (PIN_INPUT \| MUX_MODE0) /* gpmc_ad0 */	150	0x0 (PIN_INPUT \| MUX_MODE0) /* gpmc_ad0 */
151	0x4 (PIN_INPUT \| MUX_MODE0) /* gpmc_ad1 */	151	0x4 (PIN_INPUT \| MUX_MODE0) /* gpmc_ad1 */
152	0x8 (PIN_INPUT \| MUX_MODE0) /* gpmc_ad2 */	152	0x8 (PIN_INPUT \| MUX_MODE0) /* gpmc_ad2 */
153	0xc (PIN_INPUT \| MUX_MODE0) /* gpmc_ad3 */	153	0xc (PIN_INPUT \| MUX_MODE0) /* gpmc_ad3 */
154	0x10 (PIN_INPUT \| MUX_MODE0) /* gpmc_ad4 */	154	0x10 (PIN_INPUT \| MUX_MODE0) /* gpmc_ad4 */
155	0x14 (PIN_INPUT \| MUX_MODE0) /* gpmc_ad5 */	155	0x14 (PIN_INPUT \| MUX_MODE0) /* gpmc_ad5 */
156	0x18 (PIN_INPUT \| MUX_MODE0) /* gpmc_ad6 */	156	0x18 (PIN_INPUT \| MUX_MODE0) /* gpmc_ad6 */
157	0x1c (PIN_INPUT \| MUX_MODE0) /* gpmc_ad7 */	157	0x1c (PIN_INPUT \| MUX_MODE0) /* gpmc_ad7 */
158	0x20 (PIN_INPUT \| MUX_MODE0) /* gpmc_ad8 */	158	0x20 (PIN_INPUT \| MUX_MODE0) /* gpmc_ad8 */
159	0x24 (PIN_INPUT \| MUX_MODE0) /* gpmc_ad9 */	159	0x24 (PIN_INPUT \| MUX_MODE0) /* gpmc_ad9 */
160	0x28 (PIN_INPUT \| MUX_MODE0) /* gpmc_ad10 */	160	0x28 (PIN_INPUT \| MUX_MODE0) /* gpmc_ad10 */
161	0x2c (PIN_INPUT \| MUX_MODE0) /* gpmc_ad11 */	161	0x2c (PIN_INPUT \| MUX_MODE0) /* gpmc_ad11 */
162	0x30 (PIN_INPUT \| MUX_MODE0) /* gpmc_ad12 */	162	0x30 (PIN_INPUT \| MUX_MODE0) /* gpmc_ad12 */
163	0x34 (PIN_INPUT \| MUX_MODE0) /* gpmc_ad13 */	163	0x34 (PIN_INPUT \| MUX_MODE0) /* gpmc_ad13 */
164	0x38 (PIN_INPUT \| MUX_MODE0) /* gpmc_ad14 */	164	0x38 (PIN_INPUT \| MUX_MODE0) /* gpmc_ad14 */
165	0x3c (PIN_INPUT \| MUX_MODE0) /* gpmc_ad15 */	165	0x3c (PIN_INPUT \| MUX_MODE0) /* gpmc_ad15 */
166	0xd8 (PIN_INPUT_PULLUP \| MUX_MODE0) /* gpmc_wait0 */	166	0xd8 (PIN_INPUT_PULLUP \| MUX_MODE0) /* gpmc_wait0 */
167	0xcc (PIN_OUTPUT \| MUX_MODE0) /* gpmc_wen */	167	0xcc (PIN_OUTPUT \| MUX_MODE0) /* gpmc_wen */
168	0xb4 (PIN_OUTPUT_PULLUP \| MUX_MODE0) /* gpmc_csn0 */	168	0xb4 (PIN_OUTPUT_PULLUP \| MUX_MODE0) /* gpmc_csn0 */
169	0xc4 (PIN_OUTPUT \| MUX_MODE0) /* gpmc_advn_ale */	169	0xc4 (PIN_OUTPUT \| MUX_MODE0) /* gpmc_advn_ale */
170	0xc8 (PIN_OUTPUT \| MUX_MODE0) /* gpmc_oen_ren */	170	0xc8 (PIN_OUTPUT \| MUX_MODE0) /* gpmc_oen_ren */
171	0xd0 (PIN_OUTPUT \| MUX_MODE0) /* gpmc_be0n_cle */	171	0xd0 (PIN_OUTPUT \| MUX_MODE0) /* gpmc_be0n_cle */
172	>;	172	>;
173	};	173	};
174		174
175	cpsw_default: cpsw_default {	175	cpsw_default: cpsw_default {
176	pinctrl-single,pins = <	176	pinctrl-single,pins = <
177	/* Slave 1 */	177	/* Slave 1 */
178	0x250 (PIN_OUTPUT \| MUX_MODE0) /* rgmii0_txc.rgmii0_txc */	178	0x250 (PIN_OUTPUT \| MUX_MODE0) /* rgmii0_txc.rgmii0_txc */
179	0x254 (PIN_OUTPUT \| MUX_MODE0) /* rgmii0_txctl.rgmii0_txctl */	179	0x254 (PIN_OUTPUT \| MUX_MODE0) /* rgmii0_txctl.rgmii0_txctl */
180	0x258 (PIN_OUTPUT \| MUX_MODE0) /* rgmii0_td3.rgmii0_txd3 */	180	0x258 (PIN_OUTPUT \| MUX_MODE0) /* rgmii0_td3.rgmii0_txd3 */
181	0x25c (PIN_OUTPUT \| MUX_MODE0) /* rgmii0_txd2.rgmii0_txd2 */	181	0x25c (PIN_OUTPUT \| MUX_MODE0) /* rgmii0_txd2.rgmii0_txd2 */
182	0x260 (PIN_OUTPUT \| MUX_MODE0) /* rgmii0_txd1.rgmii0_txd1 */	182	0x260 (PIN_OUTPUT \| MUX_MODE0) /* rgmii0_txd1.rgmii0_txd1 */
183	0x264 (PIN_OUTPUT \| MUX_MODE0) /* rgmii0_txd0.rgmii0_txd0 */	183	0x264 (PIN_OUTPUT \| MUX_MODE0) /* rgmii0_txd0.rgmii0_txd0 */
184	0x268 (PIN_INPUT \| MUX_MODE0) /* rgmii0_rxc.rgmii0_rxc */	184	0x268 (PIN_INPUT \| MUX_MODE0) /* rgmii0_rxc.rgmii0_rxc */
185	0x26c (PIN_INPUT \| MUX_MODE0) /* rgmii0_rxctl.rgmii0_rxctl */	185	0x26c (PIN_INPUT \| MUX_MODE0) /* rgmii0_rxctl.rgmii0_rxctl */
186	0x270 (PIN_INPUT \| MUX_MODE0) /* rgmii0_rxd3.rgmii0_rxd3 */	186	0x270 (PIN_INPUT \| MUX_MODE0) /* rgmii0_rxd3.rgmii0_rxd3 */
187	0x274 (PIN_INPUT \| MUX_MODE0) /* rgmii0_rxd2.rgmii0_rxd2 */	187	0x274 (PIN_INPUT \| MUX_MODE0) /* rgmii0_rxd2.rgmii0_rxd2 */
188	0x278 (PIN_INPUT \| MUX_MODE0) /* rgmii0_rxd1.rgmii0_rxd1 */	188	0x278 (PIN_INPUT \| MUX_MODE0) /* rgmii0_rxd1.rgmii0_rxd1 */
189	0x27c (PIN_INPUT \| MUX_MODE0) /* rgmii0_rxd0.rgmii0_rxd0 */	189	0x27c (PIN_INPUT \| MUX_MODE0) /* rgmii0_rxd0.rgmii0_rxd0 */
190		190
191	/* Slave 2 */	191	/* Slave 2 */
192	0x198 (PIN_OUTPUT \| MUX_MODE3) /* vin2a_d12.rgmii1_txc */	192	0x198 (PIN_OUTPUT \| MUX_MODE3) /* vin2a_d12.rgmii1_txc */
193	0x19c (PIN_OUTPUT \| MUX_MODE3) /* vin2a_d13.rgmii1_tctl */	193	0x19c (PIN_OUTPUT \| MUX_MODE3) /* vin2a_d13.rgmii1_tctl */
194	0x1a0 (PIN_OUTPUT \| MUX_MODE3) /* vin2a_d14.rgmii1_td3 */	194	0x1a0 (PIN_OUTPUT \| MUX_MODE3) /* vin2a_d14.rgmii1_td3 */
195	0x1a4 (PIN_OUTPUT \| MUX_MODE3) /* vin2a_d15.rgmii1_td2 */	195	0x1a4 (PIN_OUTPUT \| MUX_MODE3) /* vin2a_d15.rgmii1_td2 */
196	0x1a8 (PIN_OUTPUT \| MUX_MODE3) /* vin2a_d16.rgmii1_td1 */	196	0x1a8 (PIN_OUTPUT \| MUX_MODE3) /* vin2a_d16.rgmii1_td1 */
197	0x1ac (PIN_OUTPUT \| MUX_MODE3) /* vin2a_d17.rgmii1_td0 */	197	0x1ac (PIN_OUTPUT \| MUX_MODE3) /* vin2a_d17.rgmii1_td0 */
198	0x1b0 (PIN_INPUT \| MUX_MODE3) /* vin2a_d18.rgmii1_rclk */	198	0x1b0 (PIN_INPUT \| MUX_MODE3) /* vin2a_d18.rgmii1_rclk */
199	0x1b4 (PIN_INPUT \| MUX_MODE3) /* vin2a_d19.rgmii1_rctl */	199	0x1b4 (PIN_INPUT \| MUX_MODE3) /* vin2a_d19.rgmii1_rctl */
200	0x1b8 (PIN_INPUT \| MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */	200	0x1b8 (PIN_INPUT \| MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */
201	0x1bc (PIN_INPUT \| MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */	201	0x1bc (PIN_INPUT \| MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */
202	0x1c0 (PIN_INPUT \| MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */	202	0x1c0 (PIN_INPUT \| MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */
203	0x1c4 (PIN_INPUT \| MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */	203	0x1c4 (PIN_INPUT \| MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */
204	>;	204	>;
205		205
206	};	206	};
207		207
208	cpsw_sleep: cpsw_sleep {	208	cpsw_sleep: cpsw_sleep {
209	pinctrl-single,pins = <	209	pinctrl-single,pins = <
210	/* Slave 1 */	210	/* Slave 1 */
211	0x250 (MUX_MODE15)	211	0x250 (MUX_MODE15)
212	0x254 (MUX_MODE15)	212	0x254 (MUX_MODE15)
213	0x258 (MUX_MODE15)	213	0x258 (MUX_MODE15)
214	0x25c (MUX_MODE15)	214	0x25c (MUX_MODE15)
215	0x260 (MUX_MODE15)	215	0x260 (MUX_MODE15)
216	0x264 (MUX_MODE15)	216	0x264 (MUX_MODE15)
217	0x268 (MUX_MODE15)	217	0x268 (MUX_MODE15)
218	0x26c (MUX_MODE15)	218	0x26c (MUX_MODE15)
219	0x270 (MUX_MODE15)	219	0x270 (MUX_MODE15)
220	0x274 (MUX_MODE15)	220	0x274 (MUX_MODE15)
221	0x278 (MUX_MODE15)	221	0x278 (MUX_MODE15)
222	0x27c (MUX_MODE15)	222	0x27c (MUX_MODE15)
223		223
224	/* Slave 2 */	224	/* Slave 2 */
225	0x198 (MUX_MODE15)	225	0x198 (MUX_MODE15)
226	0x19c (MUX_MODE15)	226	0x19c (MUX_MODE15)
227	0x1a0 (MUX_MODE15)	227	0x1a0 (MUX_MODE15)
228	0x1a4 (MUX_MODE15)	228	0x1a4 (MUX_MODE15)
229	0x1a8 (MUX_MODE15)	229	0x1a8 (MUX_MODE15)
230	0x1ac (MUX_MODE15)	230	0x1ac (MUX_MODE15)
231	0x1b0 (MUX_MODE15)	231	0x1b0 (MUX_MODE15)
232	0x1b4 (MUX_MODE15)	232	0x1b4 (MUX_MODE15)
233	0x1b8 (MUX_MODE15)	233	0x1b8 (MUX_MODE15)
234	0x1bc (MUX_MODE15)	234	0x1bc (MUX_MODE15)
235	0x1c0 (MUX_MODE15)	235	0x1c0 (MUX_MODE15)
236	0x1c4 (MUX_MODE15)	236	0x1c4 (MUX_MODE15)
237	>;	237	>;
238	};	238	};
239		239
240	davinci_mdio_default: davinci_mdio_default {	240	davinci_mdio_default: davinci_mdio_default {
241	pinctrl-single,pins = <	241	pinctrl-single,pins = <
242	0x23c (PIN_OUTPUT_PULLUP \| MUX_MODE0) /* mdio_d.mdio_d */	242	0x23c (PIN_OUTPUT_PULLUP \| MUX_MODE0) /* mdio_d.mdio_d */
243	0x240 (PIN_INPUT_PULLUP \| MUX_MODE0) /* mdio_clk.mdio_clk */	243	0x240 (PIN_INPUT_PULLUP \| MUX_MODE0) /* mdio_clk.mdio_clk */
244	>;	244	>;
245	};	245	};
246		246
247	davinci_mdio_sleep: davinci_mdio_sleep {	247	davinci_mdio_sleep: davinci_mdio_sleep {
248	pinctrl-single,pins = <	248	pinctrl-single,pins = <
249	0x23c (MUX_MODE15)	249	0x23c (MUX_MODE15)
250	0x240 (MUX_MODE15)	250	0x240 (MUX_MODE15)
251	>;	251	>;
252	};	252	};
253		253
254	dcan1_pins_default: dcan1_pins_default {	254	dcan1_pins_default: dcan1_pins_default {
255	pinctrl-single,pins = <	255	pinctrl-single,pins = <
256	0x3d0 (PIN_OUTPUT \| MUX_MODE0) /* dcan1_tx */	256	0x3d0 (PIN_OUTPUT \| MUX_MODE0) /* dcan1_tx */
257	0x3d4 (MUX_MODE15) /* dcan1_rx.off */	257	0x3d4 (MUX_MODE15) /* dcan1_rx.off */
258	0x418 (PULL_DIS \| MUX_MODE1) /* wakeup0.dcan1_rx */	258	0x418 (PULL_DIS \| MUX_MODE1) /* wakeup0.dcan1_rx */
259	>;	259	>;
260	};	260	};
261		261
262	dcan1_pins_sleep: dcan1_pins_sleep {	262	dcan1_pins_sleep: dcan1_pins_sleep {
263	pinctrl-single,pins = <	263	pinctrl-single,pins = <
264	0x3d0 (MUX_MODE15) /* dcan1_tx.off */	264	0x3d0 (MUX_MODE15) /* dcan1_tx.off */
265	0x3d4 (MUX_MODE15) /* dcan1_rx.off */	265	0x3d4 (MUX_MODE15) /* dcan1_rx.off */
266	0x418 (MUX_MODE15) /* wakeup0.off */	266	0x418 (MUX_MODE15) /* wakeup0.off */
267	>;	267	>;
268	};	268	};
269	};	269	};
270		270
271	&i2c1 {	271	&i2c1 {
272	status = "okay";	272	status = "okay";
273	pinctrl-names = "default";	273	pinctrl-names = "default";
274	pinctrl-0 = <&i2c1_pins>;	274	pinctrl-0 = <&i2c1_pins>;
275	clock-frequency = <400000>;	275	clock-frequency = <400000>;
276		276
277	tps659038: tps659038@58 {	277	tps659038: tps659038@58 {
278	compatible = "ti,tps659038";	278	compatible = "ti,tps659038";
279	reg = <0x58>;	279	reg = <0x58>;
280		280
281	tps659038_pmic {	281	tps659038_pmic {
282	compatible = "ti,tps659038-pmic";	282	compatible = "ti,tps659038-pmic";
283		283
284	regulators {	284	regulators {
285	smps123_reg: smps123 {	285	smps123_reg: smps123 {
286	/* VDD_MPU */	286	/* VDD_MPU */
287	regulator-name = "smps123";	287	regulator-name = "smps123";
288	regulator-min-microvolt = < 850000>;	288	regulator-min-microvolt = < 850000>;
289	regulator-max-microvolt = <1250000>;	289	regulator-max-microvolt = <1250000>;
290	regulator-always-on;	290	regulator-always-on;
291	regulator-boot-on;	291	regulator-boot-on;
292	};	292	};
293		293
294	smps45_reg: smps45 {	294	smps45_reg: smps45 {
295	/* VDD_DSPEVE */	295	/* VDD_DSPEVE */
296	regulator-name = "smps45";	296	regulator-name = "smps45";
297	regulator-min-microvolt = < 850000>;	297	regulator-min-microvolt = < 850000>;
298	regulator-max-microvolt = <1150000>;	298	regulator-max-microvolt = <1150000>;
299	regulator-always-on;	299	regulator-always-on;
300	regulator-boot-on;	300	regulator-boot-on;
301	};	301	};
302		302
303	smps6_reg: smps6 {	303	smps6_reg: smps6 {
304	/* VDD_GPU - over VDD_SMPS6 */	304	/* VDD_GPU - over VDD_SMPS6 */
305	regulator-name = "smps6";	305	regulator-name = "smps6";
306	regulator-min-microvolt = <850000>;	306	regulator-min-microvolt = <850000>;
307	regulator-max-microvolt = <1250000>;	307	regulator-max-microvolt = <1250000>;
308	regulator-always-on;	308	regulator-always-on;
309	regulator-boot-on;	309	regulator-boot-on;
310	};	310	};
311		311
312	smps7_reg: smps7 {	312	smps7_reg: smps7 {
313	/* CORE_VDD */	313	/* CORE_VDD */
314	regulator-name = "smps7";	314	regulator-name = "smps7";
315	regulator-min-microvolt = <850000>;	315	regulator-min-microvolt = <850000>;
316	regulator-max-microvolt = <1060000>;	316	regulator-max-microvolt = <1060000>;
317	regulator-always-on;	317	regulator-always-on;
318	regulator-boot-on;	318	regulator-boot-on;
319	};	319	};
320		320
321	smps8_reg: smps8 {	321	smps8_reg: smps8 {
322	/* VDD_IVAHD */	322	/* VDD_IVAHD */
323	regulator-name = "smps8";	323	regulator-name = "smps8";
324	regulator-min-microvolt = < 850000>;	324	regulator-min-microvolt = < 850000>;
325	regulator-max-microvolt = <1250000>;	325	regulator-max-microvolt = <1250000>;
326	regulator-always-on;	326	regulator-always-on;
327	regulator-boot-on;	327	regulator-boot-on;
328	};	328	};
329		329
330	smps9_reg: smps9 {	330	smps9_reg: smps9 {
331	/* VDDS1V8 */	331	/* VDDS1V8 */
332	regulator-name = "smps9";	332	regulator-name = "smps9";
333	regulator-min-microvolt = <1800000>;	333	regulator-min-microvolt = <1800000>;
334	regulator-max-microvolt = <1800000>;	334	regulator-max-microvolt = <1800000>;
335	regulator-always-on;	335	regulator-always-on;
336	regulator-boot-on;	336	regulator-boot-on;
337	};	337	};
338		338
339	ldo1_reg: ldo1 {	339	ldo1_reg: ldo1 {
340	/* LDO1_OUT --> SDIO */	340	/* LDO1_OUT --> SDIO */
341	regulator-name = "ldo1";	341	regulator-name = "ldo1";
342	regulator-min-microvolt = <1800000>;	342	regulator-min-microvolt = <1800000>;
343	regulator-max-microvolt = <3300000>;	343	regulator-max-microvolt = <3300000>;
344	regulator-boot-on;	344	regulator-boot-on;
345	};	345	};
346		346
347	ldo2_reg: ldo2 {	347	ldo2_reg: ldo2 {
348	/* VDD_RTCIO */	348	/* VDD_RTCIO */
349	/* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */	349	/* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */
350	regulator-name = "ldo2";	350	regulator-name = "ldo2";
351	regulator-min-microvolt = <3300000>;	351	regulator-min-microvolt = <3300000>;
352	regulator-max-microvolt = <3300000>;	352	regulator-max-microvolt = <3300000>;
353	regulator-always-on;	353	regulator-always-on;
354	regulator-boot-on;	354	regulator-boot-on;
355	};	355	};
356		356
357	ldo3_reg: ldo3 {	357	ldo3_reg: ldo3 {
358	/* VDDA_1V8_PHY */	358	/* VDDA_1V8_PHY */
359	regulator-name = "ldo3";	359	regulator-name = "ldo3";
360	regulator-min-microvolt = <1800000>;	360	regulator-min-microvolt = <1800000>;
361	regulator-max-microvolt = <1800000>;	361	regulator-max-microvolt = <1800000>;
362	regulator-always-on;	362	regulator-always-on;
363	regulator-boot-on;	363	regulator-boot-on;
364	};	364	};
365		365
366	ldo9_reg: ldo9 {	366	ldo9_reg: ldo9 {
367	/* VDD_RTC */	367	/* VDD_RTC */
368	regulator-name = "ldo9";	368	regulator-name = "ldo9";
369	regulator-min-microvolt = <1050000>;	369	regulator-min-microvolt = <1050000>;
370	regulator-max-microvolt = <1050000>;	370	regulator-max-microvolt = <1050000>;
371	regulator-always-on;	371	regulator-always-on;
372	regulator-boot-on;	372	regulator-boot-on;
373	};	373	};
374		374
375	ldoln_reg: ldoln {	375	ldoln_reg: ldoln {
376	/* VDDA_1V8_PLL */	376	/* VDDA_1V8_PLL */
377	regulator-name = "ldoln";	377	regulator-name = "ldoln";
378	regulator-min-microvolt = <1800000>;	378	regulator-min-microvolt = <1800000>;
379	regulator-max-microvolt = <1800000>;	379	regulator-max-microvolt = <1800000>;
380	regulator-always-on;	380	regulator-always-on;
381	regulator-boot-on;	381	regulator-boot-on;
382	};	382	};
383		383
384	ldousb_reg: ldousb {	384	ldousb_reg: ldousb {
385	/* VDDA_3V_USB: VDDA_USBHS33 */	385	/* VDDA_3V_USB: VDDA_USBHS33 */
386	regulator-name = "ldousb";	386	regulator-name = "ldousb";
387	regulator-min-microvolt = <3300000>;	387	regulator-min-microvolt = <3300000>;
388	regulator-max-microvolt = <3300000>;	388	regulator-max-microvolt = <3300000>;
389	regulator-boot-on;	389	regulator-boot-on;
390	};	390	};
391	};	391	};
392	};	392	};
393	};	393	};
394	};	394	};
395		395
396	&i2c2 {	396	&i2c2 {
397	status = "okay";	397	status = "okay";
398	pinctrl-names = "default";	398	pinctrl-names = "default";
399	pinctrl-0 = <&i2c2_pins>;	399	pinctrl-0 = <&i2c2_pins>;
400	clock-frequency = <400000>;	400	clock-frequency = <400000>;
401	};	401	};
402		402
403	&i2c3 {	403	&i2c3 {
404	status = "okay";	404	status = "okay";
405	pinctrl-names = "default";	405	pinctrl-names = "default";
406	pinctrl-0 = <&i2c3_pins>;	406	pinctrl-0 = <&i2c3_pins>;
407	clock-frequency = <400000>;	407	clock-frequency = <400000>;
408	};	408	};
409		409
410	&mcspi1 {	410	&mcspi1 {
411	status = "okay";	411	status = "okay";
412	pinctrl-names = "default";	412	pinctrl-names = "default";
413	pinctrl-0 = <&mcspi1_pins>;	413	pinctrl-0 = <&mcspi1_pins>;
414	};	414	};
415		415
416	&mcspi2 {	416	&mcspi2 {
417	status = "okay";	417	status = "okay";
418	pinctrl-names = "default";	418	pinctrl-names = "default";
419	pinctrl-0 = <&mcspi2_pins>;	419	pinctrl-0 = <&mcspi2_pins>;
420	};	420	};
421		421
422	&uart1 {	422	&uart1 {
423	status = "okay";	423	status = "okay";
424	pinctrl-names = "default";	424	pinctrl-names = "default";
425	pinctrl-0 = <&uart1_pins>;	425	pinctrl-0 = <&uart1_pins>;
426	interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,	426	interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
427	<&dra7_pmx_core 0x3e0>;	427	<&dra7_pmx_core 0x3e0>;
428	};	428	};
429		429
430	&uart2 {	430	&uart2 {
431	status = "okay";	431	status = "okay";
432	pinctrl-names = "default";	432	pinctrl-names = "default";
433	pinctrl-0 = <&uart2_pins>;	433	pinctrl-0 = <&uart2_pins>;
434	};	434	};
435		435
436	&uart3 {	436	&uart3 {
437	status = "okay";	437	status = "okay";
438	pinctrl-names = "default";	438	pinctrl-names = "default";
439	pinctrl-0 = <&uart3_pins>;	439	pinctrl-0 = <&uart3_pins>;
440	};	440	};
441		441
442	&mmc1 {	442	&mmc1 {
443	status = "okay";	443	status = "okay";
444	vmmc-supply = <&ldo1_reg>;	444	vmmc-supply = <&ldo1_reg>;
445	bus-width = <4>;	445	bus-width = <4>;
446	};	446	};
447		447
448	&mmc2 {	448	&mmc2 {
449	status = "okay";	449	status = "okay";
450	vmmc-supply = <&mmc2_3v3>;	450	vmmc-supply = <&mmc2_3v3>;
451	bus-width = <8>;	451	bus-width = <8>;
452	};	452	};
453		453
454	&cpu0 {	454	&cpu0 {
455	cpu0-supply = <&smps123_reg>;	455	cpu0-supply = <&smps123_reg>;
456	};	456	};
457		457
458	&qspi {	458	&qspi {
459	status = "okay";	459	status = "okay";
460	pinctrl-names = "default";	460	pinctrl-names = "default";
461	pinctrl-0 = <&qspi1_pins>;	461	pinctrl-0 = <&qspi1_pins>;
462		462
463	spi-max-frequency = <48000000>;	463	spi-max-frequency = <48000000>;
464	m25p80@0 {	464	m25p80@0 {
465	compatible = "s25fl256s1";	465	compatible = "s25fl256s1";
466	spi-max-frequency = <48000000>;	466	spi-max-frequency = <48000000>;
467	reg = <0>;	467	reg = <0>;
468	spi-tx-bus-width = <1>;	468	spi-tx-bus-width = <1>;
469	spi-rx-bus-width = <4>;	469	spi-rx-bus-width = <4>;
470	spi-cpol;	470	spi-cpol;
471	spi-cpha;	471	spi-cpha;
472	#address-cells = <1>;	472	#address-cells = <1>;
473	#size-cells = <1>;	473	#size-cells = <1>;
474		474
475	/* MTD partition table.	475	/* MTD partition table.
476	* The ROM checks the first four physical blocks	476	* The ROM checks the first four physical blocks
477	* for a valid file to boot and the flash here is	477	* for a valid file to boot and the flash here is
478	* 64KiB block size.	478	* 64KiB block size.
479	*/	479	*/
480	partition@0 {	480	partition@0 {
481	label = "QSPI.SPL";	481	label = "QSPI.SPL";
482	reg = <0x00000000 0x000010000>;	482	reg = <0x00000000 0x000010000>;
483	};	483	};
484	partition@1 {	484	partition@1 {
485	label = "QSPI.SPL.backup1";	485	label = "QSPI.SPL.backup1";
486	reg = <0x00010000 0x00010000>;	486	reg = <0x00010000 0x00010000>;
487	};	487	};
488	partition@2 {	488	partition@2 {
489	label = "QSPI.SPL.backup2";	489	label = "QSPI.SPL.backup2";
490	reg = <0x00020000 0x00010000>;	490	reg = <0x00020000 0x00010000>;
491	};	491	};
492	partition@3 {	492	partition@3 {
493	label = "QSPI.SPL.backup3";	493	label = "QSPI.SPL.backup3";
494	reg = <0x00030000 0x00010000>;	494	reg = <0x00030000 0x00010000>;
495	};	495	};
496	partition@4 {	496	partition@4 {
497	label = "QSPI.u-boot";	497	label = "QSPI.u-boot";
498	reg = <0x00040000 0x00100000>;	498	reg = <0x00040000 0x00100000>;
499	};	499	};
500	partition@5 {	500	partition@5 {
501	label = "QSPI.u-boot-spl-os";	501	label = "QSPI.u-boot-spl-os";
502	reg = <0x00140000 0x00010000>;	502	reg = <0x00140000 0x00080000>;
503	};	503	};
504	partition@6 {	504	partition@6 {
505	label = "QSPI.u-boot-env";	505	label = "QSPI.u-boot-env";
506	reg = <0x00150000 0x00010000>;	506	reg = <0x001c0000 0x00010000>;
507	};	507	};
508	partition@7 {	508	partition@7 {
509	label = "QSPI.u-boot-env.backup1";	509	label = "QSPI.u-boot-env.backup1";
510	reg = <0x00160000 0x0010000>;	510	reg = <0x001d0000 0x0010000>;
511	};	511	};
512	partition@8 {	512	partition@8 {
513	label = "QSPI.kernel";	513	label = "QSPI.kernel";
514	reg = <0x00170000 0x0800000>;	514	reg = <0x001e0000 0x0800000>;
515	};	515	};
516	partition@9 {	516	partition@9 {
517	label = "QSPI.file-system";	517	label = "QSPI.file-system";
518	reg = <0x00970000 0x01690000>;	518	reg = <0x009e0000 0x01620000>;
519	};	519	};
520	};	520	};
521	};	521	};
522		522
523	&usb1 {	523	&usb1 {
524	dr_mode = "peripheral";	524	dr_mode = "peripheral";
525	pinctrl-names = "default";	525	pinctrl-names = "default";
526	pinctrl-0 = <&usb1_pins>;	526	pinctrl-0 = <&usb1_pins>;
527	};	527	};
528		528
529	&usb2 {	529	&usb2 {
530	dr_mode = "host";	530	dr_mode = "host";
531	pinctrl-names = "default";	531	pinctrl-names = "default";
532	pinctrl-0 = <&usb2_pins>;	532	pinctrl-0 = <&usb2_pins>;
533	};	533	};
534		534
535	&elm {	535	&elm {
536	status = "okay";	536	status = "okay";
537	};	537	};
538		538
539	&gpmc {	539	&gpmc {
540	status = "okay";	540	status = "okay";
541	pinctrl-names = "default";	541	pinctrl-names = "default";
542	pinctrl-0 = <&nand_flash_x16>;	542	pinctrl-0 = <&nand_flash_x16>;
543	ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */	543	ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
544	nand@0,0 {	544	nand@0,0 {
545	reg = <0 0 4>; /* device IO registers */	545	reg = <0 0 4>; /* device IO registers */
546	ti,nand-ecc-opt = "bch8";	546	ti,nand-ecc-opt = "bch8";
547	ti,elm-id = <&elm>;	547	ti,elm-id = <&elm>;
548	nand-bus-width = <16>;	548	nand-bus-width = <16>;
549	gpmc,device-width = <2>;	549	gpmc,device-width = <2>;
550	gpmc,sync-clk-ps = <0>;	550	gpmc,sync-clk-ps = <0>;
551	gpmc,cs-on-ns = <0>;	551	gpmc,cs-on-ns = <0>;
552	gpmc,cs-rd-off-ns = <80>;	552	gpmc,cs-rd-off-ns = <80>;
553	gpmc,cs-wr-off-ns = <80>;	553	gpmc,cs-wr-off-ns = <80>;
554	gpmc,adv-on-ns = <0>;	554	gpmc,adv-on-ns = <0>;
555	gpmc,adv-rd-off-ns = <60>;	555	gpmc,adv-rd-off-ns = <60>;
556	gpmc,adv-wr-off-ns = <60>;	556	gpmc,adv-wr-off-ns = <60>;
557	gpmc,we-on-ns = <10>;	557	gpmc,we-on-ns = <10>;
558	gpmc,we-off-ns = <50>;	558	gpmc,we-off-ns = <50>;
559	gpmc,oe-on-ns = <4>;	559	gpmc,oe-on-ns = <4>;
560	gpmc,oe-off-ns = <40>;	560	gpmc,oe-off-ns = <40>;
561	gpmc,access-ns = <40>;	561	gpmc,access-ns = <40>;
562	gpmc,wr-access-ns = <80>;	562	gpmc,wr-access-ns = <80>;
563	gpmc,rd-cycle-ns = <80>;	563	gpmc,rd-cycle-ns = <80>;
564	gpmc,wr-cycle-ns = <80>;	564	gpmc,wr-cycle-ns = <80>;
565	gpmc,bus-turnaround-ns = <0>;	565	gpmc,bus-turnaround-ns = <0>;
566	gpmc,cycle2cycle-delay-ns = <0>;	566	gpmc,cycle2cycle-delay-ns = <0>;
567	gpmc,clk-activation-ns = <0>;	567	gpmc,clk-activation-ns = <0>;
568	gpmc,wait-monitoring-ns = <0>;	568	gpmc,wait-monitoring-ns = <0>;
569	gpmc,wr-data-mux-bus-ns = <0>;	569	gpmc,wr-data-mux-bus-ns = <0>;
570	/* MTD partition table */	570	/* MTD partition table */
571	/* All SPL-* partitions are sized to minimal length	571	/* All SPL-* partitions are sized to minimal length
572	* which can be independently programmable. For	572	* which can be independently programmable. For
573	* NAND flash this is equal to size of erase-block */	573	* NAND flash this is equal to size of erase-block */
574	#address-cells = <1>;	574	#address-cells = <1>;
575	#size-cells = <1>;	575	#size-cells = <1>;
576	partition@0 {	576	partition@0 {
577	label = "NAND.SPL";	577	label = "NAND.SPL";
578	reg = <0x00000000 0x000020000>;	578	reg = <0x00000000 0x000020000>;
579	};	579	};
580	partition@1 {	580	partition@1 {
581	label = "NAND.SPL.backup1";	581	label = "NAND.SPL.backup1";
582	reg = <0x00020000 0x00020000>;	582	reg = <0x00020000 0x00020000>;
583	};	583	};
584	partition@2 {	584	partition@2 {
585	label = "NAND.SPL.backup2";	585	label = "NAND.SPL.backup2";
586	reg = <0x00040000 0x00020000>;	586	reg = <0x00040000 0x00020000>;
587	};	587	};
588	partition@3 {	588	partition@3 {
589	label = "NAND.SPL.backup3";	589	label = "NAND.SPL.backup3";
590	reg = <0x00060000 0x00020000>;	590	reg = <0x00060000 0x00020000>;
591	};	591	};
592	partition@4 {	592	partition@4 {
593	label = "NAND.u-boot-spl-os";	593	label = "NAND.u-boot-spl-os";
594	reg = <0x00080000 0x00040000>;	594	reg = <0x00080000 0x00040000>;
595	};	595	};
596	partition@5 {	596	partition@5 {
597	label = "NAND.u-boot";	597	label = "NAND.u-boot";
598	reg = <0x000c0000 0x00100000>;	598	reg = <0x000c0000 0x00100000>;
599	};	599	};
600	partition@6 {	600	partition@6 {
601	label = "NAND.u-boot-env";	601	label = "NAND.u-boot-env";
602	reg = <0x001c0000 0x00020000>;	602	reg = <0x001c0000 0x00020000>;
603	};	603	};
604	partition@7 {	604	partition@7 {
605	label = "NAND.u-boot-env.backup1";	605	label = "NAND.u-boot-env.backup1";
606	reg = <0x001e0000 0x00020000>;	606	reg = <0x001e0000 0x00020000>;
607	};	607	};
608	partition@8 {	608	partition@8 {
609	label = "NAND.kernel";	609	label = "NAND.kernel";
610	reg = <0x00200000 0x00800000>;	610	reg = <0x00200000 0x00800000>;
611	};	611	};
612	partition@9 {	612	partition@9 {
613	label = "NAND.file-system";	613	label = "NAND.file-system";
614	reg = <0x00a00000 0x0f600000>;	614	reg = <0x00a00000 0x0f600000>;
615	};	615	};
616	};	616	};
617	};	617	};
618		618
619	&usb2_phy1 {	619	&usb2_phy1 {
620	phy-supply = <&ldousb_reg>;	620	phy-supply = <&ldousb_reg>;
621	};	621	};
622		622
623	&usb2_phy2 {	623	&usb2_phy2 {
624	phy-supply = <&ldousb_reg>;	624	phy-supply = <&ldousb_reg>;
625	};	625	};
626		626
627	&gpio7 {	627	&gpio7 {
628	ti,no-reset-on-init;	628	ti,no-reset-on-init;
629	ti,no-idle-on-init;	629	ti,no-idle-on-init;
630	};	630	};
631		631
632	&mac {	632	&mac {
633	status = "okay";	633	status = "okay";
634	pinctrl-names = "default", "sleep";	634	pinctrl-names = "default", "sleep";
635	pinctrl-0 = <&cpsw_default>;	635	pinctrl-0 = <&cpsw_default>;
636	pinctrl-1 = <&cpsw_sleep>;	636	pinctrl-1 = <&cpsw_sleep>;
637	dual_emac;	637	dual_emac;
638	};	638	};
639		639
640	&cpsw_emac0 {	640	&cpsw_emac0 {
641	phy_id = <&davinci_mdio>, <2>;	641	phy_id = <&davinci_mdio>, <2>;
642	phy-mode = "rgmii";	642	phy-mode = "rgmii";
643	dual_emac_res_vlan = <1>;	643	dual_emac_res_vlan = <1>;
644	};	644	};
645		645
646	&cpsw_emac1 {	646	&cpsw_emac1 {
647	phy_id = <&davinci_mdio>, <3>;	647	phy_id = <&davinci_mdio>, <3>;
648	phy-mode = "rgmii";	648	phy-mode = "rgmii";
649	dual_emac_res_vlan = <2>;	649	dual_emac_res_vlan = <2>;
650	};	650	};
651		651
652	&davinci_mdio {	652	&davinci_mdio {
653	pinctrl-names = "default", "sleep";	653	pinctrl-names = "default", "sleep";
654	pinctrl-0 = <&davinci_mdio_default>;	654	pinctrl-0 = <&davinci_mdio_default>;
655	pinctrl-1 = <&davinci_mdio_sleep>;	655	pinctrl-1 = <&davinci_mdio_sleep>;
656	};	656	};
657		657
658	&dcan1 {	658	&dcan1 {
659	status = "ok";	659	status = "ok";
660	pinctrl-names = "default", "sleep";	660	pinctrl-names = "default", "sleep";
661	pinctrl-0 = <&dcan1_pins_default>;	661	pinctrl-0 = <&dcan1_pins_default>;
662	pinctrl-1 = <&dcan1_pins_sleep>;	662	pinctrl-1 = <&dcan1_pins_sleep>;
663	};	663	};
664		664

arch/arm/boot/dts/omap3-n900.dts

Diff comments View file @ e3db221

 /*
  * Copyright (C) 2013 Pavel Machek <pavel@ucw.cz>
  * Copyright (C) 2013-2014 Aaro Koskinen <aaro.koskinen@iki.fi>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 (or later) as
  * published by the Free Software Foundation.
  */
 /dts-v1/;
 #include "omap34xx-hs.dtsi"
 #include <dt-bindings/input/input.h>
 / {
 	model = "Nokia N900";
 	compatible = "nokia,omap3-n900", "ti,omap3430", "ti,omap3";
 	cpus {
 		cpu@0 {
 			cpu0-supply = <&vcc>;
 		};
 	};
 	leds {
 		compatible = "gpio-leds";
 		heartbeat {
 			label = "debug::sleep";
 			gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>;  /* gpio162 */
 			linux,default-trigger = "default-on";
 			pinctrl-names = "default";
 			pinctrl-0 = <&debug_leds>;
 		};
 	};
 	memory {
 		device_type = "memory";
 		reg = <0x80000000 0x10000000>; /* 256 MB */
 	};
 	gpio_keys {
 		compatible = "gpio-keys";
 		camera_lens_cover {
 			label = "Camera Lens Cover";
 			gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; /* 110 */
 			linux,input-type = <5>; /* EV_SW */
 			linux,code = <0x09>; /* SW_CAMERA_LENS_COVER */
 			gpio-key,wakeup;
 		};
 		camera_focus {
 			label = "Camera Focus";
 			gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; /* 68 */
 			linux,code = <0x210>; /* KEY_CAMERA_FOCUS */
 			gpio-key,wakeup;
 		};
 		camera_capture {
 			label = "Camera Capture";
 			gpios = <&gpio3 5 GPIO_ACTIVE_LOW>; /* 69 */
 			linux,code = <0xd4>; /* KEY_CAMERA */
 			gpio-key,wakeup;
 		};
 		lock_button {
 			label = "Lock Button";
 			gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; /* 113 */
 			linux,code = <0x98>; /* KEY_SCREENLOCK */
 			gpio-key,wakeup;
 		};
 		keypad_slide {
 			label = "Keypad Slide";
 			gpios = <&gpio3 7 GPIO_ACTIVE_LOW>; /* 71 */
 			linux,input-type = <5>; /* EV_SW */
 			linux,code = <0x0a>; /* SW_KEYPAD_SLIDE */
 			gpio-key,wakeup;
 		};
 		proximity_sensor {
 			label = "Proximity Sensor";
 			gpios = <&gpio3 25 GPIO_ACTIVE_HIGH>; /* 89 */
 			linux,input-type = <5>; /* EV_SW */
 			linux,code = <0x0b>; /* SW_FRONT_PROXIMITY */
 		};
 	};
 	isp1704: isp1704 {
 		compatible = "nxp,isp1704";
 		nxp,enable-gpio = <&gpio3 3 GPIO_ACTIVE_HIGH>;
 		usb-phy = <&usb2_phy>;
 	};
 	tv: connector {
 		compatible = "composite-video-connector";
 		label = "tv";
 		port {
 			tv_connector_in: endpoint {
 				remote-endpoint = <&venc_out>;
 			};
 		};
 	};
 	sound: n900-audio {
 		compatible = "nokia,n900-audio";
 		nokia,cpu-dai = <&mcbsp2>;
 		nokia,audio-codec = <&tlv320aic3x>, <&tlv320aic3x_aux>;
 		nokia,headphone-amplifier = <&tpa6130a2>;
 		tvout-selection-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; /* 40 */
 		jack-detection-gpios = <&gpio6 17 GPIO_ACTIVE_HIGH>; /* 177 */
 		eci-switch-gpios = <&gpio6 22 GPIO_ACTIVE_HIGH>; /* 182 */
 		speaker-amplifier-gpios = <&twl_gpio 7 GPIO_ACTIVE_HIGH>;
 	};
 	battery: n900-battery {
 		compatible = "nokia,n900-battery";
 		io-channels = <&twl_madc 0>, <&twl_madc 4>, <&twl_madc 12>;
 		io-channel-names = "temp", "bsi", "vbat";
 	};
 };
 &omap3_pmx_core {
 	pinctrl-names = "default";
 	uart2_pins: pinmux_uart2_pins {
 		pinctrl-single,pins = <
 			0x14a (PIN_INPUT | MUX_MODE0)		/* uart2_rx */
 			0x148 (PIN_OUTPUT | MUX_MODE0)		/* uart2_tx */
 		>;
 	};
 	uart3_pins: pinmux_uart3_pins {
 		pinctrl-single,pins = <
 			0x16e (PIN_INPUT | MUX_MODE0)		/* uart3_rx */
 			0x170 (PIN_OUTPUT | MUX_MODE0)		/* uart3_tx */
 		>;
 	};
 	ethernet_pins: pinmux_ethernet_pins {
 		pinctrl-single,pins = <
 			OMAP3_CORE1_IOPAD(0x20b4, PIN_INPUT_PULLDOWN | MUX_MODE4)	/* gpmc_ncs3.gpio_54 */
 			OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE4)		/* dss_data16.gpio_86 */
 			OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE4)		/* uart3_rts_sd.gpio_164 */
 		>;
 	};
 	gpmc_pins: pinmux_gpmc_pins {
 		pinctrl-single,pins = <
 			/* address lines */
                         OMAP3_CORE1_IOPAD(0x207a, PIN_OUTPUT | MUX_MODE0)       /* gpmc_a1.gpmc_a1 */
                         OMAP3_CORE1_IOPAD(0x207c, PIN_OUTPUT | MUX_MODE0)       /* gpmc_a2.gpmc_a2 */
                         OMAP3_CORE1_IOPAD(0x207e, PIN_OUTPUT | MUX_MODE0)       /* gpmc_a3.gpmc_a3 */
 			/* data lines, gpmc_d0..d7 not muxable according to TRM */
                         OMAP3_CORE1_IOPAD(0x209e, PIN_INPUT | MUX_MODE0)        /* gpmc_d8.gpmc_d8 */
                         OMAP3_CORE1_IOPAD(0x20a0, PIN_INPUT | MUX_MODE0)        /* gpmc_d9.gpmc_d9 */
                         OMAP3_CORE1_IOPAD(0x20a2, PIN_INPUT | MUX_MODE0)        /* gpmc_d10.gpmc_d10 */
                         OMAP3_CORE1_IOPAD(0x20a4, PIN_INPUT | MUX_MODE0)        /* gpmc_d11.gpmc_d11 */
                         OMAP3_CORE1_IOPAD(0x20a6, PIN_INPUT | MUX_MODE0)        /* gpmc_d12.gpmc_d12 */
                         OMAP3_CORE1_IOPAD(0x20a8, PIN_INPUT | MUX_MODE0)        /* gpmc_d13.gpmc_d13 */
                         OMAP3_CORE1_IOPAD(0x20aa, PIN_INPUT | MUX_MODE0)        /* gpmc_d14.gpmc_d14 */
                         OMAP3_CORE1_IOPAD(0x20ac, PIN_INPUT | MUX_MODE0)        /* gpmc_d15.gpmc_d15 */
 			/*
 			 * gpmc_ncs0, gpmc_nadv_ale, gpmc_noe, gpmc_nwe, gpmc_wait0 not muxable
 			 * according to TRM. OneNAND seems to require PIN_INPUT on clock.
 			 */
                         OMAP3_CORE1_IOPAD(0x20b0, PIN_OUTPUT | MUX_MODE0)       /* gpmc_ncs1.gpmc_ncs1 */
                         OMAP3_CORE1_IOPAD(0x20be, PIN_INPUT | MUX_MODE0)        /* gpmc_clk.gpmc_clk */
 		>;
 	};
 	i2c1_pins: pinmux_i2c1_pins {
 		pinctrl-single,pins = <
 			0x18a (PIN_INPUT | MUX_MODE0)		/* i2c1_scl */
 			0x18c (PIN_INPUT | MUX_MODE0)		/* i2c1_sda */
 		>;
 	};
 	i2c2_pins: pinmux_i2c2_pins {
 		pinctrl-single,pins = <
 			0x18e (PIN_INPUT | MUX_MODE0)		/* i2c2_scl */
 			0x190 (PIN_INPUT | MUX_MODE0)		/* i2c2_sda */
 		>;
 	};
 	i2c3_pins: pinmux_i2c3_pins {
 		pinctrl-single,pins = <
 			0x192 (PIN_INPUT | MUX_MODE0)		/* i2c3_scl */
 			0x194 (PIN_INPUT | MUX_MODE0)		/* i2c3_sda */
 		>;
 	};
 	debug_leds: pinmux_debug_led_pins {
 		pinctrl-single,pins = <
 			OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4)	/* mcbsp1_clkx.gpio_162 */
 		>;
 	};
 	mcspi4_pins: pinmux_mcspi4_pins {
 		pinctrl-single,pins = <
 			0x15c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_clk */
 			0x162 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_somi */
 			0x160 (PIN_OUTPUT | MUX_MODE1) /* mcspi4_simo */
 			0x166 (PIN_OUTPUT | MUX_MODE1) /* mcspi4_cs0 */
 		>;
 	};
 	mmc1_pins: pinmux_mmc1_pins {
 		pinctrl-single,pins = <
 			0x114 (PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc1_clk */
 			0x116 (PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc1_cmd */
 			0x118 (PIN_INPUT_PULLUP | MUX_MODE0) 	/* sdmmc1_dat0 */
 			0x11a (PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc1_dat1 */
 			0x11c (PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc1_dat2 */
 			0x11e (PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc1_dat3 */
 		>;
 	};
 	mmc2_pins: pinmux_mmc2_pins {
 		pinctrl-single,pins = <
 			0x128 (PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc2_clk */
 			0x12a (PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc2_cmd */
 			0x12c (PIN_INPUT_PULLUP | MUX_MODE0) 	/* sdmmc2_dat0 */
 			0x12e (PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc2_dat1 */
 			0x130 (PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc2_dat2 */
 			0x132 (PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc2_dat3 */
 			0x134 (PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc2_dat4 */
 			0x136 (PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc2_dat5 */
 			0x138 (PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc2_dat6 */
 			0x13a (PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc2_dat7 */
 		>;
 	};
 	acx565akm_pins: pinmux_acx565akm_pins {
 		pinctrl-single,pins = <
 			0x0d4 (PIN_OUTPUT | MUX_MODE4)		/* RX51_LCD_RESET_GPIO */
 		>;
 	};
 	dss_sdi_pins: pinmux_dss_sdi_pins {
 		pinctrl-single,pins = <
 			0x0c0 (PIN_OUTPUT | MUX_MODE1)   /* dss_data10.sdi_dat1n */
 			0x0c2 (PIN_OUTPUT | MUX_MODE1)   /* dss_data11.sdi_dat1p */
 			0x0c4 (PIN_OUTPUT | MUX_MODE1)   /* dss_data12.sdi_dat2n */
 			0x0c6 (PIN_OUTPUT | MUX_MODE1)   /* dss_data13.sdi_dat2p */
 			0x0d8 (PIN_OUTPUT | MUX_MODE1)   /* dss_data22.sdi_clkp */
 			0x0da (PIN_OUTPUT | MUX_MODE1)   /* dss_data23.sdi_clkn */
 		>;
 	};
 	wl1251_pins: pinmux_wl1251 {
 		pinctrl-single,pins = <
 			0x0ce (PIN_OUTPUT | MUX_MODE4)		/* gpio 87 => wl1251 enable */
 			0x05a (PIN_INPUT | MUX_MODE4)		/* gpio 42 => wl1251 irq */
 		>;
 	};
 	ssi_pins: pinmux_ssi {
 		pinctrl-single,pins = <
 			0x150 (PIN_INPUT_PULLUP | MUX_MODE1)	/* ssi1_rdy_tx */
 			0x14e (PIN_OUTPUT | MUX_MODE1)		/* ssi1_flag_tx */
 			0x152 (PIN_INPUT | WAKEUP_EN | MUX_MODE4) /* ssi1_wake_tx (cawake) */
 			0x14c (PIN_OUTPUT | MUX_MODE1)		/* ssi1_dat_tx */
 			0x154 (PIN_INPUT | MUX_MODE1)		/* ssi1_dat_rx */
 			0x156 (PIN_INPUT | MUX_MODE1)		/* ssi1_flag_rx */
 			0x158 (PIN_OUTPUT | MUX_MODE1)		/* ssi1_rdy_rx */
 			0x15a (PIN_OUTPUT | MUX_MODE1)		/* ssi1_wake */
 		>;
 	};
 	modem_pins: pinmux_modem {
 		pinctrl-single,pins = <
 			0x0ac (PIN_OUTPUT | MUX_MODE4)		/* gpio 70 => cmt_apeslpx */
 			0x0b0 (PIN_INPUT | WAKEUP_EN | MUX_MODE4) /* gpio 72 => ape_rst_rq */
 			0x0b2 (PIN_OUTPUT | MUX_MODE4)		/* gpio 73 => cmt_rst_rq */
 			0x0b4 (PIN_OUTPUT | MUX_MODE4)		/* gpio 74 => cmt_en */
 			0x0b6 (PIN_OUTPUT | MUX_MODE4)		/* gpio 75 => cmt_rst */
 			0x15e (PIN_OUTPUT | MUX_MODE4)		/* gpio 157 => cmt_bsi */
 		>;
 	};
 };
 &i2c1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&i2c1_pins>;
 	clock-frequency = <2200000>;
 	twl: twl@48 {
 		reg = <0x48>;
 		interrupts = <7>; /* SYS_NIRQ cascaded to intc */
 		interrupt-parent = <&intc>;
 	};
 };
 #include "twl4030.dtsi"
 #include "twl4030_omap3.dtsi"
 &vaux1 {
 	regulator-name = "V28";
 	regulator-min-microvolt = <2800000>;
 	regulator-max-microvolt = <2800000>;
 	regulator-always-on; /* due battery cover sensor */
 };
 &vaux2 {
 	regulator-name = "VCSI";
 	regulator-min-microvolt = <1800000>;
 	regulator-max-microvolt = <1800000>;
 };
 &vaux3 {
 	regulator-name = "VMMC2_30";
 	regulator-min-microvolt = <2800000>;
 	regulator-max-microvolt = <3000000>;
 };
 &vaux4 {
 	regulator-name = "VCAM_ANA_28";
 	regulator-min-microvolt = <2800000>;
 	regulator-max-microvolt = <2800000>;
 };
 &vmmc1 {
 	regulator-name = "VMMC1";
 	regulator-min-microvolt = <1850000>;
 	regulator-max-microvolt = <3150000>;
 };
 &vmmc2 {
 	regulator-name = "V28_A";
 	regulator-min-microvolt = <2800000>;
 	regulator-max-microvolt = <3000000>;
 	regulator-always-on; /* due VIO leak to AIC34 VDDs */
 };
 &vpll1 {
 	regulator-name = "VPLL";
 	regulator-min-microvolt = <1800000>;
 	regulator-max-microvolt = <1800000>;
 	regulator-always-on;
 };
 &vpll2 {
 	regulator-name = "VSDI_CSI";
 	regulator-min-microvolt = <1800000>;
 	regulator-max-microvolt = <1800000>;
 	regulator-always-on;
 };
 &vsim {
 	regulator-name = "VMMC2_IO_18";
 	regulator-min-microvolt = <1800000>;
 	regulator-max-microvolt = <1800000>;
 };
 &vio {
 	regulator-name = "VIO";
 	regulator-min-microvolt = <1800000>;
 	regulator-max-microvolt = <1800000>;
 };
 &vintana1 {
 	regulator-name = "VINTANA1";
 	/* fixed to 1500000 */
 	regulator-always-on;
 };
 &vintana2 {
 	regulator-name = "VINTANA2";
 	regulator-min-microvolt = <2750000>;
 	regulator-max-microvolt = <2750000>;
 	regulator-always-on;
 };
 &vintdig {
 	regulator-name = "VINTDIG";
 	/* fixed to 1500000 */
 	regulator-always-on;
 };
 &twl {
 	twl_audio: audio {
 		compatible = "ti,twl4030-audio";
 		ti,enable-vibra = <1>;
 	};
 	twl_power: power {
 		compatible = "ti,twl4030-power-n900", "ti,twl4030-power-idle-osc-off";
 		ti,use_poweroff;
 	};
 };
 &twl_keypad {
 	linux,keymap = < MATRIX_KEY(0x00, 0x00, KEY_Q)
 			 MATRIX_KEY(0x00, 0x01, KEY_O)
 			 MATRIX_KEY(0x00, 0x02, KEY_P)
 			 MATRIX_KEY(0x00, 0x03, KEY_COMMA)
 			 MATRIX_KEY(0x00, 0x04, KEY_BACKSPACE)
 			 MATRIX_KEY(0x00, 0x06, KEY_A)
 			 MATRIX_KEY(0x00, 0x07, KEY_S)
 			 MATRIX_KEY(0x01, 0x00, KEY_W)
 			 MATRIX_KEY(0x01, 0x01, KEY_D)
 			 MATRIX_KEY(0x01, 0x02, KEY_F)
 			 MATRIX_KEY(0x01, 0x03, KEY_G)
 			 MATRIX_KEY(0x01, 0x04, KEY_H)
 			 MATRIX_KEY(0x01, 0x05, KEY_J)
 			 MATRIX_KEY(0x01, 0x06, KEY_K)
 			 MATRIX_KEY(0x01, 0x07, KEY_L)
 			 MATRIX_KEY(0x02, 0x00, KEY_E)
 			 MATRIX_KEY(0x02, 0x01, KEY_DOT)
 			 MATRIX_KEY(0x02, 0x02, KEY_UP)
 			 MATRIX_KEY(0x02, 0x03, KEY_ENTER)
 			 MATRIX_KEY(0x02, 0x05, KEY_Z)
 			 MATRIX_KEY(0x02, 0x06, KEY_X)
 			 MATRIX_KEY(0x02, 0x07, KEY_C)
 			 MATRIX_KEY(0x02, 0x08, KEY_F9)
 			 MATRIX_KEY(0x03, 0x00, KEY_R)
 			 MATRIX_KEY(0x03, 0x01, KEY_V)
 			 MATRIX_KEY(0x03, 0x02, KEY_B)
 			 MATRIX_KEY(0x03, 0x03, KEY_N)
 			 MATRIX_KEY(0x03, 0x04, KEY_M)
 			 MATRIX_KEY(0x03, 0x05, KEY_SPACE)
 			 MATRIX_KEY(0x03, 0x06, KEY_SPACE)
 			 MATRIX_KEY(0x03, 0x07, KEY_LEFT)
 			 MATRIX_KEY(0x04, 0x00, KEY_T)
 			 MATRIX_KEY(0x04, 0x01, KEY_DOWN)
 			 MATRIX_KEY(0x04, 0x02, KEY_RIGHT)
 			 MATRIX_KEY(0x04, 0x04, KEY_LEFTCTRL)
 			 MATRIX_KEY(0x04, 0x05, KEY_RIGHTALT)
 			 MATRIX_KEY(0x04, 0x06, KEY_LEFTSHIFT)
 			 MATRIX_KEY(0x04, 0x08, KEY_F10)
 			 MATRIX_KEY(0x05, 0x00, KEY_Y)
 			 MATRIX_KEY(0x05, 0x08, KEY_F11)
 			 MATRIX_KEY(0x06, 0x00, KEY_U)
 			 MATRIX_KEY(0x07, 0x00, KEY_I)
 			 MATRIX_KEY(0x07, 0x01, KEY_F7)
 			 MATRIX_KEY(0x07, 0x02, KEY_F8)
 			 >;
 };
 &twl_gpio {
 	ti,pullups	= <0x0>;
 	ti,pulldowns	= <0x03ff3f>; /* BIT(0..5) | BIT(8..17) */
 };
 &i2c2 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&i2c2_pins>;
 	clock-frequency = <100000>;
 	tlv320aic3x: tlv320aic3x@18 {
 		compatible = "ti,tlv320aic3x";
 		reg = <0x18>;
 		gpio-reset = <&gpio2 28 GPIO_ACTIVE_HIGH>; /* 60 */
 		ai3x-gpio-func = <
 			0 /* AIC3X_GPIO1_FUNC_DISABLED */
 			5 /* AIC3X_GPIO2_FUNC_DIGITAL_MIC_INPUT */
 		>;
 		AVDD-supply = <&vmmc2>;
 		DRVDD-supply = <&vmmc2>;
 		IOVDD-supply = <&vio>;
 		DVDD-supply = <&vio>;
 	};
 	tlv320aic3x_aux: tlv320aic3x@19 {
 		compatible = "ti,tlv320aic3x";
 		reg = <0x19>;
 		gpio-reset = <&gpio2 28 GPIO_ACTIVE_HIGH>; /* 60 */
 		AVDD-supply = <&vmmc2>;
 		DRVDD-supply = <&vmmc2>;
 		IOVDD-supply = <&vio>;
 		DVDD-supply = <&vio>;
 	};
 	tsl2563: tsl2563@29 {
 		compatible = "amstaos,tsl2563";
 		reg = <0x29>;
 		amstaos,cover-comp-gain = <16>;
 	};
 	lp5523: lp5523@32 {
 		compatible = "national,lp5523";
 		reg = <0x32>;
 		clock-mode = /bits/ 8 <0>; /* LP55XX_CLOCK_AUTO */
 		enable-gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>; /* 41 */
 		chan0 {
 			chan-name = "lp5523:kb1";
 			led-cur = /bits/ 8 <50>;
 			max-cur = /bits/ 8 <100>;
 		};
 		chan1 {
 			chan-name = "lp5523:kb2";
 			led-cur = /bits/ 8 <50>;
 			max-cur = /bits/ 8 <100>;
 		};
 		chan2 {
 			chan-name = "lp5523:kb3";
 			led-cur = /bits/ 8 <50>;
 			max-cur = /bits/ 8 <100>;
 		};
 		chan3 {
 			chan-name = "lp5523:kb4";
 			led-cur = /bits/ 8 <50>;
 			max-cur = /bits/ 8 <100>;
 		};
 		chan4 {
 			chan-name = "lp5523:b";
 			led-cur = /bits/ 8 <50>;
 			max-cur = /bits/ 8 <100>;
 		};
 		chan5 {
 			chan-name = "lp5523:g";
 			led-cur = /bits/ 8 <50>;
 			max-cur = /bits/ 8 <100>;
 		};
 		chan6 {
 			chan-name = "lp5523:r";
 			led-cur = /bits/ 8 <50>;
 			max-cur = /bits/ 8 <100>;
 		};
 		chan7 {
 			chan-name = "lp5523:kb5";
 			led-cur = /bits/ 8 <50>;
 			max-cur = /bits/ 8 <100>;
 		};
 		chan8 {
 			chan-name = "lp5523:kb6";
 			led-cur = /bits/ 8 <50>;
 			max-cur = /bits/ 8 <100>;
 		};
 	};
 	bq27200: bq27200@55 {
 		compatible = "ti,bq27200";
 		reg = <0x55>;
 	};
 	tpa6130a2: tpa6130a2@60 {
 		compatible = "ti,tpa6130a2";
 		reg = <0x60>;
 		Vdd-supply = <&vmmc2>;
 		power-gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>; /* 98 */
 	};
 	si4713: si4713@63 {
 		compatible = "silabs,si4713";
                 reg = <0x63>;
                 interrupts-extended = <&gpio2 21 IRQ_TYPE_EDGE_FALLING>; /* 53 */
                 reset-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; /* 163 */
                 vio-supply = <&vio>;
                 vdd-supply = <&vaux1>;
 	};
 	bq24150a: bq24150a@6b {
 		compatible = "ti,bq24150a";
 		reg = <0x6b>;
 		ti,current-limit = <100>;
 		ti,weak-battery-voltage = <3400>;
 		ti,battery-regulation-voltage = <4200>;
 		ti,charge-current = <650>;
 		ti,termination-current = <100>;
 		ti,resistor-sense = <68>;
 		ti,usb-charger-detection = <&isp1704>;
 	};
 };
 &i2c3 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&i2c3_pins>;
 	clock-frequency = <400000>;
 };
 &mmc1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&mmc1_pins>;
 	vmmc-supply = <&vmmc1>;
 	bus-width = <4>;
 	cd-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>; /* 160 */
 };
 /* most boards use vaux3, only some old versions use vmmc2 instead */
 &mmc2 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&mmc2_pins>;
 	vmmc-supply = <&vaux3>;
 	vmmc_aux-supply = <&vsim>;
 	bus-width = <8>;
 	non-removable;
 };
 &mmc3 {
 	status = "disabled";
 };
 &gpmc {
 	ranges = <0 0 0x01000000 0x01000000>,	/* 16 MB for OneNAND */
 		 <1 0 0x02000000 0x01000000>;	/* 16 MB for smc91c96 */
 	pinctrl-names = "default";
 	pinctrl-0 = <&gpmc_pins>;
 	/* sys_ndmareq1 could be used by the driver, not as gpio65 though */
 	onenand@0,0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		reg = <0 0 0x20000>;	/* CS0, offset 0, IO size 128K */
 		gpmc,sync-read;
 		gpmc,sync-write;
 		gpmc,burst-length = <16>;
 		gpmc,burst-read;
 		gpmc,burst-wrap;
 		gpmc,burst-write;
 		gpmc,device-width = <2>; /* GPMC_DEVWIDTH_16BIT */
 		gpmc,mux-add-data = <2>; /* GPMC_MUX_AD */
 		gpmc,cs-on-ns = <0>;
 		gpmc,cs-rd-off-ns = <87>;
 		gpmc,cs-wr-off-ns = <87>;
 		gpmc,adv-on-ns = <0>;
 		gpmc,adv-rd-off-ns = <10>;
 		gpmc,adv-wr-off-ns = <10>;
 		gpmc,oe-on-ns = <15>;
 		gpmc,oe-off-ns = <87>;
 		gpmc,we-on-ns = <0>;
 		gpmc,we-off-ns = <87>;
 		gpmc,rd-cycle-ns = <112>;
 		gpmc,wr-cycle-ns = <112>;
 		gpmc,access-ns = <81>;
 		gpmc,page-burst-access-ns = <15>;
 		gpmc,bus-turnaround-ns = <0>;
 		gpmc,cycle2cycle-delay-ns = <0>;
 		gpmc,wait-monitoring-ns = <0>;
 		gpmc,clk-activation-ns = <5>;
 		gpmc,wr-data-mux-bus-ns = <30>;
 		gpmc,wr-access-ns = <81>;
 		gpmc,sync-clk-ps = <15000>;
 		/*
 		 * MTD partition table corresponding to Nokia's
 		 * Maemo 5 (Fremantle) release.
 		 */
 		partition@0 {
 			label = "bootloader";
 			reg = <0x00000000 0x00020000>;
 			read-only;
 		};
 		partition@1 {
 			label = "config";
 			reg = <0x00020000 0x00060000>;
 		};
 		partition@2 {
 			label = "log";
 			reg = <0x00080000 0x00040000>;
 		};
 		partition@3 {
 			label = "kernel";
 			reg = <0x000c0000 0x00200000>;
 		};
 		partition@4 {
 			label = "initfs";
 			reg = <0x002c0000 0x00200000>;
 		};
 		partition@5 {
 			label = "rootfs";
 			reg = <0x004c0000 0x0fb40000>;
 		};
 	};
+	/* Ethernet is on some early development boards and qemu */
 	ethernet@gpmc {
 		compatible = "smsc,lan91c94";
-		status = "disabled";
 		interrupt-parent = <&gpio2>;
 		interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;	/* gpio54 */
 		reg = <1 0x300 0xf>;		/* 16 byte IO range at offset 0x300 */
 		bank-width = <2>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&ethernet_pins>;
 		power-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>;	/* gpio86 */
 		reset-gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>;	/* gpio164 */
 		gpmc,device-width = <2>;
 		gpmc,sync-clk-ps = <0>;
 		gpmc,cs-on-ns = <0>;
 		gpmc,cs-rd-off-ns = <48>;
 		gpmc,cs-wr-off-ns = <24>;
 		gpmc,adv-on-ns = <0>;
 		gpmc,adv-rd-off-ns = <0>;
 		gpmc,adv-wr-off-ns = <0>;
 		gpmc,we-on-ns = <12>;
 		gpmc,we-off-ns = <18>;
 		gpmc,oe-on-ns = <12>;
 		gpmc,oe-off-ns = <48>;
 		gpmc,page-burst-access-ns = <0>;
 		gpmc,access-ns = <42>;
 		gpmc,rd-cycle-ns = <180>;
 		gpmc,wr-cycle-ns = <180>;
 		gpmc,bus-turnaround-ns = <0>;
 		gpmc,cycle2cycle-delay-ns = <0>;
 		gpmc,wait-monitoring-ns = <0>;
 		gpmc,clk-activation-ns = <0>;
 		gpmc,wr-access-ns = <0>;
 		gpmc,wr-data-mux-bus-ns = <12>;
 	};
 };
 &mcspi1 {
 	/*
 	 * For some reason, touchscreen is necessary for screen to work at
 	 * all on real hw. It works well without it on emulator.
 	 *
 	 * Also... order in the device tree actually matters here.
 	 */
 	tsc2005@0 {
 		compatible = "ti,tsc2005";
 		spi-max-frequency = <6000000>;
 		reg = <0>;
 		vio-supply = <&vio>;
 		reset-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* 104 */
 		interrupts-extended = <&gpio4 4 IRQ_TYPE_EDGE_RISING>; /* 100 */
 		touchscreen-fuzz-x = <4>;
 		touchscreen-fuzz-y = <7>;
 		touchscreen-fuzz-pressure = <2>;
 		touchscreen-max-x = <4096>;
 		touchscreen-max-y = <4096>;
 		touchscreen-max-pressure = <2048>;
 		ti,x-plate-ohms = <280>;
 		ti,esd-recovery-timeout-ms = <8000>;
 	};
 	acx565akm@2 {
 		compatible = "sony,acx565akm";
 		spi-max-frequency = <6000000>;
 		reg = <2>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&acx565akm_pins>;
 		label = "lcd";
 		reset-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* 90 */
 		port {
 			lcd_in: endpoint {
 				remote-endpoint = <&sdi_out>;
 			};
 		};
 	};
 };
 &mcspi4 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&mcspi4_pins>;
 	wl1251@0 {
 		pinctrl-names = "default";
 		pinctrl-0 = <&wl1251_pins>;
 		vio-supply = <&vio>;
 		compatible = "ti,wl1251";
 		reg = <0>;
 		spi-max-frequency = <48000000>;
 		spi-cpol;
 		spi-cpha;
 		ti,power-gpio = <&gpio3 23 GPIO_ACTIVE_HIGH>; /* 87 */
 		interrupt-parent = <&gpio2>;
 		interrupts = <10 IRQ_TYPE_NONE>; /* gpio line 42 */
 	};
 };
 &usb_otg_hs {
 	interface-type = <0>;
 	usb-phy = <&usb2_phy>;
 	phys = <&usb2_phy>;
 	phy-names = "usb2-phy";
 	mode = <2>;
 	power = <50>;
 };
 &uart1 {
 	status = "disabled";
 };
 &uart2 {
 	interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart2_pins>;
 };
 &uart3 {
 	interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart3_pins>;
 };
 &dss {
 	status = "ok";
 	pinctrl-names = "default";
 	pinctrl-0 = <&dss_sdi_pins>;
 	vdds_sdi-supply = <&vaux1>;
 	ports {
 		#address-cells = <1>;
 		#size-cells = <0>;
 		port@1 {
 			reg = <1>;
 			sdi_out: endpoint {
 				remote-endpoint = <&lcd_in>;
 				datapairs = <2>;
 			};
 		};
 	};
 };
 &venc {
 	status = "ok";
 	vdda-supply = <&vdac>;
 	port {
 		venc_out: endpoint {
 			remote-endpoint = <&tv_connector_in>;
 			ti,channels = <1>;
 		};
 	};
 };
 &mcbsp2 {
 	status = "ok";
 };
 &ssi_port1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&ssi_pins>;
 	ti,ssi-cawake-gpio = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* 151 */
 	modem: hsi-client {
 		compatible = "nokia,n900-modem";
 		pinctrl-names = "default";
 		pinctrl-0 = <&modem_pins>;
 		hsi-channel-ids = <0>, <1>, <2>, <3>;
 		hsi-channel-names = "mcsaab-control",
 				    "speech-control",
 				    "speech-data",
 				    "mcsaab-data";
 		hsi-speed-kbps = <55000>;
 		hsi-mode = "frame";
 		hsi-flow = "synchronized";
 		hsi-arb-mode = "round-robin";
 		interrupts-extended = <&gpio3 8 IRQ_TYPE_EDGE_FALLING>; /* 72 */
 		gpios = <&gpio3  6 GPIO_ACTIVE_HIGH>, /* 70 */
 			<&gpio3  9 GPIO_ACTIVE_HIGH>, /* 73 */
 			<&gpio3 10 GPIO_ACTIVE_HIGH>, /* 74 */
 			<&gpio3 11 GPIO_ACTIVE_HIGH>, /* 75 */
 			<&gpio5 29 GPIO_ACTIVE_HIGH>; /* 157 */
 		gpio-names = "cmt_apeslpx",
 			     "cmt_rst_rq",
 			     "cmt_en",
 			     "cmt_rst",
 			     "cmt_bsi";
 	};
 };
 &ssi_port2 {
 	status = "disabled";
 };

arch/arm/configs/omap2plus_defconfig

Diff comments View file @ e3db221

1	CONFIG_SYSVIPC=y	1	CONFIG_SYSVIPC=y
2	CONFIG_POSIX_MQUEUE=y	2	CONFIG_POSIX_MQUEUE=y
3	CONFIG_FHANDLE=y	3	CONFIG_FHANDLE=y
4	CONFIG_AUDIT=y	4	CONFIG_AUDIT=y
5	CONFIG_NO_HZ=y	5	CONFIG_NO_HZ=y
6	CONFIG_HIGH_RES_TIMERS=y	6	CONFIG_HIGH_RES_TIMERS=y
7	CONFIG_BSD_PROCESS_ACCT=y	7	CONFIG_BSD_PROCESS_ACCT=y
8	CONFIG_IKCONFIG=y	8	CONFIG_IKCONFIG=y
9	CONFIG_IKCONFIG_PROC=y	9	CONFIG_IKCONFIG_PROC=y
10	CONFIG_LOG_BUF_SHIFT=16	10	CONFIG_LOG_BUF_SHIFT=16
11	CONFIG_CGROUPS=y	11	CONFIG_CGROUPS=y
12	CONFIG_CGROUP_FREEZER=y	12	CONFIG_CGROUP_FREEZER=y
13	CONFIG_CGROUP_DEVICE=y	13	CONFIG_CGROUP_DEVICE=y
14	CONFIG_CPUSETS=y	14	CONFIG_CPUSETS=y
15	CONFIG_CGROUP_CPUACCT=y	15	CONFIG_CGROUP_CPUACCT=y
16	CONFIG_RESOURCE_COUNTERS=y	16	CONFIG_RESOURCE_COUNTERS=y
17	CONFIG_MEMCG=y	17	CONFIG_MEMCG=y
18	CONFIG_MEMCG_SWAP=y	18	CONFIG_MEMCG_SWAP=y
19	CONFIG_MEMCG_KMEM=y	19	CONFIG_MEMCG_KMEM=y
20	CONFIG_CGROUP_PERF=y	20	CONFIG_CGROUP_PERF=y
21	CONFIG_CGROUP_SCHED=y	21	CONFIG_CGROUP_SCHED=y
22	CONFIG_CFS_BANDWIDTH=y	22	CONFIG_CFS_BANDWIDTH=y
23	CONFIG_RT_GROUP_SCHED=y	23	CONFIG_RT_GROUP_SCHED=y
24	CONFIG_BLK_CGROUP=y	24	CONFIG_BLK_CGROUP=y
25	CONFIG_NAMESPACES=y	25	CONFIG_NAMESPACES=y
26	CONFIG_BLK_DEV_INITRD=y	26	CONFIG_BLK_DEV_INITRD=y
27	CONFIG_EXPERT=y	27	CONFIG_EXPERT=y
28	CONFIG_SLAB=y	28	CONFIG_SLAB=y
29	CONFIG_PROFILING=y	29	CONFIG_PROFILING=y
30	CONFIG_OPROFILE=y	30	CONFIG_OPROFILE=y
31	CONFIG_KPROBES=y	31	CONFIG_KPROBES=y
32	CONFIG_MODULES=y	32	CONFIG_MODULES=y
33	CONFIG_MODULE_FORCE_LOAD=y	33	CONFIG_MODULE_FORCE_LOAD=y
34	CONFIG_MODULE_UNLOAD=y	34	CONFIG_MODULE_UNLOAD=y
35	CONFIG_MODULE_FORCE_UNLOAD=y	35	CONFIG_MODULE_FORCE_UNLOAD=y
36	CONFIG_MODVERSIONS=y	36	CONFIG_MODVERSIONS=y
37	CONFIG_MODULE_SRCVERSION_ALL=y	37	CONFIG_MODULE_SRCVERSION_ALL=y
38	# CONFIG_BLK_DEV_BSG is not set	38	# CONFIG_BLK_DEV_BSG is not set
39	CONFIG_PARTITION_ADVANCED=y	39	CONFIG_PARTITION_ADVANCED=y
40	CONFIG_ARCH_MULTI_V6=y	40	CONFIG_ARCH_MULTI_V6=y
41	CONFIG_POWER_AVS_OMAP=y	41	CONFIG_POWER_AVS_OMAP=y
42	CONFIG_POWER_AVS_OMAP_CLASS3=y	42	CONFIG_POWER_AVS_OMAP_CLASS3=y
43	CONFIG_OMAP_RESET_CLOCKS=y	43	CONFIG_OMAP_RESET_CLOCKS=y
44	CONFIG_OMAP_MUX_DEBUG=y	44	CONFIG_OMAP_MUX_DEBUG=y
45	CONFIG_ARCH_OMAP2=y	45	CONFIG_ARCH_OMAP2=y
46	CONFIG_ARCH_OMAP3=y	46	CONFIG_ARCH_OMAP3=y
47	CONFIG_ARCH_OMAP4=y	47	CONFIG_ARCH_OMAP4=y
48	CONFIG_SOC_OMAP5=y	48	CONFIG_SOC_OMAP5=y
49	CONFIG_SOC_AM33XX=y	49	CONFIG_SOC_AM33XX=y
50	CONFIG_SOC_AM43XX=y	50	CONFIG_SOC_AM43XX=y
51	CONFIG_SOC_DRA7XX=y	51	CONFIG_SOC_DRA7XX=y
52	CONFIG_ARM_THUMBEE=y	52	CONFIG_ARM_THUMBEE=y
53	CONFIG_ARM_ERRATA_411920=y	53	CONFIG_ARM_ERRATA_411920=y
54	CONFIG_ARM_ERRATA_430973=y	54	CONFIG_ARM_ERRATA_430973=y
55	CONFIG_SMP=y	55	CONFIG_SMP=y
56	CONFIG_NR_CPUS=2	56	CONFIG_NR_CPUS=2
57	CONFIG_CMA=y	57	CONFIG_CMA=y
58	CONFIG_SECCOMP=y	58	CONFIG_SECCOMP=y
59	CONFIG_ZBOOT_ROM_TEXT=0x0	59	CONFIG_ZBOOT_ROM_TEXT=0x0
60	CONFIG_ZBOOT_ROM_BSS=0x0	60	CONFIG_ZBOOT_ROM_BSS=0x0
61	CONFIG_ARM_APPENDED_DTB=y	61	CONFIG_ARM_APPENDED_DTB=y
62	CONFIG_ARM_ATAG_DTB_COMPAT=y	62	CONFIG_ARM_ATAG_DTB_COMPAT=y
63	CONFIG_CMDLINE="root=/dev/mmcblk0p2 rootwait console=ttyO2,115200"	63	CONFIG_CMDLINE="root=/dev/mmcblk0p2 rootwait console=ttyO2,115200"
64	CONFIG_KEXEC=y	64	CONFIG_KEXEC=y
65	CONFIG_CPU_FREQ=y	65	CONFIG_CPU_FREQ=y
66	CONFIG_CPU_FREQ_STAT_DETAILS=y	66	CONFIG_CPU_FREQ_STAT_DETAILS=y
67	CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y	67	CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
68	CONFIG_CPU_FREQ_GOV_POWERSAVE=y	68	CONFIG_CPU_FREQ_GOV_POWERSAVE=y
69	CONFIG_CPU_FREQ_GOV_USERSPACE=y	69	CONFIG_CPU_FREQ_GOV_USERSPACE=y
70	CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y	70	CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
71	CONFIG_GENERIC_CPUFREQ_CPU0=y	71	CONFIG_CPUFREQ_DT=y
72	# CONFIG_ARM_OMAP2PLUS_CPUFREQ is not set	72	# CONFIG_ARM_OMAP2PLUS_CPUFREQ is not set
73	CONFIG_CPU_IDLE=y	73	CONFIG_CPU_IDLE=y
74	CONFIG_BINFMT_MISC=y	74	CONFIG_BINFMT_MISC=y
75	CONFIG_PM_DEBUG=y	75	CONFIG_PM_DEBUG=y
76	CONFIG_NET=y	76	CONFIG_NET=y
77	CONFIG_PACKET=y	77	CONFIG_PACKET=y
78	CONFIG_UNIX=y	78	CONFIG_UNIX=y
79	CONFIG_XFRM_USER=y	79	CONFIG_XFRM_USER=y
80	CONFIG_NET_KEY=y	80	CONFIG_NET_KEY=y
81	CONFIG_NET_KEY_MIGRATE=y	81	CONFIG_NET_KEY_MIGRATE=y
82	CONFIG_INET=y	82	CONFIG_INET=y
83	CONFIG_IP_MULTICAST=y	83	CONFIG_IP_MULTICAST=y
84	CONFIG_IP_PNP=y	84	CONFIG_IP_PNP=y
85	CONFIG_IP_PNP_DHCP=y	85	CONFIG_IP_PNP_DHCP=y
86	CONFIG_IP_PNP_BOOTP=y	86	CONFIG_IP_PNP_BOOTP=y
87	CONFIG_IP_PNP_RARP=y	87	CONFIG_IP_PNP_RARP=y
88	# CONFIG_INET_LRO is not set	88	# CONFIG_INET_LRO is not set
89	CONFIG_NETFILTER=y	89	CONFIG_NETFILTER=y
90	CONFIG_CAN=m	90	CONFIG_CAN=m
91	CONFIG_CAN_C_CAN=m	91	CONFIG_CAN_C_CAN=m
92	CONFIG_CAN_C_CAN_PLATFORM=m	92	CONFIG_CAN_C_CAN_PLATFORM=m
93	CONFIG_BT=m	93	CONFIG_BT=m
94	CONFIG_BT_HCIUART=m	94	CONFIG_BT_HCIUART=m
95	CONFIG_BT_HCIUART_H4=y	95	CONFIG_BT_HCIUART_H4=y
96	CONFIG_BT_HCIUART_BCSP=y	96	CONFIG_BT_HCIUART_BCSP=y
97	CONFIG_BT_HCIUART_LL=y	97	CONFIG_BT_HCIUART_LL=y
98	CONFIG_BT_HCIBCM203X=m	98	CONFIG_BT_HCIBCM203X=m
99	CONFIG_BT_HCIBPA10X=m	99	CONFIG_BT_HCIBPA10X=m
100	CONFIG_CFG80211=m	100	CONFIG_CFG80211=m
101	CONFIG_MAC80211=m	101	CONFIG_MAC80211=m
102	CONFIG_DEVTMPFS=y	102	CONFIG_DEVTMPFS=y
103	CONFIG_DEVTMPFS_MOUNT=y	103	CONFIG_DEVTMPFS_MOUNT=y
104	CONFIG_DMA_CMA=y	104	CONFIG_DMA_CMA=y
105	CONFIG_OMAP_OCP2SCP=y	105	CONFIG_OMAP_OCP2SCP=y
106	CONFIG_CONNECTOR=y	106	CONFIG_CONNECTOR=y
107	CONFIG_MTD=y	107	CONFIG_MTD=y
108	CONFIG_MTD_CMDLINE_PARTS=y	108	CONFIG_MTD_CMDLINE_PARTS=y
109	CONFIG_MTD_BLOCK=y	109	CONFIG_MTD_BLOCK=y
110	CONFIG_MTD_OOPS=y	110	CONFIG_MTD_OOPS=y
111	CONFIG_MTD_CFI=y	111	CONFIG_MTD_CFI=y
112	CONFIG_MTD_CFI_INTELEXT=y	112	CONFIG_MTD_CFI_INTELEXT=y
113	CONFIG_MTD_NAND=y	113	CONFIG_MTD_NAND=y
114	CONFIG_MTD_NAND_ECC_BCH=y	114	CONFIG_MTD_NAND_ECC_BCH=y
115	CONFIG_MTD_NAND_OMAP2=y	115	CONFIG_MTD_NAND_OMAP2=y
116	CONFIG_MTD_ONENAND=y	116	CONFIG_MTD_ONENAND=y
117	CONFIG_MTD_ONENAND_VERIFY_WRITE=y	117	CONFIG_MTD_ONENAND_VERIFY_WRITE=y
118	CONFIG_MTD_ONENAND_OMAP2=y	118	CONFIG_MTD_ONENAND_OMAP2=y
119	CONFIG_MTD_UBI=y	119	CONFIG_MTD_UBI=y
120	CONFIG_BLK_DEV_LOOP=y	120	CONFIG_BLK_DEV_LOOP=y
121	CONFIG_BLK_DEV_RAM=y	121	CONFIG_BLK_DEV_RAM=y
122	CONFIG_BLK_DEV_RAM_SIZE=16384	122	CONFIG_BLK_DEV_RAM_SIZE=16384
123	CONFIG_SENSORS_TSL2550=m	123	CONFIG_SENSORS_TSL2550=m
124	CONFIG_BMP085_I2C=m	124	CONFIG_BMP085_I2C=m
125	CONFIG_SENSORS_LIS3_I2C=m	125	CONFIG_SENSORS_LIS3_I2C=m
126	CONFIG_SRAM=y	126	CONFIG_SRAM=y
127	CONFIG_SCSI=y	127	CONFIG_SCSI=y
128	CONFIG_BLK_DEV_SD=y	128	CONFIG_BLK_DEV_SD=y
129	CONFIG_SCSI_SCAN_ASYNC=y	129	CONFIG_SCSI_SCAN_ASYNC=y
130	CONFIG_ATA=y	130	CONFIG_ATA=y
131	CONFIG_SATA_AHCI_PLATFORM=y	131	CONFIG_SATA_AHCI_PLATFORM=y
132	CONFIG_MD=y	132	CONFIG_MD=y
133	CONFIG_NETDEVICES=y	133	CONFIG_NETDEVICES=y
134	# CONFIG_NET_VENDOR_ARC is not set	134	# CONFIG_NET_VENDOR_ARC is not set
135	# CONFIG_NET_CADENCE is not set	135	# CONFIG_NET_CADENCE is not set
136	# CONFIG_NET_VENDOR_BROADCOM is not set	136	# CONFIG_NET_VENDOR_BROADCOM is not set
137	# CONFIG_NET_VENDOR_CIRRUS is not set	137	# CONFIG_NET_VENDOR_CIRRUS is not set
138	# CONFIG_NET_VENDOR_FARADAY is not set	138	# CONFIG_NET_VENDOR_FARADAY is not set
139	# CONFIG_NET_VENDOR_HISILICON is not set	139	# CONFIG_NET_VENDOR_HISILICON is not set
140	# CONFIG_NET_VENDOR_INTEL is not set	140	# CONFIG_NET_VENDOR_INTEL is not set
141	# CONFIG_NET_VENDOR_MARVELL is not set	141	# CONFIG_NET_VENDOR_MARVELL is not set
142	CONFIG_KS8851=y	142	CONFIG_KS8851=y
143	CONFIG_KS8851_MLL=y	143	CONFIG_KS8851_MLL=y
144	# CONFIG_NET_VENDOR_MICROCHIP is not set	144	# CONFIG_NET_VENDOR_MICROCHIP is not set
145	# CONFIG_NET_VENDOR_NATSEMI is not set	145	# CONFIG_NET_VENDOR_NATSEMI is not set
146	# CONFIG_NET_VENDOR_QUALCOMM is not set	146	# CONFIG_NET_VENDOR_QUALCOMM is not set
147	# CONFIG_NET_VENDOR_SAMSUNG is not set	147	# CONFIG_NET_VENDOR_SAMSUNG is not set
148	# CONFIG_NET_VENDOR_SEEQ is not set	148	# CONFIG_NET_VENDOR_SEEQ is not set
149	CONFIG_SMC91X=y	149	CONFIG_SMC91X=y
150	CONFIG_SMSC911X=y	150	CONFIG_SMSC911X=y
151	# CONFIG_NET_VENDOR_STMICRO is not set	151	# CONFIG_NET_VENDOR_STMICRO is not set
152	CONFIG_TI_CPSW=y	152	CONFIG_TI_CPSW=y
153	# CONFIG_NET_VENDOR_VIA is not set	153	# CONFIG_NET_VENDOR_VIA is not set
154	# CONFIG_NET_VENDOR_WIZNET is not set	154	# CONFIG_NET_VENDOR_WIZNET is not set
155	CONFIG_AT803X_PHY=y	155	CONFIG_AT803X_PHY=y
156	CONFIG_SMSC_PHY=y	156	CONFIG_SMSC_PHY=y
157	CONFIG_USB_USBNET=y	157	CONFIG_USB_USBNET=y
158	CONFIG_USB_NET_SMSC95XX=y	158	CONFIG_USB_NET_SMSC95XX=y
159	CONFIG_USB_ALI_M5632=y	159	CONFIG_USB_ALI_M5632=y
160	CONFIG_USB_AN2720=y	160	CONFIG_USB_AN2720=y
161	CONFIG_USB_EPSON2888=y	161	CONFIG_USB_EPSON2888=y
162	CONFIG_USB_KC2190=y	162	CONFIG_USB_KC2190=y
163	CONFIG_LIBERTAS=m	163	CONFIG_LIBERTAS=m
164	CONFIG_LIBERTAS_USB=m	164	CONFIG_LIBERTAS_USB=m
165	CONFIG_LIBERTAS_SDIO=m	165	CONFIG_LIBERTAS_SDIO=m
166	CONFIG_LIBERTAS_DEBUG=y	166	CONFIG_LIBERTAS_DEBUG=y
167	CONFIG_WL_TI=y	167	CONFIG_WL_TI=y
168	CONFIG_WL12XX=m	168	CONFIG_WL12XX=m
169	CONFIG_WL18XX=m	169	CONFIG_WL18XX=m
170	CONFIG_WLCORE_SPI=m	170	CONFIG_WLCORE_SPI=m
171	CONFIG_WLCORE_SDIO=m	171	CONFIG_WLCORE_SDIO=m
172	CONFIG_MWIFIEX=m	172	CONFIG_MWIFIEX=m
173	CONFIG_MWIFIEX_SDIO=m	173	CONFIG_MWIFIEX_SDIO=m
174	CONFIG_MWIFIEX_USB=m	174	CONFIG_MWIFIEX_USB=m
175	CONFIG_INPUT_JOYDEV=y	175	CONFIG_INPUT_JOYDEV=y
176	CONFIG_INPUT_EVDEV=y	176	CONFIG_INPUT_EVDEV=y
177	CONFIG_KEYBOARD_GPIO=y	177	CONFIG_KEYBOARD_GPIO=y
178	CONFIG_KEYBOARD_MATRIX=m	178	CONFIG_KEYBOARD_MATRIX=m
179	CONFIG_KEYBOARD_TWL4030=y	179	CONFIG_KEYBOARD_TWL4030=y
180	CONFIG_INPUT_TOUCHSCREEN=y	180	CONFIG_INPUT_TOUCHSCREEN=y
181	CONFIG_TOUCHSCREEN_ADS7846=m	181	CONFIG_TOUCHSCREEN_ADS7846=m
182	CONFIG_TOUCHSCREEN_EDT_FT5X06=m	182	CONFIG_TOUCHSCREEN_EDT_FT5X06=m
183	CONFIG_TOUCHSCREEN_TSC2005=m	183	CONFIG_TOUCHSCREEN_TSC2005=m
184	CONFIG_TOUCHSCREEN_TSC2007=m	184	CONFIG_TOUCHSCREEN_TSC2007=m
185	CONFIG_INPUT_MISC=y	185	CONFIG_INPUT_MISC=y
186	CONFIG_INPUT_TWL4030_PWRBUTTON=y	186	CONFIG_INPUT_TWL4030_PWRBUTTON=y
187	# CONFIG_LEGACY_PTYS is not set	187	# CONFIG_LEGACY_PTYS is not set
188	CONFIG_SERIAL_8250=y	188	CONFIG_SERIAL_8250=y
189	CONFIG_SERIAL_8250_CONSOLE=y	189	CONFIG_SERIAL_8250_CONSOLE=y
190	CONFIG_SERIAL_8250_NR_UARTS=32	190	CONFIG_SERIAL_8250_NR_UARTS=32
191	CONFIG_SERIAL_8250_EXTENDED=y	191	CONFIG_SERIAL_8250_EXTENDED=y
192	CONFIG_SERIAL_8250_MANY_PORTS=y	192	CONFIG_SERIAL_8250_MANY_PORTS=y
193	CONFIG_SERIAL_8250_SHARE_IRQ=y	193	CONFIG_SERIAL_8250_SHARE_IRQ=y
194	CONFIG_SERIAL_8250_DETECT_IRQ=y	194	CONFIG_SERIAL_8250_DETECT_IRQ=y
195	CONFIG_SERIAL_8250_RSA=y	195	CONFIG_SERIAL_8250_RSA=y
196	CONFIG_SERIAL_OF_PLATFORM=y	196	CONFIG_SERIAL_OF_PLATFORM=y
197	CONFIG_SERIAL_OMAP=y	197	CONFIG_SERIAL_OMAP=y
198	CONFIG_SERIAL_OMAP_CONSOLE=y	198	CONFIG_SERIAL_OMAP_CONSOLE=y
199	CONFIG_HW_RANDOM=y	199	CONFIG_HW_RANDOM=y
200	CONFIG_I2C_CHARDEV=y	200	CONFIG_I2C_CHARDEV=y
201	CONFIG_SPI=y	201	CONFIG_SPI=y
202	CONFIG_SPI_OMAP24XX=y	202	CONFIG_SPI_OMAP24XX=y
203	CONFIG_PINCTRL_SINGLE=y	203	CONFIG_PINCTRL_SINGLE=y
204	CONFIG_DEBUG_GPIO=y	204	CONFIG_DEBUG_GPIO=y
205	CONFIG_GPIO_SYSFS=y	205	CONFIG_GPIO_SYSFS=y
206	CONFIG_GPIO_TWL4030=y	206	CONFIG_GPIO_TWL4030=y
207	CONFIG_W1=y	207	CONFIG_W1=y
208	CONFIG_BATTERY_BQ27x00=m	208	CONFIG_BATTERY_BQ27x00=m
209	CONFIG_CHARGER_ISP1704=m	209	CONFIG_CHARGER_ISP1704=m
210	CONFIG_CHARGER_TWL4030=m	210	CONFIG_CHARGER_TWL4030=m
211	CONFIG_CHARGER_BQ2415X=m	211	CONFIG_CHARGER_BQ2415X=m
212	CONFIG_CHARGER_BQ24190=m	212	CONFIG_CHARGER_BQ24190=m
213	CONFIG_CHARGER_BQ24735=m	213	CONFIG_CHARGER_BQ24735=m
214	CONFIG_POWER_RESET=y	214	CONFIG_POWER_RESET=y
215	CONFIG_POWER_AVS=y	215	CONFIG_POWER_AVS=y
216	CONFIG_SENSORS_LM75=m	216	CONFIG_SENSORS_LM75=m
217	CONFIG_THERMAL=y	217	CONFIG_THERMAL=y
218	CONFIG_THERMAL_GOV_FAIR_SHARE=y	218	CONFIG_THERMAL_GOV_FAIR_SHARE=y
219	CONFIG_THERMAL_GOV_USER_SPACE=y	219	CONFIG_THERMAL_GOV_USER_SPACE=y
220	CONFIG_CPU_THERMAL=y	220	CONFIG_CPU_THERMAL=y
221	CONFIG_TI_SOC_THERMAL=y	221	CONFIG_TI_SOC_THERMAL=y
222	CONFIG_TI_THERMAL=y	222	CONFIG_TI_THERMAL=y
223	CONFIG_OMAP4_THERMAL=y	223	CONFIG_OMAP4_THERMAL=y
224	CONFIG_OMAP5_THERMAL=y	224	CONFIG_OMAP5_THERMAL=y
225	CONFIG_DRA752_THERMAL=y	225	CONFIG_DRA752_THERMAL=y
226	CONFIG_WATCHDOG=y	226	CONFIG_WATCHDOG=y
227	CONFIG_OMAP_WATCHDOG=y	227	CONFIG_OMAP_WATCHDOG=y
228	CONFIG_TWL4030_WATCHDOG=y	228	CONFIG_TWL4030_WATCHDOG=y
229	CONFIG_MFD_SYSCON=y	229	CONFIG_MFD_SYSCON=y
230	CONFIG_MFD_PALMAS=y	230	CONFIG_MFD_PALMAS=y
231	CONFIG_MFD_TPS65217=y	231	CONFIG_MFD_TPS65217=y
232	CONFIG_MFD_TPS65218=y	232	CONFIG_MFD_TPS65218=y
233	CONFIG_MFD_TPS65910=y	233	CONFIG_MFD_TPS65910=y
234	CONFIG_TWL6040_CORE=y	234	CONFIG_TWL6040_CORE=y
235	CONFIG_REGULATOR_PALMAS=y	235	CONFIG_REGULATOR_PALMAS=y
236	CONFIG_REGULATOR_PBIAS=y	236	CONFIG_REGULATOR_PBIAS=y
237	CONFIG_REGULATOR_TI_ABB=y	237	CONFIG_REGULATOR_TI_ABB=y
238	CONFIG_REGULATOR_TPS65023=y	238	CONFIG_REGULATOR_TPS65023=y
239	CONFIG_REGULATOR_TPS6507X=y	239	CONFIG_REGULATOR_TPS6507X=y
240	CONFIG_REGULATOR_TPS65217=y	240	CONFIG_REGULATOR_TPS65217=y
241	CONFIG_REGULATOR_TPS65218=y	241	CONFIG_REGULATOR_TPS65218=y
242	CONFIG_REGULATOR_TPS65910=y	242	CONFIG_REGULATOR_TPS65910=y
243	CONFIG_REGULATOR_TWL4030=y	243	CONFIG_REGULATOR_TWL4030=y
244	CONFIG_FB=y	244	CONFIG_FB=y
245	CONFIG_FIRMWARE_EDID=y	245	CONFIG_FIRMWARE_EDID=y
246	CONFIG_FB_MODE_HELPERS=y	246	CONFIG_FB_MODE_HELPERS=y
247	CONFIG_FB_TILEBLITTING=y	247	CONFIG_FB_TILEBLITTING=y
248	CONFIG_OMAP2_DSS=m	248	CONFIG_OMAP2_DSS=m
249	CONFIG_OMAP5_DSS_HDMI=y	249	CONFIG_OMAP5_DSS_HDMI=y
250	CONFIG_OMAP2_DSS_SDI=y	250	CONFIG_OMAP2_DSS_SDI=y
251	CONFIG_OMAP2_DSS_DSI=y	251	CONFIG_OMAP2_DSS_DSI=y
252	CONFIG_FB_OMAP2=m	252	CONFIG_FB_OMAP2=m
253	CONFIG_DISPLAY_ENCODER_TFP410=m	253	CONFIG_DISPLAY_ENCODER_TFP410=m
254	CONFIG_DISPLAY_ENCODER_TPD12S015=m	254	CONFIG_DISPLAY_ENCODER_TPD12S015=m
255	CONFIG_DISPLAY_CONNECTOR_DVI=m	255	CONFIG_DISPLAY_CONNECTOR_DVI=m
256	CONFIG_DISPLAY_CONNECTOR_HDMI=m	256	CONFIG_DISPLAY_CONNECTOR_HDMI=m
257	CONFIG_DISPLAY_CONNECTOR_ANALOG_TV=m	257	CONFIG_DISPLAY_CONNECTOR_ANALOG_TV=m
258	CONFIG_DISPLAY_PANEL_DPI=m	258	CONFIG_DISPLAY_PANEL_DPI=m
259	CONFIG_DISPLAY_PANEL_DSI_CM=m	259	CONFIG_DISPLAY_PANEL_DSI_CM=m
260	CONFIG_DISPLAY_PANEL_SONY_ACX565AKM=m	260	CONFIG_DISPLAY_PANEL_SONY_ACX565AKM=m
261	CONFIG_DISPLAY_PANEL_LGPHILIPS_LB035Q02=m	261	CONFIG_DISPLAY_PANEL_LGPHILIPS_LB035Q02=m
262	CONFIG_DISPLAY_PANEL_SHARP_LS037V7DW01=m	262	CONFIG_DISPLAY_PANEL_SHARP_LS037V7DW01=m
263	CONFIG_DISPLAY_PANEL_TPO_TD028TTEC1=m	263	CONFIG_DISPLAY_PANEL_TPO_TD028TTEC1=m
264	CONFIG_DISPLAY_PANEL_TPO_TD043MTEA1=m	264	CONFIG_DISPLAY_PANEL_TPO_TD043MTEA1=m
265	CONFIG_DISPLAY_PANEL_NEC_NL8048HL11=m	265	CONFIG_DISPLAY_PANEL_NEC_NL8048HL11=m
266	CONFIG_BACKLIGHT_LCD_SUPPORT=y	266	CONFIG_BACKLIGHT_LCD_SUPPORT=y
267	CONFIG_LCD_CLASS_DEVICE=y	267	CONFIG_LCD_CLASS_DEVICE=y
268	CONFIG_LCD_PLATFORM=y	268	CONFIG_LCD_PLATFORM=y
269	CONFIG_BACKLIGHT_CLASS_DEVICE=y	269	CONFIG_BACKLIGHT_CLASS_DEVICE=y
270	CONFIG_BACKLIGHT_GENERIC=m	270	CONFIG_BACKLIGHT_GENERIC=m
271	CONFIG_BACKLIGHT_PWM=m	271	CONFIG_BACKLIGHT_PWM=m
272	CONFIG_BACKLIGHT_PANDORA=m	272	CONFIG_BACKLIGHT_PANDORA=m
273	CONFIG_BACKLIGHT_GPIO=m	273	CONFIG_BACKLIGHT_GPIO=m
274	CONFIG_FRAMEBUFFER_CONSOLE=y	274	CONFIG_FRAMEBUFFER_CONSOLE=y
275	CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y	275	CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
276	CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y	276	CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
277	CONFIG_LOGO=y	277	CONFIG_LOGO=y
278	CONFIG_SOUND=m	278	CONFIG_SOUND=m
279	CONFIG_SND=m	279	CONFIG_SND=m
280	CONFIG_SND_MIXER_OSS=m	280	CONFIG_SND_MIXER_OSS=m
281	CONFIG_SND_PCM_OSS=m	281	CONFIG_SND_PCM_OSS=m
282	CONFIG_SND_VERBOSE_PRINTK=y	282	CONFIG_SND_VERBOSE_PRINTK=y
283	CONFIG_SND_DEBUG=y	283	CONFIG_SND_DEBUG=y
284	CONFIG_SND_USB_AUDIO=m	284	CONFIG_SND_USB_AUDIO=m
285	CONFIG_SND_SOC=m	285	CONFIG_SND_SOC=m
286	CONFIG_SND_EDMA_SOC=m	286	CONFIG_SND_EDMA_SOC=m
287	CONFIG_SND_AM33XX_SOC_EVM=m	287	CONFIG_SND_AM33XX_SOC_EVM=m
288	CONFIG_SND_OMAP_SOC=m	288	CONFIG_SND_OMAP_SOC=m
289	CONFIG_SND_OMAP_SOC_OMAP_TWL4030=m	289	CONFIG_SND_OMAP_SOC_OMAP_TWL4030=m
290	CONFIG_SND_OMAP_SOC_OMAP_ABE_TWL6040=m	290	CONFIG_SND_OMAP_SOC_OMAP_ABE_TWL6040=m
291	CONFIG_SND_OMAP_SOC_OMAP3_PANDORA=m	291	CONFIG_SND_OMAP_SOC_OMAP3_PANDORA=m
292	CONFIG_USB=y	292	CONFIG_USB=y
293	CONFIG_USB_ANNOUNCE_NEW_DEVICES=y	293	CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
294	CONFIG_USB_MON=y	294	CONFIG_USB_MON=y
295	CONFIG_USB_XHCI_HCD=m	295	CONFIG_USB_XHCI_HCD=m
296	CONFIG_USB_WDM=y	296	CONFIG_USB_WDM=y
297	CONFIG_USB_STORAGE=y	297	CONFIG_USB_STORAGE=y
298	CONFIG_USB_DWC3=m	298	CONFIG_USB_DWC3=m
299	CONFIG_USB_TEST=y	299	CONFIG_USB_TEST=y
300	CONFIG_AM335X_PHY_USB=y	300	CONFIG_AM335X_PHY_USB=y
301	CONFIG_USB_GADGET=y	301	CONFIG_USB_GADGET=y
302	CONFIG_USB_GADGET_DEBUG=y	302	CONFIG_USB_GADGET_DEBUG=y
303	CONFIG_USB_GADGET_DEBUG_FILES=y	303	CONFIG_USB_GADGET_DEBUG_FILES=y
304	CONFIG_USB_GADGET_DEBUG_FS=y	304	CONFIG_USB_GADGET_DEBUG_FS=y
305	CONFIG_USB_ZERO=m	305	CONFIG_USB_ZERO=m
306	CONFIG_MMC=y	306	CONFIG_MMC=y
307	CONFIG_SDIO_UART=y	307	CONFIG_SDIO_UART=y
308	CONFIG_MMC_OMAP=y	308	CONFIG_MMC_OMAP=y
309	CONFIG_MMC_OMAP_HS=y	309	CONFIG_MMC_OMAP_HS=y
310	CONFIG_NEW_LEDS=y	310	CONFIG_NEW_LEDS=y
311	CONFIG_LEDS_CLASS=y	311	CONFIG_LEDS_CLASS=y
312	CONFIG_LEDS_GPIO=y	312	CONFIG_LEDS_GPIO=y
313	CONFIG_LEDS_TRIGGERS=y	313	CONFIG_LEDS_TRIGGERS=y
314	CONFIG_LEDS_TRIGGER_TIMER=y	314	CONFIG_LEDS_TRIGGER_TIMER=y
315	CONFIG_LEDS_TRIGGER_ONESHOT=y	315	CONFIG_LEDS_TRIGGER_ONESHOT=y
316	CONFIG_LEDS_TRIGGER_HEARTBEAT=y	316	CONFIG_LEDS_TRIGGER_HEARTBEAT=y
317	CONFIG_LEDS_TRIGGER_BACKLIGHT=y	317	CONFIG_LEDS_TRIGGER_BACKLIGHT=y
318	CONFIG_LEDS_TRIGGER_CPU=y	318	CONFIG_LEDS_TRIGGER_CPU=y
319	CONFIG_LEDS_TRIGGER_GPIO=y	319	CONFIG_LEDS_TRIGGER_GPIO=y
320	CONFIG_LEDS_TRIGGER_DEFAULT_ON=y	320	CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
321	CONFIG_RTC_CLASS=y	321	CONFIG_RTC_CLASS=y
322	CONFIG_RTC_DRV_TWL92330=y	322	CONFIG_RTC_DRV_TWL92330=y
323	CONFIG_RTC_DRV_TWL4030=y	323	CONFIG_RTC_DRV_TWL4030=y
324	CONFIG_RTC_DRV_OMAP=y	324	CONFIG_RTC_DRV_OMAP=y
325	CONFIG_DMADEVICES=y	325	CONFIG_DMADEVICES=y
326	CONFIG_TI_EDMA=y	326	CONFIG_TI_EDMA=y
327	CONFIG_DMA_OMAP=y	327	CONFIG_DMA_OMAP=y
328	CONFIG_EXTCON=y	328	CONFIG_EXTCON=y
329	CONFIG_EXTCON_PALMAS=y	329	CONFIG_EXTCON_PALMAS=y
330	CONFIG_PWM=y	330	CONFIG_PWM=y
331	CONFIG_PWM_TIECAP=y	331	CONFIG_PWM_TIECAP=y
332	CONFIG_PWM_TIEHRPWM=y	332	CONFIG_PWM_TIEHRPWM=y
333	CONFIG_PWM_TWL=y	333	CONFIG_PWM_TWL=y
334	CONFIG_PWM_TWL_LED=y	334	CONFIG_PWM_TWL_LED=y
335	CONFIG_OMAP_USB2=y	335	CONFIG_OMAP_USB2=y
336	CONFIG_TI_PIPE3=y	336	CONFIG_TI_PIPE3=y
337	CONFIG_EXT2_FS=y	337	CONFIG_EXT2_FS=y
338	CONFIG_EXT3_FS=y	338	CONFIG_EXT3_FS=y
339	# CONFIG_EXT3_FS_XATTR is not set	339	# CONFIG_EXT3_FS_XATTR is not set
340	CONFIG_EXT4_FS=y	340	CONFIG_EXT4_FS=y
341	CONFIG_FANOTIFY=y	341	CONFIG_FANOTIFY=y
342	CONFIG_QUOTA=y	342	CONFIG_QUOTA=y
343	CONFIG_QFMT_V2=y	343	CONFIG_QFMT_V2=y
344	CONFIG_AUTOFS4_FS=m	344	CONFIG_AUTOFS4_FS=m
345	CONFIG_MSDOS_FS=y	345	CONFIG_MSDOS_FS=y
346	CONFIG_VFAT_FS=y	346	CONFIG_VFAT_FS=y
347	CONFIG_TMPFS=y	347	CONFIG_TMPFS=y
348	CONFIG_TMPFS_POSIX_ACL=y	348	CONFIG_TMPFS_POSIX_ACL=y
349	CONFIG_JFFS2_FS=y	349	CONFIG_JFFS2_FS=y
350	CONFIG_JFFS2_SUMMARY=y	350	CONFIG_JFFS2_SUMMARY=y
351	CONFIG_JFFS2_FS_XATTR=y	351	CONFIG_JFFS2_FS_XATTR=y
352	CONFIG_JFFS2_COMPRESSION_OPTIONS=y	352	CONFIG_JFFS2_COMPRESSION_OPTIONS=y
353	CONFIG_JFFS2_LZO=y	353	CONFIG_JFFS2_LZO=y
354	CONFIG_JFFS2_RUBIN=y	354	CONFIG_JFFS2_RUBIN=y
355	CONFIG_UBIFS_FS=y	355	CONFIG_UBIFS_FS=y
356	CONFIG_CRAMFS=y	356	CONFIG_CRAMFS=y
357	CONFIG_NFS_FS=y	357	CONFIG_NFS_FS=y
358	CONFIG_NFS_V3_ACL=y	358	CONFIG_NFS_V3_ACL=y
359	CONFIG_NFS_V4=y	359	CONFIG_NFS_V4=y
360	CONFIG_ROOT_NFS=y	360	CONFIG_ROOT_NFS=y
361	CONFIG_NLS_CODEPAGE_437=y	361	CONFIG_NLS_CODEPAGE_437=y
362	CONFIG_NLS_ISO8859_1=y	362	CONFIG_NLS_ISO8859_1=y
363	CONFIG_PRINTK_TIME=y	363	CONFIG_PRINTK_TIME=y
364	CONFIG_DEBUG_INFO=y	364	CONFIG_DEBUG_INFO=y
365	CONFIG_MAGIC_SYSRQ=y	365	CONFIG_MAGIC_SYSRQ=y
366	CONFIG_SCHEDSTATS=y	366	CONFIG_SCHEDSTATS=y
367	CONFIG_TIMER_STATS=y	367	CONFIG_TIMER_STATS=y
368	CONFIG_PROVE_LOCKING=y	368	CONFIG_PROVE_LOCKING=y
369	# CONFIG_DEBUG_BUGVERBOSE is not set	369	# CONFIG_DEBUG_BUGVERBOSE is not set
370	CONFIG_SECURITY=y	370	CONFIG_SECURITY=y
371	CONFIG_CRYPTO_MICHAEL_MIC=y	371	CONFIG_CRYPTO_MICHAEL_MIC=y
372	# CONFIG_CRYPTO_ANSI_CPRNG is not set	372	# CONFIG_CRYPTO_ANSI_CPRNG is not set
373	CONFIG_CRC_CCITT=y	373	CONFIG_CRC_CCITT=y
374	CONFIG_CRC_T10DIF=y	374	CONFIG_CRC_T10DIF=y
375	CONFIG_CRC_ITU_T=y	375	CONFIG_CRC_ITU_T=y
376	CONFIG_CRC7=y	376	CONFIG_CRC7=y
377	CONFIG_LIBCRC32C=y	377	CONFIG_LIBCRC32C=y
378	CONFIG_FONTS=y	378	CONFIG_FONTS=y
379	CONFIG_FONT_8x8=y	379	CONFIG_FONT_8x8=y
380	CONFIG_FONT_8x16=y	380	CONFIG_FONT_8x16=y
381		381

arch/arm/mach-omap2/board-generic.c

Diff comments View file @ e3db221

 /*
  * Copyright (C) 2005 Nokia Corporation
  * Author: Paul Mundt <paul.mundt@nokia.com>
  *
  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
  *
  * Modified from the original mach-omap/omap2/board-generic.c did by Paul
  * to support the OMAP2+ device tree boards with an unique board file.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
 #include <linux/io.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/irqdomain.h>
 #include <asm/mach/arch.h>
 #include "common.h"
 #if !(defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3))
 #define intc_of_init	NULL
 #endif
 #ifndef CONFIG_ARCH_OMAP4
 #define gic_of_init		NULL
 #endif
 static const struct of_device_id omap_dt_match_table[] __initconst = {
 	{ .compatible = "simple-bus", },
 	{ .compatible = "ti,omap-infra", },
 	{ }
 };
 static void __init omap_generic_init(void)
 {
 	omapdss_early_init_of();
 	pdata_quirks_init(omap_dt_match_table);
 	omapdss_init_of();
 }
 #ifdef CONFIG_SOC_OMAP2420
 static const char *const omap242x_boards_compat[] __initconst = {
 	"ti,omap2420",
 	NULL,
 };
 DT_MACHINE_START(OMAP242X_DT, "Generic OMAP2420 (Flattened Device Tree)")
 	.reserve	= omap_reserve,
 	.map_io		= omap242x_map_io,
 	.init_early	= omap2420_init_early,
 	.init_machine	= omap_generic_init,
 	.init_time	= omap2_sync32k_timer_init,
 	.dt_compat	= omap242x_boards_compat,
 	.restart	= omap2xxx_restart,
 MACHINE_END
 #endif
 #ifdef CONFIG_SOC_OMAP2430
 static const char *const omap243x_boards_compat[] __initconst = {
 	"ti,omap2430",
 	NULL,
 };
 DT_MACHINE_START(OMAP243X_DT, "Generic OMAP2430 (Flattened Device Tree)")
 	.reserve	= omap_reserve,
 	.map_io		= omap243x_map_io,
 	.init_early	= omap2430_init_early,
 	.init_machine	= omap_generic_init,
 	.init_time	= omap2_sync32k_timer_init,
 	.dt_compat	= omap243x_boards_compat,
 	.restart	= omap2xxx_restart,
 MACHINE_END
 #endif
 #ifdef CONFIG_ARCH_OMAP3
+/* Some boards need board name for legacy userspace in /proc/cpuinfo */
+static const char *const n900_boards_compat[] __initconst = {
+	"nokia,omap3-n900",
+	NULL,
+};
+DT_MACHINE_START(OMAP3_N900_DT, "Nokia RX-51 board")
+	.reserve	= omap_reserve,
+	.map_io		= omap3_map_io,
+	.init_early	= omap3430_init_early,
+	.init_machine	= omap_generic_init,
+	.init_late	= omap3_init_late,
+	.init_time	= omap3_sync32k_timer_init,
+	.dt_compat	= n900_boards_compat,
+	.restart	= omap3xxx_restart,
+MACHINE_END
+/* Generic omap3 boards, most boards can use these */
 static const char *const omap3_boards_compat[] __initconst = {
 	"ti,omap3430",
 	"ti,omap3",
 	NULL,
 };
 DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)")
 	.reserve	= omap_reserve,
 	.map_io		= omap3_map_io,
 	.init_early	= omap3430_init_early,
 	.init_machine	= omap_generic_init,
 	.init_late	= omap3_init_late,
 	.init_time	= omap3_sync32k_timer_init,
 	.dt_compat	= omap3_boards_compat,
 	.restart	= omap3xxx_restart,
 MACHINE_END
 static const char *const omap36xx_boards_compat[] __initconst = {
 	"ti,omap36xx",
 	NULL,
 };
 DT_MACHINE_START(OMAP36XX_DT, "Generic OMAP36xx (Flattened Device Tree)")
 	.reserve	= omap_reserve,
 	.map_io		= omap3_map_io,
 	.init_early	= omap3630_init_early,
 	.init_machine	= omap_generic_init,
 	.init_late	= omap3_init_late,
 	.init_time	= omap3_sync32k_timer_init,
 	.dt_compat	= omap36xx_boards_compat,
 	.restart	= omap3xxx_restart,
 MACHINE_END
 static const char *const omap3_gp_boards_compat[] __initconst = {
 	"ti,omap3-beagle",
 	"timll,omap3-devkit8000",
 	NULL,
 };
 DT_MACHINE_START(OMAP3_GP_DT, "Generic OMAP3-GP (Flattened Device Tree)")
 	.reserve	= omap_reserve,
 	.map_io		= omap3_map_io,
 	.init_early	= omap3430_init_early,
 	.init_machine	= omap_generic_init,
 	.init_late	= omap3_init_late,
 	.init_time	= omap3_secure_sync32k_timer_init,
 	.dt_compat	= omap3_gp_boards_compat,
 	.restart	= omap3xxx_restart,
 MACHINE_END
 static const char *const am3517_boards_compat[] __initconst = {
 	"ti,am3517",
 	NULL,
 };
 DT_MACHINE_START(AM3517_DT, "Generic AM3517 (Flattened Device Tree)")
 	.reserve	= omap_reserve,
 	.map_io		= omap3_map_io,
 	.init_early	= am35xx_init_early,
 	.init_machine	= omap_generic_init,
 	.init_late	= omap3_init_late,
 	.init_time	= omap3_gptimer_timer_init,
 	.dt_compat	= am3517_boards_compat,
 	.restart	= omap3xxx_restart,
 MACHINE_END
 #endif
 #ifdef CONFIG_SOC_AM33XX
 static const char *const am33xx_boards_compat[] __initconst = {
 	"ti,am33xx",
 	NULL,
 };
 DT_MACHINE_START(AM33XX_DT, "Generic AM33XX (Flattened Device Tree)")
 	.reserve	= omap_reserve,
 	.map_io		= am33xx_map_io,
 	.init_early	= am33xx_init_early,
 	.init_machine	= omap_generic_init,
 	.init_late	= am33xx_init_late,
 	.init_time	= omap3_gptimer_timer_init,
 	.dt_compat	= am33xx_boards_compat,
 	.restart	= am33xx_restart,
 MACHINE_END
 #endif
 #ifdef CONFIG_ARCH_OMAP4
 static const char *const omap4_boards_compat[] __initconst = {
 	"ti,omap4460",
 	"ti,omap4430",
 	"ti,omap4",
 	NULL,
 };
 DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)")
 	.reserve	= omap_reserve,
 	.smp		= smp_ops(omap4_smp_ops),
 	.map_io		= omap4_map_io,
 	.init_early	= omap4430_init_early,
 	.init_irq	= omap_gic_of_init,
 	.init_machine	= omap_generic_init,
 	.init_late	= omap4430_init_late,
 	.init_time	= omap4_local_timer_init,
 	.dt_compat	= omap4_boards_compat,
 	.restart	= omap44xx_restart,
 MACHINE_END
 #endif
 #ifdef CONFIG_SOC_OMAP5
 static const char *const omap5_boards_compat[] __initconst = {
 	"ti,omap5432",
 	"ti,omap5430",
 	"ti,omap5",
 	NULL,
 };
 DT_MACHINE_START(OMAP5_DT, "Generic OMAP5 (Flattened Device Tree)")
 	.reserve	= omap_reserve,
 	.smp		= smp_ops(omap4_smp_ops),
 	.map_io		= omap5_map_io,
 	.init_early	= omap5_init_early,
 	.init_irq	= omap_gic_of_init,
 	.init_machine	= omap_generic_init,
 	.init_late	= omap5_init_late,
 	.init_time	= omap5_realtime_timer_init,
 	.dt_compat	= omap5_boards_compat,
 	.restart	= omap44xx_restart,
 MACHINE_END
 #endif
 #ifdef CONFIG_SOC_AM43XX
 static const char *const am43_boards_compat[] __initconst = {
 	"ti,am4372",
 	"ti,am43",
 	NULL,
 };
 DT_MACHINE_START(AM43_DT, "Generic AM43 (Flattened Device Tree)")
 	.map_io		= am33xx_map_io,
 	.init_early	= am43xx_init_early,
 	.init_late	= am43xx_init_late,
 	.init_irq	= omap_gic_of_init,
 	.init_machine	= omap_generic_init,
 	.init_time	= omap3_gptimer_timer_init,
 	.dt_compat	= am43_boards_compat,
 	.restart	= omap44xx_restart,
 MACHINE_END
 #endif
 #ifdef CONFIG_SOC_DRA7XX
 static const char *const dra74x_boards_compat[] __initconst = {
 	"ti,am5728",
 	"ti,am5726",
 	"ti,dra742",
 	"ti,dra7",
 	NULL,
 };
 DT_MACHINE_START(DRA74X_DT, "Generic DRA74X (Flattened Device Tree)")
 	.reserve	= omap_reserve,
 	.smp		= smp_ops(omap4_smp_ops),
 	.map_io		= omap5_map_io,
 	.init_early	= dra7xx_init_early,
 	.init_late	= dra7xx_init_late,
 	.init_irq	= omap_gic_of_init,
 	.init_machine	= omap_generic_init,
 	.init_time	= omap5_realtime_timer_init,
 	.dt_compat	= dra74x_boards_compat,
 	.restart	= omap44xx_restart,
 MACHINE_END
 static const char *const dra72x_boards_compat[] __initconst = {
 	"ti,am5718",
 	"ti,am5716",
 	"ti,dra722",
 	NULL,
 };
 DT_MACHINE_START(DRA72X_DT, "Generic DRA72X (Flattened Device Tree)")
 	.reserve	= omap_reserve,
 	.map_io		= omap5_map_io,
 	.init_early	= dra7xx_init_early,
 	.init_late	= dra7xx_init_late,
 	.init_irq	= omap_gic_of_init,
 	.init_machine	= omap_generic_init,
 	.init_time	= omap5_realtime_timer_init,
 	.dt_compat	= dra72x_boards_compat,
 	.restart	= omap44xx_restart,
 MACHINE_END
 #endif

arch/arm/mach-omap2/common.h

Diff comments View file @ e3db221

 /*
  * Header for code common to all OMAP2+ machines.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms of the GNU General Public License as published by the
  * Free Software Foundation; either version 2 of the License, or (at your
  * option) any later version.
  *
  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  * You should have received a copy of the  GNU General Public License along
  * with this program; if not, write  to the Free Software Foundation, Inc.,
  * 675 Mass Ave, Cambridge, MA 02139, USA.
  */
 #ifndef __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H
 #define __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H
 #ifndef __ASSEMBLER__
 #include <linux/irq.h>
 #include <linux/delay.h>
 #include <linux/i2c.h>
 #include <linux/i2c/twl.h>
 #include <linux/i2c-omap.h>
 #include <linux/reboot.h>
 #include <linux/irqchip/irq-omap-intc.h>
 #include <asm/proc-fns.h>
 #include "i2c.h"
 #include "serial.h"
 #include "usb.h"
 #define OMAP_INTC_START		NR_IRQS
 #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP2)
 int omap2_pm_init(void);
 #else
 static inline int omap2_pm_init(void)
 {
 	return 0;
 }
 #endif
 #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
 int omap3_pm_init(void);
 #else
 static inline int omap3_pm_init(void)
 {
 	return 0;
 }
 #endif
 #if defined(CONFIG_PM) && (defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX))
 int omap4_pm_init(void);
 int omap4_pm_init_early(void);
 #else
 static inline int omap4_pm_init(void)
 {
 	return 0;
 }
 static inline int omap4_pm_init_early(void)
 {
 	return 0;
 }
 #endif
 #ifdef CONFIG_OMAP_MUX
 int omap_mux_late_init(void);
 #else
 static inline int omap_mux_late_init(void)
 {
 	return 0;
 }
 #endif
 extern void omap2_init_common_infrastructure(void);
 extern void omap2_sync32k_timer_init(void);
 extern void omap3_sync32k_timer_init(void);
 extern void omap3_secure_sync32k_timer_init(void);
 extern void omap3_gptimer_timer_init(void);
 extern void omap4_local_timer_init(void);
 #ifdef CONFIG_CACHE_L2X0
 int omap_l2_cache_init(void);
 #else
 static inline int omap_l2_cache_init(void)
 {
 	return 0;
 }
 #endif
 extern void omap5_realtime_timer_init(void);
 void omap2420_init_early(void);
 void omap2430_init_early(void);
 void omap3430_init_early(void);
 void omap35xx_init_early(void);
 void omap3630_init_early(void);
 void omap3_init_early(void);	/* Do not use this one */
 void am33xx_init_early(void);
 void am35xx_init_early(void);
 void ti81xx_init_early(void);
 void am33xx_init_early(void);
 void am43xx_init_early(void);
 void am43xx_init_late(void);
 void omap4430_init_early(void);
 void omap5_init_early(void);
 void omap3_init_late(void);	/* Do not use this one */
 void omap4430_init_late(void);
 void omap2420_init_late(void);
 void omap2430_init_late(void);
 void omap3430_init_late(void);
 void omap35xx_init_late(void);
 void omap3630_init_late(void);
 void am35xx_init_late(void);
 void ti81xx_init_late(void);
 void am33xx_init_late(void);
 void omap5_init_late(void);
 int omap2_common_pm_late_init(void);
 void dra7xx_init_early(void);
 void dra7xx_init_late(void);
 #ifdef CONFIG_SOC_BUS
 void omap_soc_device_init(void);
 #else
 static inline void omap_soc_device_init(void)
 {
 }
 #endif
 #if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
 void omap2xxx_restart(enum reboot_mode mode, const char *cmd);
 #else
 static inline void omap2xxx_restart(enum reboot_mode mode, const char *cmd)
 {
 }
 #endif
 #ifdef CONFIG_SOC_AM33XX
 void am33xx_restart(enum reboot_mode mode, const char *cmd);
 #else
 static inline void am33xx_restart(enum reboot_mode mode, const char *cmd)
 {
 }
 #endif
 #ifdef CONFIG_ARCH_OMAP3
 void omap3xxx_restart(enum reboot_mode mode, const char *cmd);
 #else
 static inline void omap3xxx_restart(enum reboot_mode mode, const char *cmd)
 {
 }
 #endif
 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
 	defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM43XX)
 void omap44xx_restart(enum reboot_mode mode, const char *cmd);
 #else
 static inline void omap44xx_restart(enum reboot_mode mode, const char *cmd)
 {
 }
 #endif
 /* This gets called from mach-omap2/io.c, do not call this */
 void __init omap2_set_globals_tap(u32 class, void __iomem *tap);
 void __init omap242x_map_io(void);
 void __init omap243x_map_io(void);
 void __init omap3_map_io(void);
 void __init am33xx_map_io(void);
 void __init omap4_map_io(void);
 void __init omap5_map_io(void);
 void __init ti81xx_map_io(void);
 /* omap_barriers_init() is OMAP4 only */
 void omap_barriers_init(void);
 /**
  * omap_test_timeout - busy-loop, testing a condition
  * @cond: condition to test until it evaluates to true
  * @timeout: maximum number of microseconds in the timeout
  * @index: loop index (integer)
  *
  * Loop waiting for @cond to become true or until at least @timeout
  * microseconds have passed.  To use, define some integer @index in the
  * calling code.  After running, if @index == @timeout, then the loop has
  * timed out.
  */
 #define omap_test_timeout(cond, timeout, index)			\
 ({								\
 	for (index = 0; index < timeout; index++) {		\
 		if (cond)					\
 			break;					\
 		udelay(1);					\
 	}							\
 })
 extern struct device *omap2_get_mpuss_device(void);
 extern struct device *omap2_get_iva_device(void);
 extern struct device *omap2_get_l3_device(void);
 extern struct device *omap4_get_dsp_device(void);
 void omap_gic_of_init(void);
 #ifdef CONFIG_CACHE_L2X0
 extern void __iomem *omap4_get_l2cache_base(void);
 #endif
 struct device_node;
 #ifdef CONFIG_SMP
 extern void __iomem *omap4_get_scu_base(void);
 #else
 static inline void __iomem *omap4_get_scu_base(void)
 {
 	return NULL;
 }
 #endif
 extern void gic_dist_disable(void);
 extern void gic_dist_enable(void);
 extern bool gic_dist_disabled(void);
 extern void gic_timer_retrigger(void);
 extern void omap_smc1(u32 fn, u32 arg);
 extern void __iomem *omap4_get_sar_ram_base(void);
 extern void omap_do_wfi(void);
 #ifdef CONFIG_SMP
 /* Needed for secondary core boot */
 extern void omap4_secondary_startup(void);
 extern void omap4460_secondary_startup(void);
 extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
 extern void omap_auxcoreboot_addr(u32 cpu_addr);
 extern u32 omap_read_auxcoreboot0(void);
 extern void omap4_cpu_die(unsigned int cpu);
 extern struct smp_operations omap4_smp_ops;
 extern void omap5_secondary_startup(void);
+extern void omap5_secondary_hyp_startup(void);
 #endif
 #if defined(CONFIG_SMP) && defined(CONFIG_PM)
 extern int omap4_mpuss_init(void);
 extern int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state);
 extern int omap4_finish_suspend(unsigned long cpu_state);
 extern void omap4_cpu_resume(void);
 extern int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state);
 #else
 static inline int omap4_enter_lowpower(unsigned int cpu,
 					unsigned int power_state)
 {
 	cpu_do_idle();
 	return 0;
 }
 static inline int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
 {
 	cpu_do_idle();
 	return 0;
 }
 static inline int omap4_mpuss_init(void)
 {
 	return 0;
 }
 static inline int omap4_finish_suspend(unsigned long cpu_state)
 {
 	return 0;
 }
 static inline void omap4_cpu_resume(void)
 {}
 #endif
 void pdata_quirks_init(const struct of_device_id *);
 void omap_auxdata_legacy_init(struct device *dev);
 void omap_pcs_legacy_init(int irq, void (*rearm)(void));
 struct omap_sdrc_params;
 extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
 				      struct omap_sdrc_params *sdrc_cs1);
 struct omap2_hsmmc_info;
 extern void omap_reserve(void);
 struct omap_hwmod;
 extern int omap_dss_reset(struct omap_hwmod *);
 /* SoC specific clock initializer */
 int omap_clk_init(void);
 int __init omapdss_init_of(void);
 void __init omapdss_early_init_of(void);
 #endif /* __ASSEMBLER__ */
 #endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */

arch/arm/mach-omap2/control.h

Diff comments View file @ e3db221

 /*
  * arch/arm/mach-omap2/control.h
  *
  * OMAP2/3/4 System Control Module definitions
  *
  * Copyright (C) 2007-2010 Texas Instruments, Inc.
  * Copyright (C) 2007-2008, 2010 Nokia Corporation
  *
  * Written by Paul Walmsley
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation.
  */
 #ifndef __ARCH_ARM_MACH_OMAP2_CONTROL_H
 #define __ARCH_ARM_MACH_OMAP2_CONTROL_H
 #include "am33xx.h"
 #ifndef __ASSEMBLY__
 #define OMAP242X_CTRL_REGADDR(reg)					\
 		OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
 #define OMAP243X_CTRL_REGADDR(reg)					\
 		OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
 #define OMAP343X_CTRL_REGADDR(reg)					\
 		OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
 #define AM33XX_CTRL_REGADDR(reg)					\
 		AM33XX_L4_WK_IO_ADDRESS(AM33XX_SCM_BASE + (reg))
 #else
 #define OMAP242X_CTRL_REGADDR(reg)					\
 		OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
 #define OMAP243X_CTRL_REGADDR(reg)					\
 		OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
 #define OMAP343X_CTRL_REGADDR(reg)					\
 		OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
 #define AM33XX_CTRL_REGADDR(reg)					\
 		AM33XX_L4_WK_IO_ADDRESS(AM33XX_SCM_BASE + (reg))
 #endif /* __ASSEMBLY__ */
 /*
  * As elsewhere, the "OMAP2_" prefix indicates that the macro is valid for
  * OMAP24XX and OMAP34XX.
  */
 /* Control submodule offsets */
 #define OMAP2_CONTROL_INTERFACE		0x000
 #define OMAP2_CONTROL_PADCONFS		0x030
 #define OMAP2_CONTROL_GENERAL		0x270
 #define OMAP343X_CONTROL_MEM_WKUP	0x600
 #define OMAP343X_CONTROL_PADCONFS_WKUP	0xa00
 #define OMAP343X_CONTROL_GENERAL_WKUP	0xa60
 /* TI81XX spefic control submodules */
 #define TI81XX_CONTROL_DEVCONF		0x600
 /* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */
 #define OMAP2_CONTROL_SYSCONFIG		(OMAP2_CONTROL_INTERFACE + 0x10)
 /* CONTROL_GENERAL register offsets common to OMAP2 & 3 */
 #define OMAP2_CONTROL_DEVCONF0		(OMAP2_CONTROL_GENERAL + 0x0004)
 #define OMAP2_CONTROL_MSUSPENDMUX_0	(OMAP2_CONTROL_GENERAL + 0x0020)
 #define OMAP2_CONTROL_MSUSPENDMUX_1	(OMAP2_CONTROL_GENERAL + 0x0024)
 #define OMAP2_CONTROL_MSUSPENDMUX_2	(OMAP2_CONTROL_GENERAL + 0x0028)
 #define OMAP2_CONTROL_MSUSPENDMUX_3	(OMAP2_CONTROL_GENERAL + 0x002c)
 #define OMAP2_CONTROL_MSUSPENDMUX_4	(OMAP2_CONTROL_GENERAL + 0x0030)
 #define OMAP2_CONTROL_MSUSPENDMUX_5	(OMAP2_CONTROL_GENERAL + 0x0034)
 #define OMAP2_CONTROL_SEC_CTRL		(OMAP2_CONTROL_GENERAL + 0x0040)
 #define OMAP2_CONTROL_RPUB_KEY_H_0	(OMAP2_CONTROL_GENERAL + 0x0090)
 #define OMAP2_CONTROL_RPUB_KEY_H_1	(OMAP2_CONTROL_GENERAL + 0x0094)
 #define OMAP2_CONTROL_RPUB_KEY_H_2	(OMAP2_CONTROL_GENERAL + 0x0098)
 #define OMAP2_CONTROL_RPUB_KEY_H_3	(OMAP2_CONTROL_GENERAL + 0x009c)
 /* 242x-only CONTROL_GENERAL register offsets */
 #define OMAP242X_CONTROL_DEVCONF	OMAP2_CONTROL_DEVCONF0 /* match TRM */
 #define OMAP242X_CONTROL_OCM_RAM_PERM	(OMAP2_CONTROL_GENERAL + 0x0068)
 /* 243x-only CONTROL_GENERAL register offsets */
 /* CONTROL_IVA2_BOOT{ADDR,MOD} are at the same place on 343x - noted below */
 #define OMAP243X_CONTROL_DEVCONF1	(OMAP2_CONTROL_GENERAL + 0x0078)
 #define OMAP243X_CONTROL_CSIRXFE	(OMAP2_CONTROL_GENERAL + 0x007c)
 #define OMAP243X_CONTROL_IVA2_BOOTADDR	(OMAP2_CONTROL_GENERAL + 0x0190)
 #define OMAP243X_CONTROL_IVA2_BOOTMOD	(OMAP2_CONTROL_GENERAL + 0x0194)
 #define OMAP243X_CONTROL_IVA2_GEMCFG	(OMAP2_CONTROL_GENERAL + 0x0198)
 #define OMAP243X_CONTROL_PBIAS_LITE	(OMAP2_CONTROL_GENERAL + 0x0230)
 /* 24xx-only CONTROL_GENERAL register offsets */
 #define OMAP24XX_CONTROL_DEBOBS		(OMAP2_CONTROL_GENERAL + 0x0000)
 #define OMAP24XX_CONTROL_EMU_SUPPORT	(OMAP2_CONTROL_GENERAL + 0x0008)
 #define OMAP24XX_CONTROL_SEC_TEST	(OMAP2_CONTROL_GENERAL + 0x0044)
 #define OMAP24XX_CONTROL_PSA_CTRL	(OMAP2_CONTROL_GENERAL + 0x0048)
 #define OMAP24XX_CONTROL_PSA_CMD	(OMAP2_CONTROL_GENERAL + 0x004c)
 #define OMAP24XX_CONTROL_PSA_VALUE	(OMAP2_CONTROL_GENERAL + 0x0050)
 #define OMAP24XX_CONTROL_SEC_EMU	(OMAP2_CONTROL_GENERAL + 0x0060)
 #define OMAP24XX_CONTROL_SEC_TAP	(OMAP2_CONTROL_GENERAL + 0x0064)
 #define OMAP24XX_CONTROL_OCM_PUB_RAM_ADD	(OMAP2_CONTROL_GENERAL + 0x006c)
 #define OMAP24XX_CONTROL_EXT_SEC_RAM_START_ADD	(OMAP2_CONTROL_GENERAL + 0x0070)
 #define OMAP24XX_CONTROL_EXT_SEC_RAM_STOP_ADD	(OMAP2_CONTROL_GENERAL + 0x0074)
 #define OMAP24XX_CONTROL_SEC_STATUS		(OMAP2_CONTROL_GENERAL + 0x0080)
 #define OMAP24XX_CONTROL_SEC_ERR_STATUS		(OMAP2_CONTROL_GENERAL + 0x0084)
 #define OMAP24XX_CONTROL_STATUS			(OMAP2_CONTROL_GENERAL + 0x0088)
 #define OMAP24XX_CONTROL_GENERAL_PURPOSE_STATUS	(OMAP2_CONTROL_GENERAL + 0x008c)
 #define OMAP24XX_CONTROL_RAND_KEY_0	(OMAP2_CONTROL_GENERAL + 0x00a0)
 #define OMAP24XX_CONTROL_RAND_KEY_1	(OMAP2_CONTROL_GENERAL + 0x00a4)
 #define OMAP24XX_CONTROL_RAND_KEY_2	(OMAP2_CONTROL_GENERAL + 0x00a8)
 #define OMAP24XX_CONTROL_RAND_KEY_3	(OMAP2_CONTROL_GENERAL + 0x00ac)
 #define OMAP24XX_CONTROL_CUST_KEY_0	(OMAP2_CONTROL_GENERAL + 0x00b0)
 #define OMAP24XX_CONTROL_CUST_KEY_1	(OMAP2_CONTROL_GENERAL + 0x00b4)
 #define OMAP24XX_CONTROL_TEST_KEY_0	(OMAP2_CONTROL_GENERAL + 0x00c0)
 #define OMAP24XX_CONTROL_TEST_KEY_1	(OMAP2_CONTROL_GENERAL + 0x00c4)
 #define OMAP24XX_CONTROL_TEST_KEY_2	(OMAP2_CONTROL_GENERAL + 0x00c8)
 #define OMAP24XX_CONTROL_TEST_KEY_3	(OMAP2_CONTROL_GENERAL + 0x00cc)
 #define OMAP24XX_CONTROL_TEST_KEY_4	(OMAP2_CONTROL_GENERAL + 0x00d0)
 #define OMAP24XX_CONTROL_TEST_KEY_5	(OMAP2_CONTROL_GENERAL + 0x00d4)
 #define OMAP24XX_CONTROL_TEST_KEY_6	(OMAP2_CONTROL_GENERAL + 0x00d8)
 #define OMAP24XX_CONTROL_TEST_KEY_7	(OMAP2_CONTROL_GENERAL + 0x00dc)
 #define OMAP24XX_CONTROL_TEST_KEY_8	(OMAP2_CONTROL_GENERAL + 0x00e0)
 #define OMAP24XX_CONTROL_TEST_KEY_9	(OMAP2_CONTROL_GENERAL + 0x00e4)
 #define OMAP343X_CONTROL_PADCONF_SYSNIRQ (OMAP2_CONTROL_INTERFACE + 0x01b0)
 /* 34xx-only CONTROL_GENERAL register offsets */
 #define OMAP343X_CONTROL_PADCONF_OFF	(OMAP2_CONTROL_GENERAL + 0x0000)
 #define OMAP343X_CONTROL_MEM_DFTRW0	(OMAP2_CONTROL_GENERAL + 0x0008)
 #define OMAP343X_CONTROL_MEM_DFTRW1	(OMAP2_CONTROL_GENERAL + 0x000c)
 #define OMAP343X_CONTROL_DEVCONF1	(OMAP2_CONTROL_GENERAL + 0x0068)
 #define OMAP343X_CONTROL_CSIRXFE		(OMAP2_CONTROL_GENERAL + 0x006c)
 #define OMAP343X_CONTROL_SEC_STATUS		(OMAP2_CONTROL_GENERAL + 0x0070)
 #define OMAP343X_CONTROL_SEC_ERR_STATUS		(OMAP2_CONTROL_GENERAL + 0x0074)
 #define OMAP343X_CONTROL_SEC_ERR_STATUS_DEBUG	(OMAP2_CONTROL_GENERAL + 0x0078)
 #define OMAP343X_CONTROL_STATUS			(OMAP2_CONTROL_GENERAL + 0x0080)
 #define OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS	(OMAP2_CONTROL_GENERAL + 0x0084)
 #define OMAP343X_CONTROL_RPUB_KEY_H_4	(OMAP2_CONTROL_GENERAL + 0x00a0)
 #define OMAP343X_CONTROL_RAND_KEY_0	(OMAP2_CONTROL_GENERAL + 0x00a8)
 #define OMAP343X_CONTROL_RAND_KEY_1	(OMAP2_CONTROL_GENERAL + 0x00ac)
 #define OMAP343X_CONTROL_RAND_KEY_2	(OMAP2_CONTROL_GENERAL + 0x00b0)
 #define OMAP343X_CONTROL_RAND_KEY_3	(OMAP2_CONTROL_GENERAL + 0x00b4)
 #define OMAP343X_CONTROL_TEST_KEY_0	(OMAP2_CONTROL_GENERAL + 0x00c8)
 #define OMAP343X_CONTROL_TEST_KEY_1	(OMAP2_CONTROL_GENERAL + 0x00cc)
 #define OMAP343X_CONTROL_TEST_KEY_2	(OMAP2_CONTROL_GENERAL + 0x00d0)
 #define OMAP343X_CONTROL_TEST_KEY_3	(OMAP2_CONTROL_GENERAL + 0x00d4)
 #define OMAP343X_CONTROL_TEST_KEY_4	(OMAP2_CONTROL_GENERAL + 0x00d8)
 #define OMAP343X_CONTROL_TEST_KEY_5	(OMAP2_CONTROL_GENERAL + 0x00dc)
 #define OMAP343X_CONTROL_TEST_KEY_6	(OMAP2_CONTROL_GENERAL + 0x00e0)
 #define OMAP343X_CONTROL_TEST_KEY_7	(OMAP2_CONTROL_GENERAL + 0x00e4)
 #define OMAP343X_CONTROL_TEST_KEY_8	(OMAP2_CONTROL_GENERAL + 0x00e8)
 #define OMAP343X_CONTROL_TEST_KEY_9	(OMAP2_CONTROL_GENERAL + 0x00ec)
 #define OMAP343X_CONTROL_TEST_KEY_10	(OMAP2_CONTROL_GENERAL + 0x00f0)
 #define OMAP343X_CONTROL_TEST_KEY_11	(OMAP2_CONTROL_GENERAL + 0x00f4)
 #define OMAP343X_CONTROL_TEST_KEY_12	(OMAP2_CONTROL_GENERAL + 0x00f8)
 #define OMAP343X_CONTROL_TEST_KEY_13	(OMAP2_CONTROL_GENERAL + 0x00fc)
 #define OMAP343X_CONTROL_FUSE_OPP1_VDD1 (OMAP2_CONTROL_GENERAL + 0x0110)
 #define OMAP343X_CONTROL_FUSE_OPP2_VDD1 (OMAP2_CONTROL_GENERAL + 0x0114)
 #define OMAP343X_CONTROL_FUSE_OPP3_VDD1 (OMAP2_CONTROL_GENERAL + 0x0118)
 #define OMAP343X_CONTROL_FUSE_OPP4_VDD1 (OMAP2_CONTROL_GENERAL + 0x011c)
 #define OMAP343X_CONTROL_FUSE_OPP5_VDD1 (OMAP2_CONTROL_GENERAL + 0x0120)
 #define OMAP343X_CONTROL_FUSE_OPP1_VDD2 (OMAP2_CONTROL_GENERAL + 0x0124)
 #define OMAP343X_CONTROL_FUSE_OPP2_VDD2 (OMAP2_CONTROL_GENERAL + 0x0128)
 #define OMAP343X_CONTROL_FUSE_OPP3_VDD2 (OMAP2_CONTROL_GENERAL + 0x012c)
 #define OMAP343X_CONTROL_FUSE_SR        (OMAP2_CONTROL_GENERAL + 0x0130)
 #define OMAP343X_CONTROL_IVA2_BOOTADDR	(OMAP2_CONTROL_GENERAL + 0x0190)
 #define OMAP343X_CONTROL_IVA2_BOOTMOD	(OMAP2_CONTROL_GENERAL + 0x0194)
 #define OMAP343X_CONTROL_DEBOBS(i)	(OMAP2_CONTROL_GENERAL + 0x01B0 \
 					+ ((i) >> 1) * 4 + (!((i) & 1)) * 2)
 #define OMAP343X_CONTROL_PROG_IO0	(OMAP2_CONTROL_GENERAL + 0x01D4)
 #define OMAP343X_CONTROL_PROG_IO1	(OMAP2_CONTROL_GENERAL + 0x01D8)
 #define OMAP343X_CONTROL_DSS_DPLL_SPREADING	(OMAP2_CONTROL_GENERAL + 0x01E0)
 #define OMAP343X_CONTROL_CORE_DPLL_SPREADING	(OMAP2_CONTROL_GENERAL + 0x01E4)
 #define OMAP343X_CONTROL_PER_DPLL_SPREADING	(OMAP2_CONTROL_GENERAL + 0x01E8)
 #define OMAP343X_CONTROL_USBHOST_DPLL_SPREADING	(OMAP2_CONTROL_GENERAL + 0x01EC)
 #define OMAP343X_CONTROL_PBIAS_LITE	(OMAP2_CONTROL_GENERAL + 0x02B0)
 #define OMAP343X_CONTROL_TEMP_SENSOR	(OMAP2_CONTROL_GENERAL + 0x02B4)
 #define OMAP343X_CONTROL_SRAMLDO4	(OMAP2_CONTROL_GENERAL + 0x02B8)
 #define OMAP343X_CONTROL_SRAMLDO5	(OMAP2_CONTROL_GENERAL + 0x02C0)
 #define OMAP343X_CONTROL_CSI		(OMAP2_CONTROL_GENERAL + 0x02C4)
 /* OMAP3630 only CONTROL_GENERAL register offsets */
 #define OMAP3630_CONTROL_FUSE_OPP1G_VDD1        (OMAP2_CONTROL_GENERAL + 0x0110)
 #define OMAP3630_CONTROL_FUSE_OPP50_VDD1        (OMAP2_CONTROL_GENERAL + 0x0114)
 #define OMAP3630_CONTROL_FUSE_OPP100_VDD1       (OMAP2_CONTROL_GENERAL + 0x0118)
 #define OMAP3630_CONTROL_FUSE_OPP120_VDD1       (OMAP2_CONTROL_GENERAL + 0x0120)
 #define OMAP3630_CONTROL_FUSE_OPP50_VDD2        (OMAP2_CONTROL_GENERAL + 0x0128)
 #define OMAP3630_CONTROL_FUSE_OPP100_VDD2       (OMAP2_CONTROL_GENERAL + 0x012C)
 #define OMAP3630_CONTROL_CAMERA_PHY_CTRL	(OMAP2_CONTROL_GENERAL + 0x02f0)
 /* OMAP44xx control efuse offsets */
 #define OMAP44XX_CONTROL_FUSE_IVA_OPP50		0x22C
 #define OMAP44XX_CONTROL_FUSE_IVA_OPP100	0x22F
 #define OMAP44XX_CONTROL_FUSE_IVA_OPPTURBO	0x232
 #define OMAP44XX_CONTROL_FUSE_IVA_OPPNITRO	0x235
 #define OMAP44XX_CONTROL_FUSE_MPU_OPP50		0x240
 #define OMAP44XX_CONTROL_FUSE_MPU_OPP100	0x243
 #define OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO	0x246
 #define OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO	0x249
 #define OMAP44XX_CONTROL_FUSE_CORE_OPP50	0x254
 #define OMAP44XX_CONTROL_FUSE_CORE_OPP100	0x257
 #define OMAP44XX_CONTROL_FUSE_CORE_OPP100OV	0x25A
 /* AM35XX only CONTROL_GENERAL register offsets */
 #define AM35XX_CONTROL_MSUSPENDMUX_6    (OMAP2_CONTROL_GENERAL + 0x0038)
 #define AM35XX_CONTROL_DEVCONF2         (OMAP2_CONTROL_GENERAL + 0x0310)
 #define AM35XX_CONTROL_DEVCONF3         (OMAP2_CONTROL_GENERAL + 0x0314)
 #define AM35XX_CONTROL_CBA_PRIORITY     (OMAP2_CONTROL_GENERAL + 0x0320)
 #define AM35XX_CONTROL_LVL_INTR_CLEAR   (OMAP2_CONTROL_GENERAL + 0x0324)
 #define AM35XX_CONTROL_IP_SW_RESET      (OMAP2_CONTROL_GENERAL + 0x0328)
 #define AM35XX_CONTROL_IPSS_CLK_CTRL    (OMAP2_CONTROL_GENERAL + 0x032C)
 /* 34xx PADCONF register offsets */
 #define OMAP343X_PADCONF_ETK(i)		(OMAP2_CONTROL_PADCONFS + 0x5a8 + \
 						(i)*2)
 #define OMAP343X_PADCONF_ETK_CLK	OMAP343X_PADCONF_ETK(0)
 #define OMAP343X_PADCONF_ETK_CTL	OMAP343X_PADCONF_ETK(1)
 #define OMAP343X_PADCONF_ETK_D0		OMAP343X_PADCONF_ETK(2)
 #define OMAP343X_PADCONF_ETK_D1		OMAP343X_PADCONF_ETK(3)
 #define OMAP343X_PADCONF_ETK_D2		OMAP343X_PADCONF_ETK(4)
 #define OMAP343X_PADCONF_ETK_D3		OMAP343X_PADCONF_ETK(5)
 #define OMAP343X_PADCONF_ETK_D4		OMAP343X_PADCONF_ETK(6)
 #define OMAP343X_PADCONF_ETK_D5		OMAP343X_PADCONF_ETK(7)
 #define OMAP343X_PADCONF_ETK_D6		OMAP343X_PADCONF_ETK(8)
 #define OMAP343X_PADCONF_ETK_D7		OMAP343X_PADCONF_ETK(9)
 #define OMAP343X_PADCONF_ETK_D8		OMAP343X_PADCONF_ETK(10)
 #define OMAP343X_PADCONF_ETK_D9		OMAP343X_PADCONF_ETK(11)
 #define OMAP343X_PADCONF_ETK_D10	OMAP343X_PADCONF_ETK(12)
 #define OMAP343X_PADCONF_ETK_D11	OMAP343X_PADCONF_ETK(13)
 #define OMAP343X_PADCONF_ETK_D12	OMAP343X_PADCONF_ETK(14)
 #define OMAP343X_PADCONF_ETK_D13	OMAP343X_PADCONF_ETK(15)
 #define OMAP343X_PADCONF_ETK_D14	OMAP343X_PADCONF_ETK(16)
 #define OMAP343X_PADCONF_ETK_D15	OMAP343X_PADCONF_ETK(17)
 /* 34xx GENERAL_WKUP register offsets */
 #define OMAP343X_CONTROL_WKUP_DEBOBSMUX(i) (OMAP343X_CONTROL_GENERAL_WKUP + \
 						0x008 + (i))
 #define OMAP343X_CONTROL_WKUP_DEBOBS0 (OMAP343X_CONTROL_GENERAL_WKUP + 0x008)
 #define OMAP343X_CONTROL_WKUP_DEBOBS1 (OMAP343X_CONTROL_GENERAL_WKUP + 0x00C)
 #define OMAP343X_CONTROL_WKUP_DEBOBS2 (OMAP343X_CONTROL_GENERAL_WKUP + 0x010)
 #define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP + 0x014)
 #define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP + 0x018)
 /* 36xx-only RTA - Retention till Access control registers and bits */
 #define OMAP36XX_CONTROL_MEM_RTA_CTRL	0x40C
 #define OMAP36XX_RTA_DISABLE		0x0
 /* 34xx D2D idle-related pins, handled by PM core */
 #define OMAP3_PADCONF_SAD2D_MSTANDBY   0x250
 #define OMAP3_PADCONF_SAD2D_IDLEACK    0x254
 /* TI81XX CONTROL_DEVCONF register offsets */
 #define TI81XX_CONTROL_DEVICE_ID	(TI81XX_CONTROL_DEVCONF + 0x000)
 /* OMAP4 CONTROL MODULE */
 #define OMAP4_CTRL_MODULE_PAD_WKUP			0x4a31e000
 #define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2	0x0604
 #define OMAP4_CTRL_MODULE_CORE_STATUS			0x02c4
 #define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1	0x0218
 #define OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR		0x0304
 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY	0x0618
 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_CAMERA_RX	0x0608
 /* OMAP4 CONTROL_DSIPHY */
 #define OMAP4_DSI2_LANEENABLE_SHIFT			29
 #define OMAP4_DSI2_LANEENABLE_MASK			(0x7 << 29)
 #define OMAP4_DSI1_LANEENABLE_SHIFT			24
 #define OMAP4_DSI1_LANEENABLE_MASK			(0x1f << 24)
 #define OMAP4_DSI1_PIPD_SHIFT				19
 #define OMAP4_DSI1_PIPD_MASK				(0x1f << 19)
 #define OMAP4_DSI2_PIPD_SHIFT				14
 #define OMAP4_DSI2_PIPD_MASK				(0x1f << 14)
 /* OMAP4 CONTROL_CAMERA_RX */
 #define OMAP4_CAMERARX_CSI21_LANEENABLE_SHIFT		24
 #define OMAP4_CAMERARX_CSI21_LANEENABLE_MASK		(0x1f << 24)
 #define OMAP4_CAMERARX_CSI22_LANEENABLE_SHIFT		29
 #define OMAP4_CAMERARX_CSI22_LANEENABLE_MASK		(0x3 << 29)
 #define OMAP4_CAMERARX_CSI22_CTRLCLKEN_SHIFT		21
 #define OMAP4_CAMERARX_CSI22_CTRLCLKEN_MASK		(1 << 21)
 #define OMAP4_CAMERARX_CSI22_CAMMODE_SHIFT		19
 #define OMAP4_CAMERARX_CSI22_CAMMODE_MASK		(0x3 << 19)
 #define OMAP4_CAMERARX_CSI21_CTRLCLKEN_SHIFT		18
 #define OMAP4_CAMERARX_CSI21_CTRLCLKEN_MASK		(1 << 18)
 #define OMAP4_CAMERARX_CSI21_CAMMODE_SHIFT		16
 #define OMAP4_CAMERARX_CSI21_CAMMODE_MASK		(0x3 << 16)
 /* OMAP54XX CONTROL STATUS register */
 #define OMAP5XXX_CONTROL_STATUS                0x134
 #define OMAP5_DEVICETYPE_MASK          (0x7 << 6)
+/* DRA7XX CONTROL CORE BOOTSTRAP */
+#define DRA7_CTRL_CORE_BOOTSTRAP	0x6c4
+#define DRA7_SPEEDSELECT_MASK		(0x3 << 8)
 /*
  * REVISIT: This list of registers is not comprehensive - there are more
  * that should be added.
  */
 /*
  * Control module register bit defines - these should eventually go into
  * their own regbits file.  Some of these will be complicated, depending
  * on the device type (general-purpose, emulator, test, secure, bad, other)
  * and the security mode (secure, non-secure, don't care)
  */
 /* CONTROL_DEVCONF0 bits */
 #define OMAP2_MMCSDIO1ADPCLKISEL	(1 << 24) /* MMC1 loop back clock */
 #define OMAP24XX_USBSTANDBYCTRL		(1 << 15)
 #define OMAP2_MCBSP2_CLKS_MASK		(1 << 6)
 #define OMAP2_MCBSP1_FSR_MASK		(1 << 4)
 #define OMAP2_MCBSP1_CLKR_MASK		(1 << 3)
 #define OMAP2_MCBSP1_CLKS_MASK		(1 << 2)
 /* CONTROL_DEVCONF1 bits */
 #define OMAP243X_MMC1_ACTIVE_OVERWRITE	(1 << 31)
 #define OMAP2_MMCSDIO2ADPCLKISEL	(1 << 6) /* MMC2 loop back clock */
 #define OMAP2_MCBSP5_CLKS_MASK		(1 << 4) /* > 242x */
 #define OMAP2_MCBSP4_CLKS_MASK		(1 << 2) /* > 242x */
 #define OMAP2_MCBSP3_CLKS_MASK		(1 << 0) /* > 242x */
 /* CONTROL_STATUS bits */
 #define OMAP2_DEVICETYPE_MASK		(0x7 << 8)
 #define OMAP2_SYSBOOT_5_MASK		(1 << 5)
 #define OMAP2_SYSBOOT_4_MASK		(1 << 4)
 #define OMAP2_SYSBOOT_3_MASK		(1 << 3)
 #define OMAP2_SYSBOOT_2_MASK		(1 << 2)
 #define OMAP2_SYSBOOT_1_MASK		(1 << 1)
 #define OMAP2_SYSBOOT_0_MASK		(1 << 0)
 /* CONTROL_PBIAS_LITE bits */
 #define OMAP343X_PBIASLITESUPPLY_HIGH1	(1 << 15)
 #define OMAP343X_PBIASLITEVMODEERROR1	(1 << 11)
 #define OMAP343X_PBIASSPEEDCTRL1	(1 << 10)
 #define OMAP343X_PBIASLITEPWRDNZ1	(1 << 9)
 #define OMAP343X_PBIASLITEVMODE1	(1 << 8)
 #define OMAP343X_PBIASLITESUPPLY_HIGH0	(1 << 7)
 #define OMAP343X_PBIASLITEVMODEERROR0	(1 << 3)
 #define OMAP2_PBIASSPEEDCTRL0		(1 << 2)
 #define OMAP2_PBIASLITEPWRDNZ0		(1 << 1)
 #define OMAP2_PBIASLITEVMODE0		(1 << 0)
 /* CONTROL_PROG_IO1 bits */
 #define OMAP3630_PRG_SDMMC1_SPEEDCTRL	(1 << 20)
 /* CONTROL_IVA2_BOOTMOD bits */
 #define OMAP3_IVA2_BOOTMOD_SHIFT	0
 #define OMAP3_IVA2_BOOTMOD_MASK		(0xf << 0)
 #define OMAP3_IVA2_BOOTMOD_IDLE		(0x1 << 0)
 /* CONTROL_PADCONF_X bits */
 #define OMAP3_PADCONF_WAKEUPEVENT0	(1 << 15)
 #define OMAP3_PADCONF_WAKEUPENABLE0	(1 << 14)
 #define OMAP343X_SCRATCHPAD_ROM		(OMAP343X_CTRL_BASE + 0x860)
 #define OMAP343X_SCRATCHPAD		(OMAP343X_CTRL_BASE + 0x910)
 #define OMAP343X_SCRATCHPAD_ROM_OFFSET	0x19C
 #define OMAP343X_SCRATCHPAD_REGADDR(reg)	OMAP2_L4_IO_ADDRESS(\
 						OMAP343X_SCRATCHPAD + reg)
 /* AM35XX_CONTROL_IPSS_CLK_CTRL bits */
 #define AM35XX_USBOTG_VBUSP_CLK_SHIFT	0
 #define AM35XX_CPGMAC_VBUSP_CLK_SHIFT	1
 #define AM35XX_VPFE_VBUSP_CLK_SHIFT	2
 #define AM35XX_HECC_VBUSP_CLK_SHIFT	3
 #define AM35XX_USBOTG_FCLK_SHIFT	8
 #define AM35XX_CPGMAC_FCLK_SHIFT	9
 #define AM35XX_VPFE_FCLK_SHIFT		10
 /* AM35XX CONTROL_LVL_INTR_CLEAR bits */
 #define AM35XX_CPGMAC_C0_MISC_PULSE_CLR	BIT(0)
 #define AM35XX_CPGMAC_C0_RX_PULSE_CLR	BIT(1)
 #define AM35XX_CPGMAC_C0_RX_THRESH_CLR	BIT(2)
 #define AM35XX_CPGMAC_C0_TX_PULSE_CLR	BIT(3)
 #define AM35XX_USBOTGSS_INT_CLR		BIT(4)
 #define AM35XX_VPFE_CCDC_VD0_INT_CLR	BIT(5)
 #define AM35XX_VPFE_CCDC_VD1_INT_CLR	BIT(6)
 #define AM35XX_VPFE_CCDC_VD2_INT_CLR	BIT(7)
 /* AM35XX CONTROL_IP_SW_RESET bits */
 #define AM35XX_USBOTGSS_SW_RST		BIT(0)
 #define AM35XX_CPGMACSS_SW_RST		BIT(1)
 #define AM35XX_VPFE_VBUSP_SW_RST	BIT(2)
 #define AM35XX_HECC_SW_RST		BIT(3)
 #define AM35XX_VPFE_PCLK_SW_RST		BIT(4)
 /* AM33XX CONTROL_STATUS register */
 #define AM33XX_CONTROL_STATUS		0x040
 #define AM33XX_CONTROL_SEC_CLK_CTRL	0x1bc
 /* AM33XX CONTROL_STATUS bitfields (partial) */
 #define AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT		22
 #define AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH		0x2
 #define AM33XX_CONTROL_STATUS_SYSBOOT1_MASK		(0x3 << 22)
 /* AM33XX PWMSS Control register */
 #define AM33XX_PWMSS_TBCLK_CLKCTRL			0x664
 /* AM33XX  PWMSS Control bitfields */
 #define AM33XX_PWMSS0_TBCLKEN_SHIFT			0
 #define AM33XX_PWMSS1_TBCLKEN_SHIFT			1
 #define AM33XX_PWMSS2_TBCLKEN_SHIFT			2
 /* DEV Feature register to identify AM33XX features */
 #define AM33XX_DEV_FEATURE		0x604
 #define AM33XX_SGX_MASK			BIT(29)
 /* CONTROL OMAP STATUS register to identify OMAP3 features */
 #define OMAP3_CONTROL_OMAP_STATUS	0x044c
 #define OMAP3_SGX_SHIFT			13
 #define OMAP3_SGX_MASK			(3 << OMAP3_SGX_SHIFT)
 #define		FEAT_SGX_FULL		0
 #define		FEAT_SGX_HALF		1
 #define		FEAT_SGX_NONE		2
 #define OMAP3_IVA_SHIFT			12
 #define OMAP3_IVA_MASK			(1 << OMAP3_IVA_SHIFT)
 #define		FEAT_IVA		0
 #define		FEAT_IVA_NONE		1
 #define OMAP3_L2CACHE_SHIFT		10
 #define OMAP3_L2CACHE_MASK		(3 << OMAP3_L2CACHE_SHIFT)
 #define		FEAT_L2CACHE_NONE	0
 #define		FEAT_L2CACHE_64KB	1
 #define		FEAT_L2CACHE_128KB	2
 #define		FEAT_L2CACHE_256KB	3
 #define OMAP3_ISP_SHIFT			5
 #define OMAP3_ISP_MASK			(1 << OMAP3_ISP_SHIFT)
 #define		FEAT_ISP		0
 #define		FEAT_ISP_NONE		1
 #define OMAP3_NEON_SHIFT		4
 #define OMAP3_NEON_MASK			(1 << OMAP3_NEON_SHIFT)
 #define		FEAT_NEON		0
 #define		FEAT_NEON_NONE		1
 #ifndef __ASSEMBLY__
 #ifdef CONFIG_ARCH_OMAP2PLUS
 extern void __iomem *omap_ctrl_base_get(void);
 extern u8 omap_ctrl_readb(u16 offset);
 extern u16 omap_ctrl_readw(u16 offset);
 extern u32 omap_ctrl_readl(u16 offset);
 extern u32 omap4_ctrl_pad_readl(u16 offset);
 extern void omap_ctrl_writeb(u8 val, u16 offset);
 extern void omap_ctrl_writew(u16 val, u16 offset);
 extern void omap_ctrl_writel(u32 val, u16 offset);
 extern void omap4_ctrl_pad_writel(u32 val, u16 offset);
 extern void omap3_save_scratchpad_contents(void);
 extern void omap3_clear_scratchpad_contents(void);
 extern void omap3_restore(void);
 extern void omap3_restore_es3(void);
 extern void omap3_restore_3630(void);
 extern u32 omap3_arm_context[128];
 extern void omap3_control_save_context(void);
 extern void omap3_control_restore_context(void);
 extern void omap3_ctrl_write_boot_mode(u8 bootmode);
 extern void omap_ctrl_write_dsp_boot_addr(u32 bootaddr);
 extern void omap_ctrl_write_dsp_boot_mode(u8 bootmode);
 extern void omap3630_ctrl_disable_rta(void);
 extern int omap3_ctrl_save_padconf(void);
 void omap3_ctrl_init(void);
 extern void omap2_set_globals_control(void __iomem *ctrl,
 				      void __iomem *ctrl_pad);
 #else
 #define omap_ctrl_base_get()		0
 #define omap_ctrl_readb(x)		0
 #define omap_ctrl_readw(x)		0
 #define omap_ctrl_readl(x)		0
 #define omap4_ctrl_pad_readl(x)		0
 #define omap_ctrl_writeb(x, y)		WARN_ON(1)
 #define omap_ctrl_writew(x, y)		WARN_ON(1)
 #define omap_ctrl_writel(x, y)		WARN_ON(1)
 #define omap4_ctrl_pad_writel(x, y)	WARN_ON(1)
 #endif
 #endif	/* __ASSEMBLY__ */
 #endif /* __ARCH_ARM_MACH_OMAP2_CONTROL_H */

arch/arm/mach-omap2/omap-headsmp.S

Diff comments View file @ e3db221

 /*
  * Secondary CPU startup routine source file.
  *
  * Copyright (C) 2009-2014 Texas Instruments, Inc.
  *
  * Author:
  *      Santosh Shilimkar <santosh.shilimkar@ti.com>
  *
  * Interface functions needed for the SMP. This file is based on arm
  * realview smp platform.
  * Copyright (c) 2003 ARM Limited.
  *
  * This program is free software,you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
 #include <linux/linkage.h>
 #include <linux/init.h>
 #include "omap44xx.h"
 /* Physical address needed since MMU not enabled yet on secondary core */
 #define AUX_CORE_BOOT0_PA			0x48281800
+#define API_HYP_ENTRY				0x102
 /*
  * OMAP5 specific entry point for secondary CPU to jump from ROM
  * code.  This routine also provides a holding flag into which
  * secondary core is held until we're ready for it to initialise.
  * The primary core will update this flag using a hardware
  * register AuxCoreBoot0.
  */
 ENTRY(omap5_secondary_startup)
 wait:	ldr	r2, =AUX_CORE_BOOT0_PA	@ read from AuxCoreBoot0
 	ldr	r0, [r2]
 	mov	r0, r0, lsr #5
 	mrc	p15, 0, r4, c0, c0, 5
 	and	r4, r4, #0x0f
 	cmp	r0, r4
 	bne	wait
 	b	secondary_startup
 ENDPROC(omap5_secondary_startup)
+/*
+ * Same as omap5_secondary_startup except we call into the ROM to
+ * enable HYP mode first.  This is called instead of
+ * omap5_secondary_startup if the primary CPU was put into HYP mode by
+ * the boot loader.
+ */
+ENTRY(omap5_secondary_hyp_startup)
+wait_2:	ldr	r2, =AUX_CORE_BOOT0_PA	@ read from AuxCoreBoot0
+	ldr	r0, [r2]
+	mov	r0, r0, lsr #5
+	mrc	p15, 0, r4, c0, c0, 5
+	and	r4, r4, #0x0f
+	cmp	r0, r4
+	bne	wait_2
+	ldr	r12, =API_HYP_ENTRY
+	adr	r0, hyp_boot
+	smc	#0
+hyp_boot:
+	b	secondary_startup
+ENDPROC(omap5_secondary_hyp_startup)
 /*
  * OMAP4 specific entry point for secondary CPU to jump from ROM
  * code.  This routine also provides a holding flag into which
  * secondary core is held until we're ready for it to initialise.
  * The primary core will update this flag using a hardware
  * register AuxCoreBoot0.
  */
 ENTRY(omap4_secondary_startup)
 hold:	ldr	r12,=0x103
 	dsb
 	smc	#0			@ read from AuxCoreBoot0
 	mov	r0, r0, lsr #9
 	mrc	p15, 0, r4, c0, c0, 5
 	and	r4, r4, #0x0f
 	cmp	r0, r4
 	bne	hold
 	/*
 	 * we've been released from the wait loop,secondary_stack
 	 * should now contain the SVC stack for this core
 	 */
 	b	secondary_startup
 ENDPROC(omap4_secondary_startup)
 ENTRY(omap4460_secondary_startup)
 hold_2:	ldr	r12,=0x103
 	dsb
 	smc	#0			@ read from AuxCoreBoot0
 	mov	r0, r0, lsr #9
 	mrc	p15, 0, r4, c0, c0, 5
 	and	r4, r4, #0x0f
 	cmp	r0, r4
 	bne	hold_2
 	/*
 	 * GIC distributor control register has changed between
 	 * CortexA9 r1pX and r2pX. The Control Register secure
 	 * banked version is now composed of 2 bits:
 	 * bit 0 == Secure Enable
 	 * bit 1 == Non-Secure Enable
 	 * The Non-Secure banked register has not changed
 	 * Because the ROM Code is based on the r1pX GIC, the CPU1
 	 * GIC restoration will cause a problem to CPU0 Non-Secure SW.
 	 * The workaround must be:
 	 * 1) Before doing the CPU1 wakeup, CPU0 must disable
 	 * the GIC distributor
 	 * 2) CPU1 must re-enable the GIC distributor on
 	 * it's wakeup path.
 	 */
 	ldr	r1, =OMAP44XX_GIC_DIST_BASE
 	ldr	r0, [r1]
 	orr	r0, #1
 	str	r0, [r1]
 	/*
 	 * we've been released from the wait loop,secondary_stack
 	 * should now contain the SVC stack for this core
 	 */
 	b	secondary_startup
 ENDPROC(omap4460_secondary_startup)

arch/arm/mach-omap2/omap-smp.c

Diff comments View file @ e3db221

 /*
  * OMAP4 SMP source file. It contains platform specific functions
  * needed for the linux smp kernel.
  *
  * Copyright (C) 2009 Texas Instruments, Inc.
  *
  * Author:
  *      Santosh Shilimkar <santosh.shilimkar@ti.com>
  *
  * Platform file needed for the OMAP4 SMP. This file is based on arm
  * realview smp platform.
  * * Copyright (c) 2002 ARM Limited.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
 #include <linux/init.h>
 #include <linux/device.h>
 #include <linux/smp.h>
 #include <linux/io.h>
 #include <linux/irqchip/arm-gic.h>
 #include <asm/smp_scu.h>
+#include <asm/virt.h>
 #include "omap-secure.h"
 #include "omap-wakeupgen.h"
 #include <asm/cputype.h>
 #include "soc.h"
 #include "iomap.h"
 #include "common.h"
 #include "clockdomain.h"
 #include "pm.h"
 #define CPU_MASK		0xff0ffff0
 #define CPU_CORTEX_A9		0x410FC090
 #define CPU_CORTEX_A15		0x410FC0F0
 #define OMAP5_CORE_COUNT	0x2
 /* SCU base address */
 static void __iomem *scu_base;
 static DEFINE_SPINLOCK(boot_lock);
 void __iomem *omap4_get_scu_base(void)
 {
 	return scu_base;
 }
 static void omap4_secondary_init(unsigned int cpu)
 {
 	/*
 	 * Configure ACTRL and enable NS SMP bit access on CPU1 on HS device.
 	 * OMAP44XX EMU/HS devices - CPU0 SMP bit access is enabled in PPA
 	 * init and for CPU1, a secure PPA API provided. CPU0 must be ON
 	 * while executing NS_SMP API on CPU1 and PPA version must be 1.4.0+.
 	 * OMAP443X GP devices- SMP bit isn't accessible.
 	 * OMAP446X GP devices - SMP bit access is enabled on both CPUs.
 	 */
 	if (cpu_is_omap443x() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
 		omap_secure_dispatcher(OMAP4_PPA_CPU_ACTRL_SMP_INDEX,
 							4, 0, 0, 0, 0, 0);
 	/*
 	 * Configure the CNTFRQ register for the secondary cpu's which
 	 * indicates the frequency of the cpu local timers.
 	 */
 	if (soc_is_omap54xx() || soc_is_dra7xx())
 		set_cntfreq();
 	/*
 	 * Synchronise with the boot thread.
 	 */
 	spin_lock(&boot_lock);
 	spin_unlock(&boot_lock);
 }
 static int omap4_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
 	static struct clockdomain *cpu1_clkdm;
 	static bool booted;
 	static struct powerdomain *cpu1_pwrdm;
 	void __iomem *base = omap_get_wakeupgen_base();
 	/*
 	 * Set synchronisation state between this boot processor
 	 * and the secondary one
 	 */
 	spin_lock(&boot_lock);
 	/*
 	 * Update the AuxCoreBoot0 with boot state for secondary core.
 	 * omap4_secondary_startup() routine will hold the secondary core till
 	 * the AuxCoreBoot1 register is updated with cpu state
 	 * A barrier is added to ensure that write buffer is drained
 	 */
 	if (omap_secure_apis_support())
 		omap_modify_auxcoreboot0(0x200, 0xfffffdff);
 	else
 		writel_relaxed(0x20, base + OMAP_AUX_CORE_BOOT_0);
 	if (!cpu1_clkdm && !cpu1_pwrdm) {
 		cpu1_clkdm = clkdm_lookup("mpu1_clkdm");
 		cpu1_pwrdm = pwrdm_lookup("cpu1_pwrdm");
 	}
 	/*
 	 * The SGI(Software Generated Interrupts) are not wakeup capable
 	 * from low power states. This is known limitation on OMAP4 and
 	 * needs to be worked around by using software forced clockdomain
 	 * wake-up. To wakeup CPU1, CPU0 forces the CPU1 clockdomain to
 	 * software force wakeup. The clockdomain is then put back to
 	 * hardware supervised mode.
 	 * More details can be found in OMAP4430 TRM - Version J
 	 * Section :
 	 *	4.3.4.2 Power States of CPU0 and CPU1
 	 */
 	if (booted && cpu1_pwrdm && cpu1_clkdm) {
 		/*
 		 * GIC distributor control register has changed between
 		 * CortexA9 r1pX and r2pX. The Control Register secure
 		 * banked version is now composed of 2 bits:
 		 * bit 0 == Secure Enable
 		 * bit 1 == Non-Secure Enable
 		 * The Non-Secure banked register has not changed
 		 * Because the ROM Code is based on the r1pX GIC, the CPU1
 		 * GIC restoration will cause a problem to CPU0 Non-Secure SW.
 		 * The workaround must be:
 		 * 1) Before doing the CPU1 wakeup, CPU0 must disable
 		 * the GIC distributor
 		 * 2) CPU1 must re-enable the GIC distributor on
 		 * it's wakeup path.
 		 */
 		if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD)) {
 			local_irq_disable();
 			gic_dist_disable();
 		}
 		/*
 		 * Ensure that CPU power state is set to ON to avoid CPU
 		 * powerdomain transition on wfi
 		 */
 		clkdm_wakeup(cpu1_clkdm);
 		omap_set_pwrdm_state(cpu1_pwrdm, PWRDM_POWER_ON);
 		clkdm_allow_idle(cpu1_clkdm);
 		if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD)) {
 			while (gic_dist_disabled()) {
 				udelay(1);
 				cpu_relax();
 			}
 			gic_timer_retrigger();
 			local_irq_enable();
 		}
 	} else {
 		dsb_sev();
 		booted = true;
 	}
 	arch_send_wakeup_ipi_mask(cpumask_of(cpu));
 	/*
 	 * Now the secondary core is starting up let it run its
 	 * calibrations, then wait for it to finish
 	 */
 	spin_unlock(&boot_lock);
 	return 0;
 }
 /*
  * Initialise the CPU possible map early - this describes the CPUs
  * which may be present or become present in the system.
  */
 static void __init omap4_smp_init_cpus(void)
 {
 	unsigned int i = 0, ncores = 1, cpu_id;
 	/* Use ARM cpuid check here, as SoC detection will not work so early */
 	cpu_id = read_cpuid_id() & CPU_MASK;
 	if (cpu_id == CPU_CORTEX_A9) {
 		/*
 		 * Currently we can't call ioremap here because
 		 * SoC detection won't work until after init_early.
 		 */
 		scu_base =  OMAP2_L4_IO_ADDRESS(scu_a9_get_base());
 		BUG_ON(!scu_base);
 		ncores = scu_get_core_count(scu_base);
 	} else if (cpu_id == CPU_CORTEX_A15) {
 		ncores = OMAP5_CORE_COUNT;
 	}
 	/* sanity check */
 	if (ncores > nr_cpu_ids) {
 		pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
 			ncores, nr_cpu_ids);
 		ncores = nr_cpu_ids;
 	}
 	for (i = 0; i < ncores; i++)
 		set_cpu_possible(i, true);
 }
 static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
 {
 	void *startup_addr = omap4_secondary_startup;
 	void __iomem *base = omap_get_wakeupgen_base();
 	/*
 	 * Initialise the SCU and wake up the secondary core using
 	 * wakeup_secondary().
 	 */
 	if (scu_base)
 		scu_enable(scu_base);
 	if (cpu_is_omap446x())
 		startup_addr = omap4460_secondary_startup;
 	/*
 	 * Write the address of secondary startup routine into the
 	 * AuxCoreBoot1 where ROM code will jump and start executing
 	 * on secondary core once out of WFE
 	 * A barrier is added to ensure that write buffer is drained
 	 */
 	if (omap_secure_apis_support())
 		omap_auxcoreboot_addr(virt_to_phys(startup_addr));
 	else
-		writel_relaxed(virt_to_phys(omap5_secondary_startup),
+		/*
-			       base + OMAP_AUX_CORE_BOOT_1);
+		 * If the boot CPU is in HYP mode then start secondary
+		 * CPU in HYP mode as well.
+		 */
+		if ((__boot_cpu_mode & MODE_MASK) == HYP_MODE)
+			writel_relaxed(virt_to_phys(omap5_secondary_hyp_startup),
+				       base + OMAP_AUX_CORE_BOOT_1);
+		else
+			writel_relaxed(virt_to_phys(omap5_secondary_startup),
+				       base + OMAP_AUX_CORE_BOOT_1);
 }
 struct smp_operations omap4_smp_ops __initdata = {
 	.smp_init_cpus		= omap4_smp_init_cpus,
 	.smp_prepare_cpus	= omap4_smp_prepare_cpus,
 	.smp_secondary_init	= omap4_secondary_init,
 	.smp_boot_secondary	= omap4_boot_secondary,
 #ifdef CONFIG_HOTPLUG_CPU
 	.cpu_die		= omap4_cpu_die,
 #endif
 };

arch/arm/mach-omap2/timer.c

Diff comments View file @ e3db221

 /*
  * linux/arch/arm/mach-omap2/timer.c
  *
  * OMAP2 GP timer support.
  *
  * Copyright (C) 2009 Nokia Corporation
  *
  * Update to use new clocksource/clockevent layers
  * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
  * Copyright (C) 2007 MontaVista Software, Inc.
  *
  * Original driver:
  * Copyright (C) 2005 Nokia Corporation
  * Author: Paul Mundt <paul.mundt@nokia.com>
  *         Juha Yrjölä <juha.yrjola@nokia.com>
  * OMAP Dual-mode timer framework support by Timo Teras
  *
  * Some parts based off of TI's 24xx code:
  *
  * Copyright (C) 2004-2009 Texas Instruments, Inc.
  *
  * Roughly modelled after the OMAP1 MPU timer code.
  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License. See the file "COPYING" in the main directory of this archive
  * for more details.
  */
 #include <linux/init.h>
 #include <linux/time.h>
 #include <linux/interrupt.h>
 #include <linux/err.h>
 #include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/irq.h>
 #include <linux/clocksource.h>
 #include <linux/clockchips.h>
 #include <linux/slab.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/platform_device.h>
 #include <linux/platform_data/dmtimer-omap.h>
 #include <linux/sched_clock.h>
 #include <asm/mach/time.h>
 #include <asm/smp_twd.h>
 #include "omap_hwmod.h"
 #include "omap_device.h"
 #include <plat/counter-32k.h>
 #include <plat/dmtimer.h>
 #include "omap-pm.h"
 #include "soc.h"
 #include "common.h"
+#include "control.h"
 #include "powerdomain.h"
 #include "omap-secure.h"
 #define REALTIME_COUNTER_BASE				0x48243200
 #define INCREMENTER_NUMERATOR_OFFSET			0x10
 #define INCREMENTER_DENUMERATOR_RELOAD_OFFSET		0x14
 #define NUMERATOR_DENUMERATOR_MASK			0xfffff000
 /* Clockevent code */
 static struct omap_dm_timer clkev;
 static struct clock_event_device clockevent_gpt;
 #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
 static unsigned long arch_timer_freq;
 void set_cntfreq(void)
 {
 	omap_smc1(OMAP5_DRA7_MON_SET_CNTFRQ_INDEX, arch_timer_freq);
 }
 #endif
 static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
 {
 	struct clock_event_device *evt = &clockevent_gpt;
 	__omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW);
 	evt->event_handler(evt);
 	return IRQ_HANDLED;
 }
 static struct irqaction omap2_gp_timer_irq = {
 	.name		= "gp_timer",
 	.flags		= IRQF_TIMER | IRQF_IRQPOLL,
 	.handler	= omap2_gp_timer_interrupt,
 };
 static int omap2_gp_timer_set_next_event(unsigned long cycles,
 					 struct clock_event_device *evt)
 {
 	__omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST,
 				   0xffffffff - cycles, OMAP_TIMER_POSTED);
 	return 0;
 }
 static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
 				    struct clock_event_device *evt)
 {
 	u32 period;
 	__omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate);
 	switch (mode) {
 	case CLOCK_EVT_MODE_PERIODIC:
 		period = clkev.rate / HZ;
 		period -= 1;
 		/* Looks like we need to first set the load value separately */
 		__omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG,
 				      0xffffffff - period, OMAP_TIMER_POSTED);
 		__omap_dm_timer_load_start(&clkev,
 					OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
 					0xffffffff - period, OMAP_TIMER_POSTED);
 		break;
 	case CLOCK_EVT_MODE_ONESHOT:
 		break;
 	case CLOCK_EVT_MODE_UNUSED:
 	case CLOCK_EVT_MODE_SHUTDOWN:
 	case CLOCK_EVT_MODE_RESUME:
 		break;
 	}
 }
 static struct clock_event_device clockevent_gpt = {
 	.features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 	.rating		= 300,
 	.set_next_event	= omap2_gp_timer_set_next_event,
 	.set_mode	= omap2_gp_timer_set_mode,
 };
 static struct property device_disabled = {
 	.name = "status",
 	.length = sizeof("disabled"),
 	.value = "disabled",
 };
 static const struct of_device_id omap_timer_match[] __initconst = {
 	{ .compatible = "ti,omap2420-timer", },
 	{ .compatible = "ti,omap3430-timer", },
 	{ .compatible = "ti,omap4430-timer", },
 	{ .compatible = "ti,omap5430-timer", },
 	{ .compatible = "ti,am335x-timer", },
 	{ .compatible = "ti,am335x-timer-1ms", },
 	{ }
 };
 /**
  * omap_get_timer_dt - get a timer using device-tree
  * @match	- device-tree match structure for matching a device type
  * @property	- optional timer property to match
  *
  * Helper function to get a timer during early boot using device-tree for use
  * as kernel system timer. Optionally, the property argument can be used to
  * select a timer with a specific property. Once a timer is found then mark
  * the timer node in device-tree as disabled, to prevent the kernel from
  * registering this timer as a platform device and so no one else can use it.
  */
 static struct device_node * __init omap_get_timer_dt(const struct of_device_id *match,
 						     const char *property)
 {
 	struct device_node *np;
 	for_each_matching_node(np, match) {
 		if (!of_device_is_available(np))
 			continue;
 		if (property && !of_get_property(np, property, NULL))
 			continue;
 		if (!property && (of_get_property(np, "ti,timer-alwon", NULL) ||
 				  of_get_property(np, "ti,timer-dsp", NULL) ||
 				  of_get_property(np, "ti,timer-pwm", NULL) ||
 				  of_get_property(np, "ti,timer-secure", NULL)))
 			continue;
 		of_add_property(np, &device_disabled);
 		return np;
 	}
 	return NULL;
 }
 /**
  * omap_dmtimer_init - initialisation function when device tree is used
  *
  * For secure OMAP3 devices, timers with device type "timer-secure" cannot
  * be used by the kernel as they are reserved. Therefore, to prevent the
  * kernel registering these devices remove them dynamically from the device
  * tree on boot.
  */
 static void __init omap_dmtimer_init(void)
 {
 	struct device_node *np;
 	if (!cpu_is_omap34xx())
 		return;
 	/* If we are a secure device, remove any secure timer nodes */
 	if ((omap_type() != OMAP2_DEVICE_TYPE_GP)) {
 		np = omap_get_timer_dt(omap_timer_match, "ti,timer-secure");
 		if (np)
 			of_node_put(np);
 	}
 }
 /**
  * omap_dm_timer_get_errata - get errata flags for a timer
  *
  * Get the timer errata flags that are specific to the OMAP device being used.
  */
 static u32 __init omap_dm_timer_get_errata(void)
 {
 	if (cpu_is_omap24xx())
 		return 0;
 	return OMAP_TIMER_ERRATA_I103_I767;
 }
 static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
 					 const char *fck_source,
 					 const char *property,
 					 const char **timer_name,
 					 int posted)
 {
 	char name[10]; /* 10 = sizeof("gptXX_Xck0") */
 	const char *oh_name = NULL;
 	struct device_node *np;
 	struct omap_hwmod *oh;
 	struct resource irq, mem;
 	struct clk *src;
 	int r = 0;
 	if (of_have_populated_dt()) {
 		np = omap_get_timer_dt(omap_timer_match, property);
 		if (!np)
 			return -ENODEV;
 		of_property_read_string_index(np, "ti,hwmods", 0, &oh_name);
 		if (!oh_name)
 			return -ENODEV;
 		timer->irq = irq_of_parse_and_map(np, 0);
 		if (!timer->irq)
 			return -ENXIO;
 		timer->io_base = of_iomap(np, 0);
 		of_node_put(np);
 	} else {
 		if (omap_dm_timer_reserve_systimer(timer->id))
 			return -ENODEV;
 		sprintf(name, "timer%d", timer->id);
 		oh_name = name;
 	}
 	oh = omap_hwmod_lookup(oh_name);
 	if (!oh)
 		return -ENODEV;
 	*timer_name = oh->name;
 	if (!of_have_populated_dt()) {
 		r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL,
 						   &irq);
 		if (r)
 			return -ENXIO;
 		timer->irq = irq.start;
 		r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL,
 						   &mem);
 		if (r)
 			return -ENXIO;
 		/* Static mapping, never released */
 		timer->io_base = ioremap(mem.start, mem.end - mem.start);
 	}
 	if (!timer->io_base)
 		return -ENXIO;
 	/* After the dmtimer is using hwmod these clocks won't be needed */
 	timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh));
 	if (IS_ERR(timer->fclk))
 		return PTR_ERR(timer->fclk);
 	src = clk_get(NULL, fck_source);
 	if (IS_ERR(src))
 		return PTR_ERR(src);
 	if (clk_get_parent(timer->fclk) != src) {
 		r = clk_set_parent(timer->fclk, src);
 		if (r < 0) {
 			pr_warn("%s: %s cannot set source\n", __func__,
 				oh->name);
 			clk_put(src);
 			return r;
 		}
 	}
 	clk_put(src);
 	omap_hwmod_setup_one(oh_name);
 	omap_hwmod_enable(oh);
 	__omap_dm_timer_init_regs(timer);
 	if (posted)
 		__omap_dm_timer_enable_posted(timer);
 	/* Check that the intended posted configuration matches the actual */
 	if (posted != timer->posted)
 		return -EINVAL;
 	timer->rate = clk_get_rate(timer->fclk);
 	timer->reserved = 1;
 	return r;
 }
 static void __init omap2_gp_clockevent_init(int gptimer_id,
 						const char *fck_source,
 						const char *property)
 {
 	int res;
 	clkev.id = gptimer_id;
 	clkev.errata = omap_dm_timer_get_errata();
 	/*
 	 * For clock-event timers we never read the timer counter and
 	 * so we are not impacted by errata i103 and i767. Therefore,
 	 * we can safely ignore this errata for clock-event timers.
 	 */
 	__omap_dm_timer_override_errata(&clkev, OMAP_TIMER_ERRATA_I103_I767);
 	res = omap_dm_timer_init_one(&clkev, fck_source, property,
 				     &clockevent_gpt.name, OMAP_TIMER_POSTED);
 	BUG_ON(res);
 	omap2_gp_timer_irq.dev_id = &clkev;
 	setup_irq(clkev.irq, &omap2_gp_timer_irq);
 	__omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
 	clockevent_gpt.cpumask = cpu_possible_mask;
 	clockevent_gpt.irq = omap_dm_timer_get_irq(&clkev);
 	clockevents_config_and_register(&clockevent_gpt, clkev.rate,
 					3, /* Timer internal resynch latency */
 					0xffffffff);
 	pr_info("OMAP clockevent source: %s at %lu Hz\n", clockevent_gpt.name,
 		clkev.rate);
 }
 /* Clocksource code */
 static struct omap_dm_timer clksrc;
 static bool use_gptimer_clksrc __initdata;
 /*
  * clocksource
  */
 static cycle_t clocksource_read_cycles(struct clocksource *cs)
 {
 	return (cycle_t)__omap_dm_timer_read_counter(&clksrc,
 						     OMAP_TIMER_NONPOSTED);
 }
 static struct clocksource clocksource_gpt = {
 	.rating		= 300,
 	.read		= clocksource_read_cycles,
 	.mask		= CLOCKSOURCE_MASK(32),
 	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
 };
 static u64 notrace dmtimer_read_sched_clock(void)
 {
 	if (clksrc.reserved)
 		return __omap_dm_timer_read_counter(&clksrc,
 						    OMAP_TIMER_NONPOSTED);
 	return 0;
 }
 static const struct of_device_id omap_counter_match[] __initconst = {
 	{ .compatible = "ti,omap-counter32k", },
 	{ }
 };
 /* Setup free-running counter for clocksource */
 static int __init __maybe_unused omap2_sync32k_clocksource_init(void)
 {
 	int ret;
 	struct device_node *np = NULL;
 	struct omap_hwmod *oh;
 	void __iomem *vbase;
 	const char *oh_name = "counter_32k";
 	/*
 	 * If device-tree is present, then search the DT blob
 	 * to see if the 32kHz counter is supported.
 	 */
 	if (of_have_populated_dt()) {
 		np = omap_get_timer_dt(omap_counter_match, NULL);
 		if (!np)
 			return -ENODEV;
 		of_property_read_string_index(np, "ti,hwmods", 0, &oh_name);
 		if (!oh_name)
 			return -ENODEV;
 	}
 	/*
 	 * First check hwmod data is available for sync32k counter
 	 */
 	oh = omap_hwmod_lookup(oh_name);
 	if (!oh || oh->slaves_cnt == 0)
 		return -ENODEV;
 	omap_hwmod_setup_one(oh_name);
 	if (np) {
 		vbase = of_iomap(np, 0);
 		of_node_put(np);
 	} else {
 		vbase = omap_hwmod_get_mpu_rt_va(oh);
 	}
 	if (!vbase) {
 		pr_warn("%s: failed to get counter_32k resource\n", __func__);
 		return -ENXIO;
 	}
 	ret = omap_hwmod_enable(oh);
 	if (ret) {
 		pr_warn("%s: failed to enable counter_32k module (%d)\n",
 							__func__, ret);
 		return ret;
 	}
 	ret = omap_init_clocksource_32k(vbase);
 	if (ret) {
 		pr_warn("%s: failed to initialize counter_32k as a clocksource (%d)\n",
 							__func__, ret);
 		omap_hwmod_idle(oh);
 	}
 	return ret;
 }
 static void __init omap2_gptimer_clocksource_init(int gptimer_id,
 						  const char *fck_source,
 						  const char *property)
 {
 	int res;
 	clksrc.id = gptimer_id;
 	clksrc.errata = omap_dm_timer_get_errata();
 	res = omap_dm_timer_init_one(&clksrc, fck_source, property,
 				     &clocksource_gpt.name,
 				     OMAP_TIMER_NONPOSTED);
 	BUG_ON(res);
 	__omap_dm_timer_load_start(&clksrc,
 				   OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0,
 				   OMAP_TIMER_NONPOSTED);
 	sched_clock_register(dmtimer_read_sched_clock, 32, clksrc.rate);
 	if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
 		pr_err("Could not register clocksource %s\n",
 			clocksource_gpt.name);
 	else
 		pr_info("OMAP clocksource: %s at %lu Hz\n",
 			clocksource_gpt.name, clksrc.rate);
 }
 #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
 /*
  * The realtime counter also called master counter, is a free-running
  * counter, which is related to real time. It produces the count used
  * by the CPU local timer peripherals in the MPU cluster. The timer counts
  * at a rate of 6.144 MHz. Because the device operates on different clocks
  * in different power modes, the master counter shifts operation between
  * clocks, adjusting the increment per clock in hardware accordingly to
  * maintain a constant count rate.
  */
 static void __init realtime_counter_init(void)
 {
 	void __iomem *base;
 	static struct clk *sys_clk;
 	unsigned long rate;
-	unsigned int reg, num, den;
+	unsigned int reg;
+	unsigned long long num, den;
 	base = ioremap(REALTIME_COUNTER_BASE, SZ_32);
 	if (!base) {
 		pr_err("%s: ioremap failed\n", __func__);
 		return;
 	}
 	sys_clk = clk_get(NULL, "sys_clkin");
 	if (IS_ERR(sys_clk)) {
 		pr_err("%s: failed to get system clock handle\n", __func__);
 		iounmap(base);
 		return;
 	}
 	rate = clk_get_rate(sys_clk);
+	if (soc_is_dra7xx()) {
+		/*
+		 * Errata i856 says the 32.768KHz crystal does not start at
+		 * power on, so the CPU falls back to an emulated 32KHz clock
+		 * based on sysclk / 610 instead. This causes the master counter
+		 * frequency to not be 6.144MHz but at sysclk / 610 * 375 / 2
+		 * (OR sysclk * 75 / 244)
+		 *
+		 * This affects at least the DRA7/AM572x 1.0, 1.1 revisions.
+		 * Of course any board built without a populated 32.768KHz
+		 * crystal would also need this fix even if the CPU is fixed
+		 * later.
+		 *
+		 * Either case can be detected by using the two speedselect bits
+		 * If they are not 0, then the 32.768KHz clock driving the
+		 * coarse counter that corrects the fine counter every time it
+		 * ticks is actually rate/610 rather than 32.768KHz and we
+		 * should compensate to avoid the 570ppm (at 20MHz, much worse
+		 * at other rates) too fast system time.
+		 */
+		reg = omap_ctrl_readl(DRA7_CTRL_CORE_BOOTSTRAP);
+		if (reg & DRA7_SPEEDSELECT_MASK) {
+			num = 75;
+			den = 244;
+			goto sysclk1_based;
+		}
+	}
 	/* Numerator/denumerator values refer TRM Realtime Counter section */
 	switch (rate) {
-	case 1200000:
+	case 12000000:
 		num = 64;
 		den = 125;
 		break;
-	case 1300000:
+	case 13000000:
 		num = 768;
 		den = 1625;
 		break;
 	case 19200000:
 		num = 8;
 		den = 25;
 		break;
 	case 20000000:
 		num = 192;
 		den = 625;
 		break;
-	case 2600000:
+	case 26000000:
 		num = 384;
 		den = 1625;
 		break;
-	case 2700000:
+	case 27000000:
 		num = 256;
 		den = 1125;
 		break;
 	case 38400000:
 	default:
 		/* Program it for 38.4 MHz */
 		num = 4;
 		den = 25;
 		break;
 	}
+sysclk1_based:
 	/* Program numerator and denumerator registers */
 	reg = readl_relaxed(base + INCREMENTER_NUMERATOR_OFFSET) &
 			NUMERATOR_DENUMERATOR_MASK;
 	reg |= num;
 	writel_relaxed(reg, base + INCREMENTER_NUMERATOR_OFFSET);
 	reg = readl_relaxed(base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET) &
 			NUMERATOR_DENUMERATOR_MASK;
 	reg |= den;
 	writel_relaxed(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
-	arch_timer_freq = (rate / den) * num;
+	arch_timer_freq = DIV_ROUND_UP_ULL(rate * num, den);
 	set_cntfreq();
 	iounmap(base);
 }
 #else
 static inline void __init realtime_counter_init(void)
 {}
 #endif
 #define OMAP_SYS_GP_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop,	\
 			       clksrc_nr, clksrc_src, clksrc_prop)	\
 void __init omap##name##_gptimer_timer_init(void)			\
 {									\
 	omap_clk_init();					\
 	omap_dmtimer_init();						\
 	omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop);	\
 	omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src,		\
 					clksrc_prop);			\
 }
 #define OMAP_SYS_32K_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop,	\
 				clksrc_nr, clksrc_src, clksrc_prop)	\
 void __init omap##name##_sync32k_timer_init(void)		\
 {									\
 	omap_clk_init();					\
 	omap_dmtimer_init();						\
 	omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop);	\
 	/* Enable the use of clocksource="gp_timer" kernel parameter */	\
 	if (use_gptimer_clksrc)						\
 		omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src,	\
 						clksrc_prop);		\
 	else								\
 		omap2_sync32k_clocksource_init();			\
 }
 #ifdef CONFIG_ARCH_OMAP2
 OMAP_SYS_32K_TIMER_INIT(2, 1, "timer_32k_ck", "ti,timer-alwon",
 			2, "timer_sys_ck", NULL);
 #endif /* CONFIG_ARCH_OMAP2 */
 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM43XX)
 OMAP_SYS_32K_TIMER_INIT(3, 1, "timer_32k_ck", "ti,timer-alwon",
 			2, "timer_sys_ck", NULL);
 OMAP_SYS_32K_TIMER_INIT(3_secure, 12, "secure_32k_fck", "ti,timer-secure",
 			2, "timer_sys_ck", NULL);
 #endif /* CONFIG_ARCH_OMAP3 */
 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX) || \
 	defined(CONFIG_SOC_AM43XX)
 OMAP_SYS_GP_TIMER_INIT(3, 2, "timer_sys_ck", NULL,
 		       1, "timer_sys_ck", "ti,timer-alwon");
 #endif
 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
 	defined(CONFIG_SOC_DRA7XX)
 static OMAP_SYS_32K_TIMER_INIT(4, 1, "timer_32k_ck", "ti,timer-alwon",
 			       2, "sys_clkin_ck", NULL);
 #endif
 #ifdef CONFIG_ARCH_OMAP4
 #ifdef CONFIG_HAVE_ARM_TWD
 static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, OMAP44XX_LOCAL_TWD_BASE, 29);
 void __init omap4_local_timer_init(void)
 {
 	omap4_sync32k_timer_init();
 	/* Local timers are not supprted on OMAP4430 ES1.0 */
 	if (omap_rev() != OMAP4430_REV_ES1_0) {
 		int err;
 		if (of_have_populated_dt()) {
 			clocksource_of_init();
 			return;
 		}
 		err = twd_local_timer_register(&twd_local_timer);
 		if (err)
 			pr_err("twd_local_timer_register failed %d\n", err);
 	}
 }
 #else
 void __init omap4_local_timer_init(void)
 {
 	omap4_sync32k_timer_init();
 }
 #endif /* CONFIG_HAVE_ARM_TWD */
 #endif /* CONFIG_ARCH_OMAP4 */
 #if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
 void __init omap5_realtime_timer_init(void)
 {
 	omap4_sync32k_timer_init();
 	realtime_counter_init();
 	clocksource_of_init();
 }
 #endif /* CONFIG_SOC_OMAP5 || CONFIG_SOC_DRA7XX */
 /**
  * omap_timer_init - build and register timer device with an
  * associated timer hwmod
  * @oh:	timer hwmod pointer to be used to build timer device
  * @user:	parameter that can be passed from calling hwmod API
  *
  * Called by omap_hwmod_for_each_by_class to register each of the timer
  * devices present in the system. The number of timer devices is known
  * by parsing through the hwmod database for a given class name. At the
  * end of function call memory is allocated for timer device and it is
  * registered to the framework ready to be proved by the driver.
  */
 static int __init omap_timer_init(struct omap_hwmod *oh, void *unused)
 {
 	int id;
 	int ret = 0;
 	char *name = "omap_timer";
 	struct dmtimer_platform_data *pdata;
 	struct platform_device *pdev;
 	struct omap_timer_capability_dev_attr *timer_dev_attr;
 	pr_debug("%s: %s\n", __func__, oh->name);
 	/* on secure device, do not register secure timer */
 	timer_dev_attr = oh->dev_attr;
 	if (omap_type() != OMAP2_DEVICE_TYPE_GP && timer_dev_attr)
 		if (timer_dev_attr->timer_capability == OMAP_TIMER_SECURE)
 			return ret;
 	pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
 	if (!pdata) {
 		pr_err("%s: No memory for [%s]\n", __func__, oh->name);
 		return -ENOMEM;
 	}
 	/*
 	 * Extract the IDs from name field in hwmod database
 	 * and use the same for constructing ids' for the
 	 * timer devices. In a way, we are avoiding usage of
 	 * static variable witin the function to do the same.
 	 * CAUTION: We have to be careful and make sure the
 	 * name in hwmod database does not change in which case
 	 * we might either make corresponding change here or
 	 * switch back static variable mechanism.
 	 */
 	sscanf(oh->name, "timer%2d", &id);
 	if (timer_dev_attr)
 		pdata->timer_capability = timer_dev_attr->timer_capability;
 	pdata->timer_errata = omap_dm_timer_get_errata();
 	pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count;
 	pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata));
 	if (IS_ERR(pdev)) {
 		pr_err("%s: Can't build omap_device for %s: %s.\n",
 			__func__, name, oh->name);
 		ret = -EINVAL;
 	}
 	kfree(pdata);
 	return ret;
 }
 /**
  * omap2_dm_timer_init - top level regular device initialization
  *
  * Uses dedicated hwmod api to parse through hwmod database for
  * given class name and then build and register the timer device.
  */
 static int __init omap2_dm_timer_init(void)
 {
 	int ret;
 	/* If dtb is there, the devices will be created dynamically */
 	if (of_have_populated_dt())
 		return -ENODEV;
 	ret = omap_hwmod_for_each_by_class("timer", omap_timer_init, NULL);
 	if (unlikely(ret)) {
 		pr_err("%s: device registration failed.\n", __func__);
 		return -EINVAL;
 	}
 	return 0;
 }
 omap_arch_initcall(omap2_dm_timer_init);
 /**
  * omap2_override_clocksource - clocksource override with user configuration
  *
  * Allows user to override default clocksource, using kernel parameter
  *   clocksource="gp_timer"	(For all OMAP2PLUS architectures)
  *
  * Note that, here we are using same standard kernel parameter "clocksource=",
  * and not introducing any OMAP specific interface.
  */
 static int __init omap2_override_clocksource(char *str)
 {
 	if (!str)
 		return 0;
 	/*
 	 * For OMAP architecture, we only have two options
 	 *    - sync_32k (default)
 	 *    - gp_timer (sys_clk based)
 	 */
 	if (!strcmp(str, "gp_timer"))
 		use_gptimer_clksrc = true;
 	return 0;
 }
 early_param("clocksource", omap2_override_clocksource);