Merge tag 'omap-for-v3.19/fixes-rc1' of git://git.kernel.org/pub/scm/linux/kerne…

…l/git/tmlind/linux-omap into fixes Merge "omap fixes against v3.19-rc1" from Tony Lindgren: Fixes for omaps mostly to deal with dra7 timer issues and hypervisor mode. The other fixes are minor fixes for various boards. The summary of the fixes is: - Fix real-time counter rate typos for some frequencies - Fix counter frequency drift for am572x - Fix booting of secondary CPU in HYP mode - Fix n900 board name for legacy user space - Fix cpufreq in omap2plus_defconfig after Kconfig change - Fix dra7 qspi partitions And also, let's re-enable smc91x on some n900 boards that we have sitting in a few test boot systems after the boot loader dependencies got fixed. * tag 'omap-for-v3.19/fixes-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: dts: Revert disabling of smc91x for n900 ARM: dts: dra7-evm: fix qspi device tree partition size ARM: omap2plus_defconfig: use CONFIG_CPUFREQ_DT ARM: OMAP2+: Fix n900 board name for legacy user space ARM: omap5/dra7xx: Enable booting secondary CPU in HYP mode ARM: dra7xx: Fix counter frequency drift for AM572x errata i856 ARM: omap5/dra7xx: Fix frequency typos Signed-off-by: Olof Johansson <olof@lixom.net>

Merge tag 'omap-for-v3.19/fixes-rc1' of git://git.kernel.org/pub/scm/linux/kerne…
…l/git/tmlind/linux-omap into fixes Merge "omap fixes against v3.19-rc1" from Tony Lindgren: Fixes for omaps mostly to deal with dra7 timer issues and hypervisor mode. The other fixes are minor fixes for various boards. The summary of the fixes is: - Fix real-time counter rate typos for some frequencies - Fix counter frequency drift for am572x - Fix booting of secondary CPU in HYP mode - Fix n900 board name for legacy user space - Fix cpufreq in omap2plus_defconfig after Kconfig change - Fix dra7 qspi partitions And also, let's re-enable smc91x on some n900 boards that we have sitting in a few test boot systems after the boot loader dependencies got fixed. * tag 'omap-for-v3.19/fixes-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: dts: Revert disabling of smc91x for n900 ARM: dts: dra7-evm: fix qspi device tree partition size ARM: omap2plus_defconfig: use CONFIG_CPUFREQ_DT ARM: OMAP2+: Fix n900 board name for legacy user space ARM: omap5/dra7xx: Enable booting secondary CPU in HYP mode ARM: dra7xx: Fix counter frequency drift for AM572x errata i856 ARM: omap5/dra7xx: Fix frequency typos Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson
2 parents 3be8142951 7ac72746aa
Showing 9 changed files Side-by-side Diff
arch/arm/boot/dts/dra7-evm.dts
arch/arm/boot/dts/omap3-n900.dts
arch/arm/configs/omap2plus_defconfig
arch/arm/mach-omap2/board-generic.c
arch/arm/mach-omap2/common.h
arch/arm/mach-omap2/control.h
arch/arm/mach-omap2/omap-headsmp.S
arch/arm/mach-omap2/omap-smp.c
arch/arm/mach-omap2/timer.c
@@ -499,23 +499,23 @@
 		};
 		partition@5 {
 			label = "QSPI.u-boot-spl-os";
-			reg = <0x00140000 0x00010000>;
+			reg = <0x00140000 0x00080000>;
 		};
 		partition@6 {
 			label = "QSPI.u-boot-env";
-			reg = <0x00150000 0x00010000>;
+			reg = <0x001c0000 0x00010000>;
 		};
 		partition@7 {
 			label = "QSPI.u-boot-env.backup1";
-			reg = <0x00160000 0x0010000>;
+			reg = <0x001d0000 0x0010000>;
 		};
 		partition@8 {
 			label = "QSPI.kernel";
-			reg = <0x00170000 0x0800000>;
+			reg = <0x001e0000 0x0800000>;
 		};
 		partition@9 {
 			label = "QSPI.file-system";
-			reg = <0x00970000 0x01690000>;
+			reg = <0x009e0000 0x01620000>;
 		};
 	};
 };
@@ -700,11 +700,9 @@
 		};
 	};
  
+	/* Ethernet is on some early development boards and qemu */
 	ethernet@gpmc {
 		compatible = "smsc,lan91c94";
-
-		status = "disabled";
-
 		interrupt-parent = <&gpio2>;
 		interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;	/* gpio54 */
 		reg = <1 0x300 0xf>;		/* 16 byte IO range at offset 0x300 */
@@ -68,7 +68,7 @@
 CONFIG_CPU_FREQ_GOV_POWERSAVE=y
 CONFIG_CPU_FREQ_GOV_USERSPACE=y
 CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_GENERIC_CPUFREQ_CPU0=y
+CONFIG_CPUFREQ_DT=y
 # CONFIG_ARM_OMAP2PLUS_CPUFREQ is not set
 CONFIG_CPU_IDLE=y
 CONFIG_BINFMT_MISC=y
@@ -77,6 +77,24 @@
 #endif
  
 #ifdef CONFIG_ARCH_OMAP3
+/* Some boards need board name for legacy userspace in /proc/cpuinfo */
+static const char *const n900_boards_compat[] __initconst = {
+	"nokia,omap3-n900",
+	NULL,
+};
+
+DT_MACHINE_START(OMAP3_N900_DT, "Nokia RX-51 board")
+	.reserve	= omap_reserve,
+	.map_io		= omap3_map_io,
+	.init_early	= omap3430_init_early,
+	.init_machine	= omap_generic_init,
+	.init_late	= omap3_init_late,
+	.init_time	= omap3_sync32k_timer_init,
+	.dt_compat	= n900_boards_compat,
+	.restart	= omap3xxx_restart,
+MACHINE_END
+
+/* Generic omap3 boards, most boards can use these */
 static const char *const omap3_boards_compat[] __initconst = {
 	"ti,omap3430",
 	"ti,omap3",
@@ -249,6 +249,7 @@
 extern struct smp_operations omap4_smp_ops;
  
 extern void omap5_secondary_startup(void);
+extern void omap5_secondary_hyp_startup(void);
 #endif
  
 #if defined(CONFIG_SMP) && defined(CONFIG_PM)
@@ -286,6 +286,10 @@
 #define OMAP5XXX_CONTROL_STATUS                0x134
 #define OMAP5_DEVICETYPE_MASK          (0x7 << 6)
  
+/* DRA7XX CONTROL CORE BOOTSTRAP */
+#define DRA7_CTRL_CORE_BOOTSTRAP	0x6c4
+#define DRA7_SPEEDSELECT_MASK		(0x3 << 8)
+
 /*
  * REVISIT: This list of registers is not comprehensive - there are more
  * that should be added.
@@ -22,6 +22,7 @@
  
 /* Physical address needed since MMU not enabled yet on secondary core */
 #define AUX_CORE_BOOT0_PA			0x48281800
+#define API_HYP_ENTRY				0x102
  
 /*
  * OMAP5 specific entry point for secondary CPU to jump from ROM
@@ -40,6 +41,26 @@
 	bne	wait
 	b	secondary_startup
 ENDPROC(omap5_secondary_startup)
+/*
+ * Same as omap5_secondary_startup except we call into the ROM to
+ * enable HYP mode first.  This is called instead of
+ * omap5_secondary_startup if the primary CPU was put into HYP mode by
+ * the boot loader.
+ */
+ENTRY(omap5_secondary_hyp_startup)
+wait_2:	ldr	r2, =AUX_CORE_BOOT0_PA	@ read from AuxCoreBoot0
+	ldr	r0, [r2]
+	mov	r0, r0, lsr #5
+	mrc	p15, 0, r4, c0, c0, 5
+	and	r4, r4, #0x0f
+	cmp	r0, r4
+	bne	wait_2
+	ldr	r12, =API_HYP_ENTRY
+	adr	r0, hyp_boot
+	smc	#0
+hyp_boot:
+	b	secondary_startup
+ENDPROC(omap5_secondary_hyp_startup)
 /*
  * OMAP4 specific entry point for secondary CPU to jump from ROM
  * code.  This routine also provides a holding flag into which
@@ -22,6 +22,7 @@
 #include <linux/irqchip/arm-gic.h>
  
 #include <asm/smp_scu.h>
+#include <asm/virt.h>
  
 #include "omap-secure.h"
 #include "omap-wakeupgen.h"
@@ -227,8 +228,16 @@
 	if (omap_secure_apis_support())
 		omap_auxcoreboot_addr(virt_to_phys(startup_addr));
 	else
-		writel_relaxed(virt_to_phys(omap5_secondary_startup),
-			       base + OMAP_AUX_CORE_BOOT_1);
+		/*
+		 * If the boot CPU is in HYP mode then start secondary
+		 * CPU in HYP mode as well.
+		 */
+		if ((__boot_cpu_mode & MODE_MASK) == HYP_MODE)
+			writel_relaxed(virt_to_phys(omap5_secondary_hyp_startup),
+				       base + OMAP_AUX_CORE_BOOT_1);
+		else
+			writel_relaxed(virt_to_phys(omap5_secondary_startup),
+				       base + OMAP_AUX_CORE_BOOT_1);
  
 }
  
@@ -54,6 +54,7 @@
  
 #include "soc.h"
 #include "common.h"
+#include "control.h"
 #include "powerdomain.h"
 #include "omap-secure.h"
  
@@ -496,7 +497,8 @@
 	void __iomem *base;
 	static struct clk *sys_clk;
 	unsigned long rate;
-	unsigned int reg, num, den;
+	unsigned int reg;
+	unsigned long long num, den;
  
 	base = ioremap(REALTIME_COUNTER_BASE, SZ_32);
 	if (!base) {
  
  
@@ -511,13 +513,42 @@
 	}
  
 	rate = clk_get_rate(sys_clk);
+
+	if (soc_is_dra7xx()) {
+		/*
+		 * Errata i856 says the 32.768KHz crystal does not start at
+		 * power on, so the CPU falls back to an emulated 32KHz clock
+		 * based on sysclk / 610 instead. This causes the master counter
+		 * frequency to not be 6.144MHz but at sysclk / 610 * 375 / 2
+		 * (OR sysclk * 75 / 244)
+		 *
+		 * This affects at least the DRA7/AM572x 1.0, 1.1 revisions.
+		 * Of course any board built without a populated 32.768KHz
+		 * crystal would also need this fix even if the CPU is fixed
+		 * later.
+		 *
+		 * Either case can be detected by using the two speedselect bits
+		 * If they are not 0, then the 32.768KHz clock driving the
+		 * coarse counter that corrects the fine counter every time it
+		 * ticks is actually rate/610 rather than 32.768KHz and we
+		 * should compensate to avoid the 570ppm (at 20MHz, much worse
+		 * at other rates) too fast system time.
+		 */
+		reg = omap_ctrl_readl(DRA7_CTRL_CORE_BOOTSTRAP);
+		if (reg & DRA7_SPEEDSELECT_MASK) {
+			num = 75;
+			den = 244;
+			goto sysclk1_based;
+		}
+	}
+
 	/* Numerator/denumerator values refer TRM Realtime Counter section */
 	switch (rate) {
-	case 1200000:
+	case 12000000:
 		num = 64;
 		den = 125;
 		break;
-	case 1300000:
+	case 13000000:
 		num = 768;
 		den = 1625;
 		break;
  
@@ -529,11 +560,11 @@
 		num = 192;
 		den = 625;
 		break;
-	case 2600000:
+	case 26000000:
 		num = 384;
 		den = 1625;
 		break;
-	case 2700000:
+	case 27000000:
 		num = 256;
 		den = 1125;
 		break;
@@ -545,6 +576,7 @@
 		break;
 	}
  
+sysclk1_based:
 	/* Program numerator and denumerator registers */
 	reg = readl_relaxed(base + INCREMENTER_NUMERATOR_OFFSET) &
 			NUMERATOR_DENUMERATOR_MASK;
@@ -556,7 +588,7 @@
 	reg |= den;
 	writel_relaxed(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
  
-	arch_timer_freq = (rate / den) * num;
+	arch_timer_freq = DIV_ROUND_UP_ULL(rate * num, den);
 	set_cntfreq();
  
 	iounmap(base);
...	...	@@ -499,23 +499,23 @@
499	499	};
500	500	partition@5 {
501	501	label = "QSPI.u-boot-spl-os";
502		- reg = <0x00140000 0x00010000>;
	502	+ reg = <0x00140000 0x00080000>;
503	503	};
504	504	partition@6 {
505	505	label = "QSPI.u-boot-env";
506		- reg = <0x00150000 0x00010000>;
	506	+ reg = <0x001c0000 0x00010000>;
507	507	};
508	508	partition@7 {
509	509	label = "QSPI.u-boot-env.backup1";
510		- reg = <0x00160000 0x0010000>;
	510	+ reg = <0x001d0000 0x0010000>;
511	511	};
512	512	partition@8 {
513	513	label = "QSPI.kernel";
514		- reg = <0x00170000 0x0800000>;
	514	+ reg = <0x001e0000 0x0800000>;
515	515	};
516	516	partition@9 {
517	517	label = "QSPI.file-system";
518		- reg = <0x00970000 0x01690000>;
	518	+ reg = <0x009e0000 0x01620000>;
519	519	};
520	520	};
521	521	};
...	...	@@ -700,11 +700,9 @@
700	700	};
701	701	};
702	702
	703	+ /* Ethernet is on some early development boards and qemu */
703	704	ethernet@gpmc {
704	705	compatible = "smsc,lan91c94";
705		-
706		- status = "disabled";
707		-
708	706	interrupt-parent = <&gpio2>;
709	707	interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; /* gpio54 */
710	708	reg = <1 0x300 0xf>; /* 16 byte IO range at offset 0x300 */
...	...	@@ -68,7 +68,7 @@
68	68	CONFIG_CPU_FREQ_GOV_POWERSAVE=y
69	69	CONFIG_CPU_FREQ_GOV_USERSPACE=y
70	70	CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
71		-CONFIG_GENERIC_CPUFREQ_CPU0=y
	71	+CONFIG_CPUFREQ_DT=y
72	72	# CONFIG_ARM_OMAP2PLUS_CPUFREQ is not set
73	73	CONFIG_CPU_IDLE=y
74	74	CONFIG_BINFMT_MISC=y
...	...	@@ -77,6 +77,24 @@
77	77	#endif
78	78
79	79	#ifdef CONFIG_ARCH_OMAP3
	80	+/* Some boards need board name for legacy userspace in /proc/cpuinfo */
	81	+static const char *const n900_boards_compat[] __initconst = {
	82	+ "nokia,omap3-n900",
	83	+ NULL,
	84	+};
	85	+
	86	+DT_MACHINE_START(OMAP3_N900_DT, "Nokia RX-51 board")
	87	+ .reserve = omap_reserve,
	88	+ .map_io = omap3_map_io,
	89	+ .init_early = omap3430_init_early,
	90	+ .init_machine = omap_generic_init,
	91	+ .init_late = omap3_init_late,
	92	+ .init_time = omap3_sync32k_timer_init,
	93	+ .dt_compat = n900_boards_compat,
	94	+ .restart = omap3xxx_restart,
	95	+MACHINE_END
	96	+
	97	+/* Generic omap3 boards, most boards can use these */
80	98	static const char *const omap3_boards_compat[] __initconst = {
81	99	"ti,omap3430",
82	100	"ti,omap3",
...	...	@@ -249,6 +249,7 @@
249	249	extern struct smp_operations omap4_smp_ops;
250	250
251	251	extern void omap5_secondary_startup(void);
	252	+extern void omap5_secondary_hyp_startup(void);
252	253	#endif
253	254
254	255	#if defined(CONFIG_SMP) && defined(CONFIG_PM)
...	...	@@ -286,6 +286,10 @@
286	286	#define OMAP5XXX_CONTROL_STATUS 0x134
287	287	#define OMAP5_DEVICETYPE_MASK (0x7 << 6)
288	288
	289	+/* DRA7XX CONTROL CORE BOOTSTRAP */
	290	+#define DRA7_CTRL_CORE_BOOTSTRAP 0x6c4
	291	+#define DRA7_SPEEDSELECT_MASK (0x3 << 8)
	292	+
289	293	/*
290	294	* REVISIT: This list of registers is not comprehensive - there are more
291	295	* that should be added.
...	...	@@ -22,6 +22,7 @@
22	22
23	23	/* Physical address needed since MMU not enabled yet on secondary core */
24	24	#define AUX_CORE_BOOT0_PA 0x48281800
	25	+#define API_HYP_ENTRY 0x102
25	26
26	27	/*
27	28	* OMAP5 specific entry point for secondary CPU to jump from ROM
...	...	@@ -40,6 +41,26 @@
40	41	bne wait
41	42	b secondary_startup
42	43	ENDPROC(omap5_secondary_startup)
	44	+/*
	45	+ * Same as omap5_secondary_startup except we call into the ROM to
	46	+ * enable HYP mode first. This is called instead of
	47	+ * omap5_secondary_startup if the primary CPU was put into HYP mode by
	48	+ * the boot loader.
	49	+ */
	50	+ENTRY(omap5_secondary_hyp_startup)
	51	+wait_2: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0
	52	+ ldr r0, [r2]
	53	+ mov r0, r0, lsr #5
	54	+ mrc p15, 0, r4, c0, c0, 5
	55	+ and r4, r4, #0x0f
	56	+ cmp r0, r4
	57	+ bne wait_2
	58	+ ldr r12, =API_HYP_ENTRY
	59	+ adr r0, hyp_boot
	60	+ smc #0
	61	+hyp_boot:
	62	+ b secondary_startup
	63	+ENDPROC(omap5_secondary_hyp_startup)
43	64	/*
44	65	* OMAP4 specific entry point for secondary CPU to jump from ROM
45	66	* code. This routine also provides a holding flag into which
...	...	@@ -22,6 +22,7 @@
22	22	#include <linux/irqchip/arm-gic.h>
23	23
24	24	#include <asm/smp_scu.h>
	25	+#include <asm/virt.h>
25	26
26	27	#include "omap-secure.h"
27	28	#include "omap-wakeupgen.h"
...	...	@@ -227,8 +228,16 @@
227	228	if (omap_secure_apis_support())
228	229	omap_auxcoreboot_addr(virt_to_phys(startup_addr));
229	230	else
230		- writel_relaxed(virt_to_phys(omap5_secondary_startup),
231		- base + OMAP_AUX_CORE_BOOT_1);
	231	+ /*
	232	+ * If the boot CPU is in HYP mode then start secondary
	233	+ * CPU in HYP mode as well.
	234	+ */
	235	+ if ((__boot_cpu_mode & MODE_MASK) == HYP_MODE)
	236	+ writel_relaxed(virt_to_phys(omap5_secondary_hyp_startup),
	237	+ base + OMAP_AUX_CORE_BOOT_1);
	238	+ else
	239	+ writel_relaxed(virt_to_phys(omap5_secondary_startup),
	240	+ base + OMAP_AUX_CORE_BOOT_1);
232	241
233	242	}
234	243
...	...	@@ -54,6 +54,7 @@
54	54
55	55	#include "soc.h"
56	56	#include "common.h"
	57	+#include "control.h"
57	58	#include "powerdomain.h"
58	59	#include "omap-secure.h"
59	60
...	...	@@ -496,7 +497,8 @@
496	497	void __iomem *base;
497	498	static struct clk *sys_clk;
498	499	unsigned long rate;
499		- unsigned int reg, num, den;
	500	+ unsigned int reg;
	501	+ unsigned long long num, den;
500	502
501	503	base = ioremap(REALTIME_COUNTER_BASE, SZ_32);
502	504	if (!base) {
503	505
504	506
...	...	@@ -511,13 +513,42 @@
511	513	}
512	514
513	515	rate = clk_get_rate(sys_clk);
	516	+
	517	+ if (soc_is_dra7xx()) {
	518	+ /*
	519	+ * Errata i856 says the 32.768KHz crystal does not start at
	520	+ * power on, so the CPU falls back to an emulated 32KHz clock
	521	+ * based on sysclk / 610 instead. This causes the master counter
	522	+ * frequency to not be 6.144MHz but at sysclk / 610 * 375 / 2
	523	+ * (OR sysclk * 75 / 244)
	524	+ *
	525	+ * This affects at least the DRA7/AM572x 1.0, 1.1 revisions.
	526	+ * Of course any board built without a populated 32.768KHz
	527	+ * crystal would also need this fix even if the CPU is fixed
	528	+ * later.
	529	+ *
	530	+ * Either case can be detected by using the two speedselect bits
	531	+ * If they are not 0, then the 32.768KHz clock driving the
	532	+ * coarse counter that corrects the fine counter every time it
	533	+ * ticks is actually rate/610 rather than 32.768KHz and we
	534	+ * should compensate to avoid the 570ppm (at 20MHz, much worse
	535	+ * at other rates) too fast system time.
	536	+ */
	537	+ reg = omap_ctrl_readl(DRA7_CTRL_CORE_BOOTSTRAP);
	538	+ if (reg & DRA7_SPEEDSELECT_MASK) {
	539	+ num = 75;
	540	+ den = 244;
	541	+ goto sysclk1_based;
	542	+ }
	543	+ }
	544	+
514	545	/* Numerator/denumerator values refer TRM Realtime Counter section */
515	546	switch (rate) {
516		- case 1200000:
	547	+ case 12000000:
517	548	num = 64;
518	549	den = 125;
519	550	break;
520		- case 1300000:
	551	+ case 13000000:
521	552	num = 768;
522	553	den = 1625;
523	554	break;
524	555
...	...	@@ -529,11 +560,11 @@
529	560	num = 192;
530	561	den = 625;
531	562	break;
532		- case 2600000:
	563	+ case 26000000:
533	564	num = 384;
534	565	den = 1625;
535	566	break;
536		- case 2700000:
	567	+ case 27000000:
537	568	num = 256;
538	569	den = 1125;
539	570	break;
...	...	@@ -545,6 +576,7 @@
545	576	break;
546	577	}
547	578
	579	+sysclk1_based:
548	580	/* Program numerator and denumerator registers */
549	581	reg = readl_relaxed(base + INCREMENTER_NUMERATOR_OFFSET) &
550	582	NUMERATOR_DENUMERATOR_MASK;
...	...	@@ -556,7 +588,7 @@
556	588	reg \|= den;
557	589	writel_relaxed(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
558	590
559		- arch_timer_freq = (rate / den) * num;
	591	+ arch_timer_freq = DIV_ROUND_UP_ULL(rate * num, den);
560	592	set_cntfreq();
561	593
562	594	iounmap(base);