Merge branch 'fixes' of git://ftp.arm.linux.org.uk/~rmk/linux-arm

Pull ARM fixes from Russell King: "Another round of relatively small ARM fixes. Thomas spotted that the strex backoff delay bit was a disable bit, so it needed to be clear for this to work. Vladimir spotted that using a restart block for the cache flush operation would return -EINTR, which userspace was not expecting. Dmitry spotted that the auxiliary control register accesses for Xscale were not correct" * 'fixes' of git://ftp.arm.linux.org.uk/~rmk/linux-arm: ARM: 8226/1: cacheflush: get rid of restarting block ARM: 8222/1: mvebu: enable strex backoff delay ARM: 8216/1: xscale: correct auxiliary register in suspend/resume

Merge branch 'fixes' of git://ftp.arm.linux.org.uk/~rmk/linux-arm
Pull ARM fixes from Russell King: "Another round of relatively small ARM fixes. Thomas spotted that the strex backoff delay bit was a disable bit, so it needed to be clear for this to work. Vladimir spotted that using a restart block for the cache flush operation would return -EINTR, which userspace was not expecting. Dmitry spotted that the auxiliary control register accesses for Xscale were not correct" * 'fixes' of git://ftp.arm.linux.org.uk/~rmk/linux-arm: ARM: 8226/1: cacheflush: get rid of restarting block ARM: 8222/1: mvebu: enable strex backoff delay ARM: 8216/1: xscale: correct auxiliary register in suspend/resume
Linus Torvalds
2 parents 98e8d2e094 3f4aa45cee
Showing 4 changed files Side-by-side Diff
arch/arm/include/asm/thread_info.h
arch/arm/kernel/traps.c
arch/arm/mm/proc-v7.S
arch/arm/mm/proc-xscale.S
@@ -44,16 +44,6 @@
 	__u32	extra[2];		/* Xscale 'acc' register, etc */
 };
  
-struct arm_restart_block {
-	union {
-		/* For user cache flushing */
-		struct {
-			unsigned long start;
-			unsigned long end;
-		} cache;
-	};
-};
-
 /*
  * low level task data that entry.S needs immediate access to.
  * __switch_to() assumes cpu_context follows immediately after cpu_domain.
@@ -79,7 +69,6 @@
 	unsigned long		thumbee_state;	/* ThumbEE Handler Base register */
 #endif
 	struct restart_block	restart_block;
-	struct arm_restart_block	arm_restart_block;
 };
  
 #define INIT_THREAD_INFO(tsk)						\
@@ -533,8 +533,6 @@
 	return regs->ARM_r0;
 }
  
-static long do_cache_op_restart(struct restart_block *);
-
 static inline int
 __do_cache_op(unsigned long start, unsigned long end)
 {
  
@@ -543,25 +541,9 @@
 	do {
 		unsigned long chunk = min(PAGE_SIZE, end - start);
  
-		if (signal_pending(current)) {
-			struct thread_info *ti = current_thread_info();
+		if (fatal_signal_pending(current))
+			return 0;
  
-			ti->restart_block = (struct restart_block) {
-				.fn	= do_cache_op_restart,
-			};
-
-			ti->arm_restart_block = (struct arm_restart_block) {
-				{
-					.cache = {
-						.start	= start,
-						.end	= end,
-					},
-				},
-			};
-
-			return -ERESTART_RESTARTBLOCK;
-		}
-
 		ret = flush_cache_user_range(start, start + chunk);
 		if (ret)
 			return ret;
@@ -571,15 +553,6 @@
 	} while (start < end);
  
 	return 0;
-}
-
-static long do_cache_op_restart(struct restart_block *unused)
-{
-	struct arm_restart_block *restart_block;
-
-	restart_block = &current_thread_info()->arm_restart_block;
-	return __do_cache_op(restart_block->cache.start,
-			     restart_block->cache.end);
 }
  
 static inline int
@@ -270,7 +270,6 @@
 /* Auxiliary Debug Modes Control 1 Register */
 #define PJ4B_STATIC_BP (1 << 2) /* Enable Static BP */
 #define PJ4B_INTER_PARITY (1 << 8) /* Disable Internal Parity Handling */
-#define PJ4B_BCK_OFF_STREX (1 << 5) /* Enable the back off of STREX instr */
 #define PJ4B_CLEAN_LINE (1 << 16) /* Disable data transfer for clean line */
  
 /* Auxiliary Debug Modes Control 2 Register */
@@ -293,7 +292,6 @@
 	/* Auxiliary Debug Modes Control 1 Register */
 	mrc	p15, 1,	r0, c15, c1, 1
 	orr     r0, r0, #PJ4B_CLEAN_LINE
-	orr     r0, r0, #PJ4B_BCK_OFF_STREX
 	orr     r0, r0, #PJ4B_INTER_PARITY
 	bic	r0, r0, #PJ4B_STATIC_BP
 	mcr	p15, 1,	r0, c15, c1, 1
@@ -535,7 +535,7 @@
 	mrc	p15, 0, r5, c15, c1, 0	@ CP access reg
 	mrc	p15, 0, r6, c13, c0, 0	@ PID
 	mrc	p15, 0, r7, c3, c0, 0	@ domain ID
-	mrc	p15, 0, r8, c1, c1, 0	@ auxiliary control reg
+	mrc	p15, 0, r8, c1, c0, 1	@ auxiliary control reg
 	mrc	p15, 0, r9, c1, c0, 0	@ control reg
 	bic	r4, r4, #2		@ clear frequency change bit
 	stmia	r0, {r4 - r9}		@ store cp regs
@@ -552,7 +552,7 @@
 	mcr	p15, 0, r6, c13, c0, 0	@ PID
 	mcr	p15, 0, r7, c3, c0, 0	@ domain ID
 	mcr	p15, 0, r1, c2, c0, 0	@ translation table base addr
-	mcr	p15, 0, r8, c1, c1, 0	@ auxiliary control reg
+	mcr	p15, 0, r8, c1, c0, 1	@ auxiliary control reg
 	mov	r0, r9			@ control register
 	b	cpu_resume_mmu
 ENDPROC(cpu_xscale_do_resume)
...	...	@@ -44,16 +44,6 @@
44	44	__u32 extra[2]; /* Xscale 'acc' register, etc */
45	45	};
46	46
47		-struct arm_restart_block {
48		- union {
49		- /* For user cache flushing */
50		- struct {
51		- unsigned long start;
52		- unsigned long end;
53		- } cache;
54		- };
55		-};
56		-
57	47	/*
58	48	* low level task data that entry.S needs immediate access to.
59	49	* __switch_to() assumes cpu_context follows immediately after cpu_domain.
...	...	@@ -79,7 +69,6 @@
79	69	unsigned long thumbee_state; /* ThumbEE Handler Base register */
80	70	#endif
81	71	struct restart_block restart_block;
82		- struct arm_restart_block arm_restart_block;
83	72	};
84	73
85	74	#define INIT_THREAD_INFO(tsk) \
...	...	@@ -533,8 +533,6 @@
533	533	return regs->ARM_r0;
534	534	}
535	535
536		-static long do_cache_op_restart(struct restart_block *);
537		-
538	536	static inline int
539	537	__do_cache_op(unsigned long start, unsigned long end)
540	538	{
541	539
...	...	@@ -543,25 +541,9 @@
543	541	do {
544	542	unsigned long chunk = min(PAGE_SIZE, end - start);
545	543
546		- if (signal_pending(current)) {
547		- struct thread_info *ti = current_thread_info();
	544	+ if (fatal_signal_pending(current))
	545	+ return 0;
548	546
549		- ti->restart_block = (struct restart_block) {
550		- .fn = do_cache_op_restart,
551		- };
552		-
553		- ti->arm_restart_block = (struct arm_restart_block) {
554		- {
555		- .cache = {
556		- .start = start,
557		- .end = end,
558		- },
559		- },
560		- };
561		-
562		- return -ERESTART_RESTARTBLOCK;
563		- }
564		-
565	547	ret = flush_cache_user_range(start, start + chunk);
566	548	if (ret)
567	549	return ret;
...	...	@@ -571,15 +553,6 @@
571	553	} while (start < end);
572	554
573	555	return 0;
574		-}
575		-
576		-static long do_cache_op_restart(struct restart_block *unused)
577		-{
578		- struct arm_restart_block *restart_block;
579		-
580		- restart_block = &current_thread_info()->arm_restart_block;
581		- return __do_cache_op(restart_block->cache.start,
582		- restart_block->cache.end);
583	556	}
584	557
585	558	static inline int
...	...	@@ -270,7 +270,6 @@
270	270	/* Auxiliary Debug Modes Control 1 Register */
271	271	#define PJ4B_STATIC_BP (1 << 2) /* Enable Static BP */
272	272	#define PJ4B_INTER_PARITY (1 << 8) /* Disable Internal Parity Handling */
273		-#define PJ4B_BCK_OFF_STREX (1 << 5) /* Enable the back off of STREX instr */
274	273	#define PJ4B_CLEAN_LINE (1 << 16) /* Disable data transfer for clean line */
275	274
276	275	/* Auxiliary Debug Modes Control 2 Register */
...	...	@@ -293,7 +292,6 @@
293	292	/* Auxiliary Debug Modes Control 1 Register */
294	293	mrc p15, 1, r0, c15, c1, 1
295	294	orr r0, r0, #PJ4B_CLEAN_LINE
296		- orr r0, r0, #PJ4B_BCK_OFF_STREX
297	295	orr r0, r0, #PJ4B_INTER_PARITY
298	296	bic r0, r0, #PJ4B_STATIC_BP
299	297	mcr p15, 1, r0, c15, c1, 1
...	...	@@ -535,7 +535,7 @@
535	535	mrc p15, 0, r5, c15, c1, 0 @ CP access reg
536	536	mrc p15, 0, r6, c13, c0, 0 @ PID
537	537	mrc p15, 0, r7, c3, c0, 0 @ domain ID
538		- mrc p15, 0, r8, c1, c1, 0 @ auxiliary control reg
	538	+ mrc p15, 0, r8, c1, c0, 1 @ auxiliary control reg
539	539	mrc p15, 0, r9, c1, c0, 0 @ control reg
540	540	bic r4, r4, #2 @ clear frequency change bit
541	541	stmia r0, {r4 - r9} @ store cp regs
...	...	@@ -552,7 +552,7 @@
552	552	mcr p15, 0, r6, c13, c0, 0 @ PID
553	553	mcr p15, 0, r7, c3, c0, 0 @ domain ID
554	554	mcr p15, 0, r1, c2, c0, 0 @ translation table base addr
555		- mcr p15, 0, r8, c1, c1, 0 @ auxiliary control reg
	555	+ mcr p15, 0, r8, c1, c0, 1 @ auxiliary control reg
556	556	mov r0, r9 @ control register
557	557	b cpu_resume_mmu
558	558	ENDPROC(cpu_xscale_do_resume)