17 Oct, 2014
5 commits
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On the Haswell platform, a split BAR option to allow creation of 2
32bit BARs (4 and 5) from the 64bit BAR 4. Adding support for this
new option.Signed-off-by: Dave Jiang
Signed-off-by: Jon Mason -
Instead of using a module parameter, we should detect the errata via
PCI DID and then set an appropriate flag. This will be used for additional
errata later on.Signed-off-by: Dave Jiang
Signed-off-by: Jon Mason -
To simplify some of the platform detection code. Move the platform detection
to a function to be called earlier.Signed-off-by: Dave Jiang
Signed-off-by: Jon Mason -
Move the platform detection function to separate functions to allow
easier maintenence.Signed-off-by: Dave Jiang
Signed-off-by: Jon Mason -
Create a debugfs entry for the NTB device to log the basic device info,
as well as display the error count on a number of registers.Signed-off-by: Jon Mason
14 Sep, 2014
2 commits
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The NTB translate register must have the value to be BAR size aligned.
This alignment check make sure that the DMA memory allocated has the
proper alignment. Another requirement for NTB to function properly with
memory window BAR size greater or equal to 4M is to use the CMA feature
in 3.16 kernel with the appropriate CONFIG_CMA_ALIGNMENT and
CONFIG_CMA_SIZE_MBYTES set.Signed-off-by: Dave Jiang
Signed-off-by: Jon Mason -
The detection of an uneven number of queues on the given memory windows
was not correct. The mw_num is zero based and the mod should be
division to spread them evenly over the mw's.Signed-off-by: Jon Mason
08 Apr, 2014
7 commits
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As result of deprecation of MSI-X/MSI enablement functions
pci_enable_msix() and pci_enable_msi_block() all drivers
using these two interfaces need to be updated to use the
new pci_enable_msi_range() or pci_enable_msi_exact()
and pci_enable_msix_range() or pci_enable_msix_exact()
interfaces.Signed-off-by: Alexander Gordeev
Signed-off-by: Jon Mason -
This is an cleanup effort to make ntb_setup_msix() more
readable - use ntb_setup_bwd_msix() to init MSI-Xs on
BWD hardware and ntb_setup_snb_msix() - on SNB hardware.Function ntb_setup_snb_msix() also initializes MSI-Xs the
way it should has been done - looping pci_enable_msix()
until success or failure.Signed-off-by: Alexander Gordeev
Signed-off-by: Jon Mason -
Signed-off-by: Alexander Gordeev
Signed-off-by: Jon Mason -
Some white space and 80 char overruns corrected.
Signed-off-by: Jon Mason
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Provide a better event interface between the client and transport
Signed-off-by: Jon Mason
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Signed-off-by: Alexander Gordeev
Signed-off-by: Jon Mason -
In the code for Xeon devices in back-to-back mode with xeon_errata_workaround
disabled, the downstream device puts the wrong value in SNB_B2B_XLAT_OFFSETL
(SNB_MBAR01_DSD_ADDR vs. SNB_MBAR01_USD_ADDR).This was spotted while reading code, since the typo has no practical effect,
at least for now: the low 32 bits of both constants are actually identical
anyway. However, it's clearer and safer to use the right name.Signed-off-by: Roland Dreier
Signed-off-by: Jon Mason
27 Nov, 2013
1 commit
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Pull non-transparent bridge updates from Jon Mason:
"NTB driver bug fixes to address a missed call to pci_enable_msix,
NTB-RP Link Up issue, Xeon Doorbell errata workaround, ntb_transport
link down race, and correct dmaengine_get/put usage.Also, clean-ups to remove duplicate defines and document a hardware
errata. Finally, some changes to improve performance"* tag 'ntb-3.13' of git://github.com/jonmason/ntb:
NTB: Disable interrupts and poll under high load
NTB: Enable Snoop on Primary Side
NTB: Document HW errata
NTB: remove duplicate defines
NTB: correct dmaengine_get/put usage
NTB: Fix ntb_transport link down race
ntb: Fix missed call to pci_enable_msix()
NTB: Fix NTB-RP Link Up
NTB: Xeon Doorbell errata workaround
21 Nov, 2013
9 commits
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Disable interrupts and poll under high load
Signed-off-by: Jon Mason
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Enable Snoop from Primary to Secondary side on BAR23 and BAR45 on all
TLPs. Previously, Snoop was only enabled from Secondary to Primary
side. This can have a performance improvement on some workloads.Also, make the code more obvious about how the link is being enabled.
Signed-off-by: Jon Mason
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Add a comment describing the necessary ordering of modifications to the
NTB Limit and Base registers.Signed-off-by: Jon Mason
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Remove duplicate defines in drivers/ntb/ntb_regs.h
Signed-off-by: Michael Opdenacker
Signed-off-by: Jon Mason -
dmaengine_get() causes the initialization of the per-cpu channel tables.
It needs to be called prior to dma_find_channel().Initial version by Dan Williams
Signed-off-by: Jon Mason
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A WARN_ON is being hit in ntb_qp_link_work due to the NTB transport link
being down while the ntb qp link is still active. This is caused by the
transport link being brought down prior to the qp link worker thread
being terminated. To correct this, shutdown the qp's prior to bringing
the transport link down. Also, only call the qp worker thread if it is
in interrupt context, otherwise call the function directly.Signed-off-by: Jon Mason
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Current MSI-X enablement code assumes MSI-Xs were successfully
allocated in case less than requested vectors were available.
That assumption is wrong, since MSI-Xs should be enabled with
a repeated call to pci_enable_msix(). This update fixes this.Signed-off-by: Alexander Gordeev
Signed-off-by: Jon Mason -
The Xeon NTB-RP setup, the transparent side does not get a link up/down
interrupt. Since the presence of a NTB device on the transparent side
means that we have a NTB link up, we can work around the lack of an
interrupt by simply calling the link up function to notify the upper
layers.Signed-off-by: Jon Mason
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Modifications to the 14th bit of the B2BDOORBELL register will not be
mirrored to the remote system due to a hardware issue. To get around
the issue, shrink the number of available doorbell bits by 1. The max
number of doorbells was being used as a way to referencing the Link
Doorbell bit. Since this would no longer work, the driver must now
explicitly reference that bit.This does not affect the xeon_errata_workaround case, as it is not using
the b2bdoorbell register.Signed-off-by: Jon Mason
15 Nov, 2013
2 commits
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Remove no longer needed DMA unmap flags:
- DMA_COMPL_SKIP_SRC_UNMAP
- DMA_COMPL_SKIP_DEST_UNMAP
- DMA_COMPL_SRC_UNMAP_SINGLE
- DMA_COMPL_DEST_UNMAP_SINGLECc: Vinod Koul
Cc: Tomasz Figa
Cc: Dave Jiang
Signed-off-by: Bartlomiej Zolnierkiewicz
Signed-off-by: Kyungmin Park
Acked-by: Jon Mason
Acked-by: Mark Brown
[djbw: clean up straggling skip unmap flags in ntb]
Signed-off-by: Dan Williams -
Use the generic unmap object to unmap dma buffers.
Cc: Vinod Koul
Cc: Tomasz Figa
Cc: Dave Jiang
Signed-off-by: Bartlomiej Zolnierkiewicz
Signed-off-by: Kyungmin Park
Acked-by: Jon Mason
[djbw: fix up unmap len, and GFP flags]
Signed-off-by: Dan Williams
06 Sep, 2013
8 commits
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PCI core will initialize device MSI/MSI-X capability in
pci_msi_init_pci_dev(). So device driver should use
pci_dev->msi_cap/msix_cap to determine whether the device
support MSI/MSI-X instead of using
pci_find_capability(pci_dev, PCI_CAP_ID_MSI/MSIX).
Access to PCIe device config space again will consume more time.Signed-off-by: Yijing Wang
Signed-off-by: Jon Mason -
Update NTB version to 1.0
Signed-off-by: Jon Mason
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Add "data" ntb_register_db_callback parameter description comment and
correct poor spelling.Signed-off-by: Jon Mason
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Remove unused pci_dev variable from ntb_transport_free()
Signed-off-by: Jon Mason
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NTB-RP is not a supported configuration on BWD hardware. Remove the
code attempting to set it up.Signed-off-by: Jon Mason
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Add support for Non-Transparent Bridge connected to a PCI-E Root Port on
the remote system (also known as NTB-RP mode). This allows for a NTB
enabled system to be connected to a non-NTB enabled system/slot.Modifications to the registers and BARs/MWs on the Secondary side by the
remote system are reflected into registers on the Primary side for the
local system. Similarly, modifications of registers and BARs/MWs on
Primary side by the local system are reflected into registers on the
Secondary side for the Remote System. This allows communication between
the 2 sides via these registers and BARs/MWs.Note: there is not a fix for the Xeon Errata (that was already worked
around in NTB-B2B mode) for NTB-RP mode. Due to this limitation, NTB-RP
will not work on the Secondary side with the Xeon Errata workaround
enabled. To get around this, disable the workaround via the
xeon_errata_workaround=0 modparm. However, this can cause the hang
described in the errata.Signed-off-by: Jon Mason
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Many variable names in the NTB driver refer to the primary or secondary
side. However, these variables will be used to access the reverse case
when in NTB-RP mode. Make these names more generic in anticipation of
NTB-RP support.Signed-off-by: Jon Mason
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Allocate and use a DMA engine channel to transmit and receive data over
NTB. If none is allocated, fall back to using the CPU to transfer data.Signed-off-by: Jon Mason
Reviewed-by: Dan Williams
Reviewed-by: Dave Jiang
04 Sep, 2013
6 commits
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Correct the issues on NTB that prevented it from working on x86_32 and
modify the Kconfig to allow it to be permitted to be used in that
environment as well.Signed-off-by: Jon Mason
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Add support for new Intel NTB devices on upcoming Xeon hardware. Since
the Xeon hardware design is already in place in the driver, all that is
needed are the new device ids.Remove the device IDs for NTB devs running in Transparent Bridge mode,
as this driver is not being used for those devices.Rename the device IDs for NTB devs running in NTB-RP mode to better
identify their usage model. "PS" to denote the Primary Side of NTB, and
"SS" to denote the secondary side. The primary side is the interface
exposed to the local system, and the secondary side is the interface
exposed to the remote system.Signed-off-by: Jon Mason
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The BWD NTB device will drop the link if an error is encountered on the
point-to-point PCI bridge. The link will stay down until all errors are
cleared and the link is re-established. On link down, check to see if
the error is detected, if so do the necessary housekeeping to try and
recover from the error and reestablish the link.There is a potential race between the 2 NTB devices recovering at the
same time. If the times are synchronized, the link will not recover and the
driver will be stuck in this loop forever. Add a random interval to the
recovery time to prevent this race.Signed-off-by: Jon Mason
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There is a Xeon hardware errata related to writes to SDOORBELL or
B2BDOORBELL in conjunction with inbound access to NTB MMIO Space, which
may hang the system. To workaround this issue, use one of the memory
windows to access the interrupt and scratch pad registers on the remote
system. This bypasses the issue, but removes one of the memory windows
from use by the transport. This reduction of MWs necessitates adding
some logic to determine the number of available MWs.Since some NTB usage methodologies may have unidirectional traffic, the
ability to disable the workaround via modparm has been added.See BF113 in
http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/xeon-c5500-c3500-spec-update.pdf
See BT119 in
http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/xeon-e5-family-spec-update.pdfSigned-off-by: Jon Mason
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Debugfs was setup in NTB to only have a single debugfs directory. This
resulted in the leaking of debugfs directories and files when multiple
NTB devices were present, due to each device stomping on the variables
containing the previous device's values (thus preventing them from being
freed on cleanup). Correct this by creating a secondary directory of
the PCI BDF for each device present, and nesting the previously existing
information in those directories.Signed-off-by: Jon Mason
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Due to ambiguous documentation, the USD/DSD identification is backward
when compared to the setting in BIOS. Correct the bits to match the
BIOS setting.Signed-off-by: Jon Mason