06 Feb, 2015
1 commit
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commit a0b957f306fa4d0a39f4ffe5e5e25e856e6be46e upstream.
Today we expect that all the bank are enabled, and count the number of banks
used by the pinctrl based on it instead of using the last bank id enabled.So switch to it, set the chained IRQ at runtime based on enabled banks
and wait only the number of enabled gpio controllers at probe time.Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD
Signed-off-by: Ludovic Desroches
Acked-by: Nicolas Ferre
Signed-off-by: Linus Walleij
Signed-off-by: Greg Kroah-Hartman
08 Oct, 2014
1 commit
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Pull pin control changes from Linus Walleij:
"This is the bulk of pin control changes for the v3.18 development
series:- New drivers for the Freescale i.MX21, Qualcomm APQ8084 pin
controllers.- Incremental new features on the Rockchip, atlas 6, OMAP, AM437x,
APQ8064, prima2, AT91, Tegra, i.MX, Berlin and Nomadik.- Push Freescale drivers down into their own subdirectory.
- Assorted sprays of syntax and semantic fixes"
* tag 'pinctrl-v3.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (48 commits)
pinctrl: specify bindings for pins and groups
pinctrl: nomadik: improve GPIO debug prints
pinctrl: abx500: refactor DT parser to take two paths
pinctrl: abx500: use helpers for map allocation/free
pinctrl: alter device tree bindings for functions
pinctrl: nomadik: refactor DT parser to take two paths
pinctrl: nomadik: use utils map free function
pinctrl: nomadik: use util function to reserve maps
pinctrl: qcom: use restart_notifier mechanism for ps_hold
pinctrl: sh-pfc: sh73a0: Remove unnecessary SoC data allocation
pinctrl: berlin: fix the dt_free_map function
pinctrl: at91: disable PD or PU before enabling PU or PD
pinctrl: st: remove gpiochip in failure cases
pinctrl: at91: Fix error handling while doing gpiochio_irqchip_add
pinctrl: at91: Fix failure path in at91_gpio_probe path
pinctrl: lantiq: Release gpiochip resources in fail case
pinctrl: imx: detect uninitialized pins
pinctrl: tegra: Add MIPI pad control
pinctrl: at91: Switch to using managed clk_get
pinctrl: adi2: Remove duplicate gpiochip_remove_pin_ranges
...
23 Sep, 2014
3 commits
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Disable Pull-Down or Pull-Up property before enabling Pull-Up or
Pull-Down, because the pin's Pull-Up and Pull-Down property is
mutually exclusive.Signed-off-by: Wenyou Yang
Acked-by: Nicolas Ferre
Signed-off-by: Linus Walleij -
This patch removes a call to panic function when gpiochio_irqchip_add
fails and just returns the error to the calling function.
Same return value is used to handle the error case and adds a lable
to release resources on error.
The error message has been improved to indicate failure to add irqchip
to gpiochip.This also changes first argument to function at91_gpio_of_irq_setup from
struct device_node to struct platform_device. Because The device_node
argument was anyway not being used. Passed pdev so that on failure dev_err
can use &pdev->dev and log can be associated with proper device.CC: Jean-Christophe Plagniol-Villard
CC: Linus Walleij
Signed-off-by: Pramod Gurav
Signed-off-by: Linus Walleij -
This fixes the whole error handling in probe function by capturing and
returning error values on kernel function like clk_prepare,
clk_enable, gpiochip_add etc.CC: Jean-Christophe Plagniol-Villard
CC: Linus Walleij
Signed-off-by: Pramod Gurav
Signed-off-by: Linus Walleij
05 Sep, 2014
2 commits
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This patch switches to using managed version of clk_get and hence
removes clk_put from failure path.CC: Jean-Christophe Plagniol-Villard
CC: Linus Walleij
Signed-off-by: Pramod Gurav
Signed-off-by: Linus Walleij -
The SAMA5 and SAM9x5 series both have drive strength
options for the PIOs. This patch adds the ability to set
one of three hardware options for drive strengths of low,
medium or high for the each pin. The actual current output
of the chip based on the setting is defined in the datasheets
and varies per pins separate from banks and with supply
voltage.This patch adds three new dt-bindings that allow setting the
strength when configuring pins. By default, no change will
be made to the drive strength of a pin from its reset value.
Due to the difference between the register addresses of the
SAMA5 and SAM9x5 series, a new sama5d3-pinctrl id was added.Signed-off-by: Marek Roszko
Acked-by: Nicolas Ferre
Signed-off-by: Linus Walleij
04 Sep, 2014
1 commit
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commit 2243a87d90b42eb38bc281957df3e57c712b5e56
"pinctrl: avoid duplicated calling enable_pinmux_setting for a pin"
removed the .disable callback from the struct pinmux_ops,
making the .enable() callback the only remaining callback.However .enable() is a bad name as it seems to imply that a
muxing can also be disabled. Rename the callback to .set_mux()
and also take this opportunity to clean out any remaining
mentions of .disable() from the documentation.Acked-by: Stephen Warren
Acked-by: Bjorn Andersson
Acked-by: Fan Wu
Signed-off-by: Linus Walleij
17 Aug, 2014
1 commit
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The prefix suggests the number should be printed in hex, so use
the %x specifier to do that.Found by using regex suggested by Joe Perches.
Signed-off-by: Hans Wennborg
Acked-by: Alexandre Belloni
Signed-off-by: Linus Walleij
11 Jul, 2014
3 commits
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Remove variable that are never used
This was found using a static code analysis program called cppcheck.
Signed-off-by: Rickard Strandqvist
Signed-off-by: Linus Walleij -
Remove checking if a unsigned is less than zero
This was found using a static code analysis program called cppcheck.
Signed-off-by: Rickard Strandqvist
Signed-off-by: Linus Walleij -
What the patch does:
1. Call pinmux_disable_setting ahead of pinmux_enable_setting
each time pinctrl_select_state is called
2. Remove the HW disable operation in pinmux_disable_setting function.
3. Remove the disable ops in struct pinmux_ops
4. Remove all the disable ops users in current code base.Notes:
1. Great thanks for the suggestion from Linus, Tony Lindgren and
Stephen Warren and Everyone that shared comments on this patch.
2. The patch also includes comment fixes from Stephen Warren.The reason why we do this:
1. To avoid duplicated calling of the enable_setting operation
without disabling operation inbetween which will let the pin
descriptor desc->mux_usecount increase monotonously.
2. The HW pin disable operation is not useful for any of the
existing platforms.
And this can be used to avoid the HW glitch after using the
item #1 modification.In the following case, the issue can be reproduced:
1. There is a driver that need to switch pin state dynamically,
e.g. between "sleep" and "default" state
2. The pin setting configuration in a DTS node may be like this:component a {
pinctrl-names = "default", "sleep";
pinctrl-0 = ;
pinctrl-1 = ;
}The "c_grp_setting" config node is totally identical, maybe like
following one:c_grp_setting: c_grp_setting {
pinctrl-single,pins = ;
}3. When switching the pin state in the following official pinctrl
sequence:
pin = pinctrl_get();
state = pinctrl_lookup_state(wanted_state);
pinctrl_select_state(state);
pinctrl_put();Test Result:
1. The switch is completed as expected, that is: the device's
pin configuration is changed according to the description in the
"wanted_state" group setting
2. The "desc->mux_usecount" of the corresponding pins in "c_group"
is increased without being decreased, because the "desc" is for
each physical pin while the setting is for each setting node
in the DTS.
Thus, if the "c_grp_setting" in pinctrl-0 is not disabled ahead
of enabling "c_grp_setting" in pinctrl-1, the desc->mux_usecount
will keep increasing without any chance to be decreased.According to the comments in the original code, only the setting,
in old state but not in new state, will be "disabled" (calling
pinmux_disable_setting), which is correct logic but not intact. We
still need consider case that the setting is in both old state
and new state. We can do this in the following two ways:1. Avoid to "enable"(calling pinmux_enable_setting) the "same pin
setting" repeatedly
2. "Disable"(calling pinmux_disable_setting) the "same pin setting",
actually two setting instances, ahead of enabling them.Analysis:
1. The solution #2 is better because it can avoid too much
iteration.
2. If we disable all of the settings in the old state and one of
the setting(s) exist in the new state, the pins mux function
change may happen when some SoC vendors defined the
"pinctrl-single,function-off"
in their DTS file.
old_setting => disabled_setting => new_setting.
3. In the pinmux framework, when a pin state is switched, the
setting in the old state should be marked as "disabled".Conclusion:
1. To Remove the HW disabling operation to above the glitch mentioned
above.
2. Handle the issue mentioned above by disabling all of the settings
in old state and then enable the all of the settings in new state.Signed-off-by: Fan Wu
Acked-by: Stephen Warren
Acked-by: Patrice Chotard
Acked-by: Heiko Stuebner
Acked-by: Maxime Coquelin
Signed-off-by: Linus Walleij
27 May, 2014
1 commit
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With commit 80cc3732 (pinctrl/at91: convert driver to use gpiolib irqchip)
gpiochip_set_chained_irqchip is called for PIOC, PIOD and PIOE. The
associated GPIO chip for the IRQ chip is overwritten each time, because
they share the same hard IRQ line.
Thus if an IRQ occurs on PIOC or PIOD, gpio_irq_handler will only check on
PIOE (the assigned GPIO chip) where no event occured. Thus the IRQ will
not be cleared, retriggering the ISR.
Fix that (like done before) by only set the PIOC GPIO chip to the IRQ chip
and walk the list in the irq handler.Signed-off-by: Alexander Stein
Signed-off-by: Linus Walleij
23 Apr, 2014
2 commits
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pin_to_mask expects a bank pin number. So do not add the chip base.
Without that patch cat /sys/kernel/debug/gpio looks like that:
GPIOs 0-31, platform/fffff200.gpio, fffff200.gpio:
[spi32766.0] GPIOfffff200.gpio5: [gpio] set
[ads7846_pendown] GPIOfffff200.gpio15: [gpio] set
[ohci_vbus] GPIOfffff200.gpio21: [gpio] set
[ohci_vbus] GPIOfffff200.gpio24: [gpio] set
[button1] GPIOfffff200.gpio28: [gpio] clear
[button2] GPIOfffff200.gpio29: [gpio] clearGPIOs 32-63, platform/fffff400.gpio, fffff400.gpio:
[sda] GPIOfffff400.gpio4: [periph A]
[scl] GPIOfffff400.gpio5: [periph A]
[spi32766.3] GPIOfffff400.gpio11: [periph A]
[error] GPIOfffff400.gpio22: [periph A]
[run] GPIOfffff400.gpio23: [periph A]GPIOs 64-95, platform/fffff600.gpio, fffff600.gpio:
[reset_pin] GPIOfffff600.gpio29: [periph A]GPIOs 96-127, platform/fffff800.gpio, fffff800.gpio:
[led1] GPIOfffff800.gpio5: [periph A]
[led2] GPIOfffff800.gpio6: [periph A]
[led3] GPIOfffff800.gpio7: [periph A]
[led4] GPIOfffff800.gpio8: [periph A]GPIOs 128-159, platform/fffffa00.gpio, fffffa00.gpio:
[button3] GPIOfffffa00.gpio10: [periph A]
[button4] GPIOfffffa00.gpio12: [periph A]Note that every bank despite bank 0 only shows "periph A" which are
obviously used as GPIOs.Signed-off-by: Alexander Stein
Acked-by: Alexandre Belloni
Acked-by: Nicolas Ferre
Signed-off-by: Linus Walleij -
This converts the AT91 pin control driver to register its
chained irq handler and irqchip using the helpers in the
gpiolib core.Signed-off-by: Alexander Stein
Signed-off-by: Linus Walleij
25 Feb, 2014
1 commit
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This is needed for gpiod_get_direction().
Otherwise, it returns -EINVAL.Signed-off-by: Richard Genoud
Signed-off-by: Linus Walleij
10 Feb, 2014
1 commit
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When an IRQ is started on a GPIO line, mark this GPIO as IRQ in
the gpiolib so we can keep track of the usage centrally.Signed-off-by: Jean-Jacques Hiblot
Signed-off-by: Linus Walleij
03 Feb, 2014
1 commit
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When setting the gpio irq type, use the __irq_set_handler_locked()
variant instead of the irq_set_handler() to prevent false
spinlock recursion warning.Signed-off-by: Nicolas Ferre
Cc: stable # v3.12
Signed-off-by: Linus Walleij
22 Jan, 2014
1 commit
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Pull bulk pin control changes from Linus Walleij:
"This has been queued and tested for a while. Lots of action here,
like in the GPIO tree, embedded stuff like this is really hot now it
seems. Details in the signed tag. I'm especially happy about the
Qualcomm driver as it is used in such a huge subset of mobile handsets
out there, and these platforms in general need better upstream support- New driver for the Qualcomm TLMM pin controller and its msm8x74
subdriver.- New driver for the Broadcom Capri BCM281xx SoC.
- New subdriver for the imx25 pin controller.
- New subdriver for the Tegra124 pin controller.
- Lock GPIO lines as IRQs for select combined pin control and GPIO
drivers for baytrail and sirf.- Some semi-big refactorings and extenstions to the sirf driver.
- Lots of patching, cleanup and fixing in the Renesas "PFC" driver
and associated subdrivers as usual. It is settling down a little
bit now it seems.- Minor fixes and incremental updates here and there as usual"
* tag 'pinctrl-v3.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (72 commits)
pinctrl: sunxi: Honor GPIO output initial vaules
pinctrl: capri: add dependency on OF
ARM: bcm11351: Enable pinctrl for Broadcom Capri SoCs
ARM: pinctrl: Add Broadcom Capri pinctrl driver
pinctrl: Add pinctrl binding for Broadcom Capri SoCs
pinctrl: Add void * to pinctrl_pin_desc
pinctrl: st: Fix a typo in probe
pinctrl: Fix some typos and grammar issues in the documentation
pinctrl: sirf: lock IRQs when starting them
pinctrl: sirf: put gpio interrupt pin into input status automatically
pinctrl: sirf: use only one irq_domain for the whole device node
pinctrl: single: fix infinite loop caused by bad mask
pinctrl: single: fix pcs_disable with bits_per_mux
pinctrl: single: fix DT bindings documentation
pinctrl: as3722: Set pin to output mode for some function
pinctrl: sirf: add pin group for USP0 with only RX or TX frame sync
pinctrl: sirf: fix the pins of sdmmc5 connected with TriG
pinctrl: sirf: add lost usp1_uart_nostreamctrl group for atlas6
pinctrl: sunxi: Add Allwinner A20 clock output pin functions
pinctrl/lantiq: fix typo
...
16 Dec, 2013
2 commits
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Replace the clk_prepare and clk_enable calls by a single
clk_prepare_enable call.Signed-off-by: Boris BREZILLON
Acked-by: Nicolas Ferre
Signed-off-by: Linus Walleij -
clk_unprepare shall be called before clk_disable.
Fix the issue by replacing the clk_unprepare and clk_disable calls by a
single clk_disable_unprepare call.Signed-off-by: Boris BREZILLON
Acked-by: Nicolas Ferre
Signed-off-by: Linus Walleij
13 Dec, 2013
1 commit
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This allows to get the pin configuration by using debugfs. On my system:
# cat /sys/kernel/debug/pinctrl/pinctrl.3/pinconf-pinsSigned-off-by: Alexandre Belloni
Acked-by: Nicolas Ferre
Signed-off-by: Linus Walleij
12 Dec, 2013
2 commits
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When passing a not initialized config parameter, at91_pinconf_get() would return
a bogus value. Fix that by initializing it to zero before using it.Signed-off-by: Alexandre Belloni
Signed-off-by: Linus Walleij -
Signed-off-by: Alexandre Belloni
Signed-off-by: Linus Walleij
04 Dec, 2013
1 commit
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This switches the two members of struct gpio_chip that were
defined as unsigned foo:1 to bool, because that is indeed what
they are. Switch all users in the gpio and pinctrl subsystems
to assign these values with true/false instead of 0/1. The
users outside these subsystems will survive since true/false
is 1/0, atleast we set some kind of more strict typing example.Signed-off-by: Linus Walleij
05 Nov, 2013
1 commit
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The #define for the maximum number of GPIO blocks was retrieved
into pinctrl-at91.c by implicit inclusion of
from creating a dependency on machine-local
. Break the depenency by copying this single
define into the driver.Acked-by: Nicolas Ferre
Signed-off-by: Linus Walleij
23 Oct, 2013
1 commit
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Signed-off-by: Alexandre Belloni
Acked-by: Nicolas Ferre
Signed-off-by: Linus Walleij
08 Oct, 2013
1 commit
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The data structure of_match_ptr() protects is always compiled in.
Hence of_match_ptr() is not needed.This is a squash commit of:
pinctrl: at91: Remove redundant of_match_ptr
pinctrl: exynos5440: Remove redundant of_match_ptr
pinctrl: imx35: Remove redundant of_match_ptr
pinctrl: imx51: Remove redundant of_match_ptr
pinctrl: imx53: Remove redundant of_match_ptr
pinctrl: imx6dl: Remove redundant of_match_ptr
pinctrl: imx6q: Remove redundant of_match_ptr
pinctrl: samsung: Remove redundant of_match_ptr
pinctrl: vf610: Remove redundant of_match_ptr
pinctrl: imx6sl: Remove redundant of_match_ptr
pinctrl: plgpio: Remove redundant of_match_ptrAcked-by: Viresh Kumar
Signed-off-by: Sachin Kamat
Signed-off-by: Linus Walleij
27 Sep, 2013
2 commits
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Replace at91_mux_get_deglitch with at91_mux_pio3_get_deglitch when using
sam9x5 (pio3) IP.
at91_mux_get_deglitch only test the activation of the "Input Filter" which
may be overloaded by the activation of the "Input Filter Slow Clock" to use
the input filter as a debounce filter instead of a deglitch filter.Fix at91_mux_pio3_get_debounce to test the activation of the Input Filter
before testing the activation of the debounce filter (Input Filter Slow
Clock depends on Input Filter).Fix at91_mux_pio3_set_debounce function to avoid disabling the deglitch
filter ("Input Filter") when debounce filter is disabled.Signed-off-by: Boris BREZILLON
Acked-by: Jean-Christophe PLAGNIOL-VILLARD
Signed-off-by: Linus Walleij -
Fix AT91_PINCTRL_DEBOUNCE_VAL dt macro typo.
Fix at91_pinctrl_mux_ops callback typos.Signed-off-by: Boris BREZILLON
Acked-by: Jean-Christophe PLAGNIOL-VILLARD
Signed-off-by: Linus Walleij
29 Aug, 2013
1 commit
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In PIO_PUSR and PIO_PPDSR register if a given bit is set 1 this means the
pullup/down for this pin (pin is represented as a bit position) is
disabled.Cc: stable # 3.8+
Signed-off-by: Boris BREZILLON
Acked-by: Nicolas Ferre
Signed-off-by: Linus Walleij
28 Aug, 2013
1 commit
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When setting pin configuration in the pinctrl framework, pin_config_set() or
pin_config_group_set() is called in a loop to set one configuration at a time
for the specified pin or group.This patch 1) removes the loop and 2) changes the API to pass the whole pin
config array to the driver. It is now up to the driver to loop through the
configs. This allows the driver to potentially combine configs and reduce the
number of writes to pin config registers.All c files changed have been build-tested to verify the change compiles and
that the corresponding .o is successfully generated.Signed-off-by: Sherman Yin
Reviewed-by: Christian Daudt
Reviewed-by: Matt Porter
Tested-by: Stephen Warren
Acked-by: Laurent Pinchart
Signed-off-by: Linus Walleij
08 Aug, 2013
1 commit
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The current implementation handle both edge and level interrupts with the
'handle_simple_irq' handler.Level interrupts are active as long as the pin stays at the configured
level (low or high). In this case we have to use 'handle_level_irq' which
mask the interrupt until the handle has treated it.Signed-off-by: Boris BREZILLON
Tested-by: Alexandre Belloni
Signed-off-by: Linus Walleij
16 Jun, 2013
1 commit
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devm_ioremap_resource does sanity checks on the given resource. No need to
duplicate this in the driver.Signed-off-by: Wolfram Sang
Acked-by: Jean-Christophe PLAGNIOL-VILLARD
Signed-off-by: Linus Walleij
03 May, 2013
1 commit
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Pull ARM SoC cleanup from Olof Johansson:
"Here is a collection of cleanup patches. Among the pieces that stand
out are:- The deletion of h720x platforms
- Split of at91 non-dt platforms to their own Kconfig file to keep
them separate
- General cleanups and refactoring of i.MX and MXS platforms
- Some restructuring of clock tables for OMAP
- Convertion of PMC driver for Tegra to dt-only
- Some renames of sunxi -> sun4i (Allwinner A10)
- ... plus a bunch of other stuff that I haven't mentioned"* tag 'cleanup-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (119 commits)
ARM: i.MX: remove unused ARCH_* configs
ARM i.MX53: remove platform ahci support
ARM: sunxi: Rework the restart code
irqchip: sunxi: Rename sunxi to sun4i
irqchip: sunxi: Make use of the IRQCHIP_DECLARE macro
clocksource: sunxi: Rename sunxi to sun4i
clocksource: sunxi: make use of CLKSRC_OF
clocksource: sunxi: Cleanup the timer code
ARM: at91: remove trailing semicolon from macros
ARM: at91/setup: fix trivial typos
ARM: EXYNOS: remove "config EXYNOS_DEV_DRM"
ARM: EXYNOS: change the name of USB ohci header
ARM: SAMSUNG: Remove unnecessary code for dma
ARM: S3C24XX: Remove unused GPIO drive strength register definitions
ARM: OMAP4+: PM: Restore CPU power state to ON with clockdomain force wakeup method
ARM: S3C24XX: Removed unneeded dependency on CPU_S3C2412
ARM: S3C24XX: Removed unneeded dependency on CPU_S3C2410
ARM: S3C24XX: Removed unneeded dependency on ARCH_S3C24XX for boards
ARM: SAMSUNG: Fix typo "CONFIG_SAMSUNG_DEV_RTC"
ARM: S5P64X0: Fix typo "CONFIG_S5P64X0_SETUP_SDHCI"
...
09 Apr, 2013
1 commit
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This is a dependency for the mxs/cleanup branch.
Signed-off-by: Arnd Bergmann
04 Apr, 2013
1 commit
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Linux 3.9-rc5
Conflicts:
drivers/pinctrl/pinconf.c
28 Mar, 2013
2 commits
-
Fixes the following types of checkpatch errors:
ERROR: "foo * bar" should be "foo *bar"
ERROR: "foo* bar" should be "foo *bar"
ERROR: space required before the open parenthesis '('
ERROR: "(foo*)" should be "(foo *)"
ERROR: space required after that ',' (ctx:WxV)
ERROR: "(foo*const*)" should be "(foo *const*)"
ERROR: space required before that '*' (ctx:VxB)Signed-off-by: Sachin Kamat
Signed-off-by: Linus Walleij -
const declared twice. Fixes the following sparse warning:
drivers/pinctrl/pinctrl-at91.c:815:21: warning: duplicate const
drivers/pinctrl/pinctrl-at91.c:849:21: warning: duplicate constSigned-off-by: Sachin Kamat
Signed-off-by: Linus Walleij
27 Mar, 2013
1 commit
-
These functions have been introduced by commit 10a8c383 (irq: introduce
entry and exit functions for chained handlers) in asm/mach/irq.h. This
patch moves them to linux/irqchip/chained_irq.h so that generic irqchip
drivers do not rely on architecture specific header files.Signed-off-by: Catalin Marinas
Tested-by: Marc Zyngier
Cc: Russell King
Cc: Thomas Gleixner
Cc: Rob Herring
