11 Nov, 2013
2 commits
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The clk_enet_ref_table[] is missing a final empty entry as end of list
marker. Also make the existing markers more obvious.Signed-off-by: Lothar Waßmann
Signed-off-by: Shawn Guo -
instead of pll3_usb_otg the parent of can_root clock
should be pll3_60m.Signed-off-by: Jiada Wang
Signed-off-by: Shawn Guo
21 Oct, 2013
5 commits
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The LPM (Low Power Mode) code that currently sits in imx6q clock driver
will be reused by imx6sl. Let's move it into pm-imx6q.c, so that we
can keep clock driver SoC specific and reuse pm-imx6q.c on imx6sl.In order to avoid adding another ioremap for CCM block,
imx6q_pm_set_ccm_base() is created to let clock driver set up ccm_base
for pm code.During the move, the unused CCGR macros get removed.
Signed-off-by: Shawn Guo
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Update imx6q clock initialization and Kconfig for PCIe support.
Signed-off-by: Sean Cross
Signed-off-by: Shawn Guo -
The i.MX6 has two general-purpose LVDS clocks that can be driven
from a variety of sources. This patch adds a mux and a gate for
both of these clocks.Signed-off-by: Sean Cross
Signed-off-by: Shawn Guo -
It calls imx_set_soc_revision() to set up soc revision in
imx6q_init_revision(), and replaces all the occurrences of
imx6q_revision() with common helper imx_get_soc_revision().Signed-off-by: Shawn Guo
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There's a pll4_audio_div clock, an extra divider for pll4, missing
in current clock tree, thus add it.Signed-off-by: Nicolin Chen
Signed-off-by: Shawn Guo
22 Aug, 2013
5 commits
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The CLKO is widely used by imx6q board designs to clock audio codec.
Since most codecs accept 24 MHz frequency, let's initially set up CLKO
with OSC24M (cko -
Add the missing vdoa gate clock for imx6q.
Signed-off-by: Shawn Guo
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The clock output on imx6q CCM_CLKO1 pad is not always cko1 clock, and
there is a multiplexer to select between cko1 and cko2. Add this
missing selection as the clock cko.Signed-off-by: Shawn Guo
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It adds the missing cko2 clocks, including multiplexer, divider and
gate.Signed-off-by: Shawn Guo
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It adds the missing spdif gate clock into imx6q clock driver.
Signed-off-by: Shawn Guo
16 Aug, 2013
2 commits
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All the clocks controlled by the register 'CCM Serial Clock
Multiplexer Register 1' should be fixup clocks. This patch
changes those clocks from basic multiplexer or divider clocks
to fixup clocks.Signed-off-by: Liu Ying
Signed-off-by: Shawn Guo -
i.MX6S/DL have the Video PLL post dividers fixed already in revision 1.0
Signed-off-by: Philipp Zabel
Signed-off-by: Shawn Guo
15 Jul, 2013
1 commit
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The correct muxing for emi_sel clock should be
2b'00 - 396M PFD
2b'01 - PLL3
2b'10 - AXI clk root
2b'11 - 352M PFDThis patch corrects the muxing in the clock driver.
Signed-off-by: Liu Ying
Signed-off-by: Shawn Guo
Acked-by: Dirk Behme
17 Jun, 2013
7 commits
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WM8962 needs 24MHz clock for its MCLK, so choose PLL4 as the parent of clko1.
Signed-off-by: Nicolin Chen
Signed-off-by: Shawn Guo -
Instead of explicitly calling clock initialization functions, we can
declare the functions with CLK_OF_DECLARE() and then call common
of_clk_init() to have them invoked properly.Signed-off-by: Shawn Guo
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As the fixed rate clocks are defined in device tree, we can just call
of_clk_init() to register them.Signed-off-by: Shawn Guo
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The CCM_CBCMR register (address 0x02C4018) has different meaning
between the i.MX6 Quad/Dual and the i.MX6 Solo/DualLite.Compared to the i.MX6 Quad/Dual, the CCM_CBCMR register in the
i.MX6 Solo/DualLite reuses the gpu2d_core bits for the MLB clock
configuration.Signed-off-by: Dirk Behme
Signed-off-by: Shawn Guo -
Add the eim_slow clock, since the weim needs it.
Signed-off-by: Huang Shijie
Signed-off-by: Shawn Guo -
The MLB PLL clock's operation doesn't fit for clock framework and
it should be handled internally in MLB driver.
Remove initialization of pll8_mlb clock device but leave its
declaration in mx6q_clks to avoid affecting imx6q clock numbering.Signed-off-by: Jiada Wang
CC: Dirk Behme
Signed-off-by: Shawn Guo -
The CCM_CBCMR register (address 0x02C4018) has different meaning
between the i.MX6 Quad/Dual and the i.MX6 Solo/DualLite.Compared to the i.MX6 Quad/Dual, the CCM_CBCMR register in the
i.MX6 Solo/DualLite doesn't have a gpu3d_shader configuration and
moves the gpu2_core configuration at that place.Handle these i.MX6 Quad/Dual vs. i.MX6 Solo/DualLite clock differences
by using cpu_is_mx6dl().Signed-off-by: Dirk Behme
Signed-off-by: Shawn Guo
03 Jun, 2013
1 commit
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The AXI clock mux should be as below:
00: periph;
01: pll2_pfd2_396m;
10: periph;
11: pll3_pfd1_540m;Signed-off-by: Anson Huang
Signed-off-by: Shawn Guo
23 May, 2013
1 commit
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As pll5_video_div has been introduced to represent the clock
generated from post-divider for video.
Instead of pll5_video, pll5_video_div should be proper root clock
for ldb_di_sel.Signed-off-by: Jiada Wang
Signed-off-by: Shawn Guo
12 May, 2013
3 commits
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There is no clock pll2_pfd9_720m. Instead it should be pll3_pfd0_720m.
Fix the typo in gpu3d_shader_sels.Signed-off-by: Shawn Guo
Acked-by: Dirk Behme -
According to the i.MX6 Dual/Quad technical reference manual
(Figure 18-2. Clock Tree - Part 1) the MLB clock is directly
feed by the AXI_CLK_ROOT. This is called 'axi' in our code.Note that the clock of the MLB IP block on the i.MX6 is completely
independent of the PLL8 (MLB PLL). The MLB PLL isn't responsible
for feeding the MLB IP block with a clock. Instead, it's used
internally by the MLB module to sync the bus clock in case the MLB
6-pin interface is enabled:MediaLB Control 0 Register, MLB150_MLBC0[5], MLBPEN:
1 MediaLB 6-pin interface enabled. MLB PLL and MLB PHY is enabled in this case.I.e. the PLL8 MLB PLL has to be handled by the MLB driver and isn't needed
for clocking the MLB module itself.Signed-off-by: Dirk Behme
CC: Jiada Wang
Signed-off-by: Shawn Guo -
The periph_clk2_sel mux can be set to pll3, osc/pll1_ref_clk, or osc/
pll2_burn_in_clk. The periph2_clk2_sel mux can be set to pll3 or pll2.Signed-off-by: Philipp Zabel
Signed-off-by: Shawn Guo
12 Apr, 2013
6 commits
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The i.MX6 DualLite/Solo is another i.MX6 family SoC, which is highly
compatible with i.MX6 Quad/Dual. And that's why we choose to support
it using imx6q code with cpu_is_imx6dl() check when necessary.Signed-off-by: Shawn Guo
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On i.MX6q revision 1.1 and later, set the video PLL as parent for
the LDB clock branch. On revision 1.0, the video PLL is useless
due to missing dividers, so keep the default parent (mmdc_ch1_axi).Signed-off-by: Philipp Zabel
Signed-off-by: Shawn Guo -
Query silicon revision to determine clock tree and add post
dividers for newer revisions.Signed-off-by: Philipp Zabel
Signed-off-by: Shawn Guo -
Use imx_clk_mux_flags and imx_clk_divider_flags to set the appropriate
flags for the LDB display interface divider and selector clocks.Signed-off-by: Philipp Zabel
Signed-off-by: Shawn Guo -
RBC is to control whether some ANATOP sub modules
can enter lpm mode when SOC is into STOP mode, if
RBC is enabled and PMIC_VSTBY_REQ is set, ANATOP
will have below behaviors:1. Digital LDOs(CORE, SOC and PU) are bypassed;
2. Analog LDOs(1P1, 2P5, 3P0) are disabled;As the 2P5 is necessary for DRAM IO pre-drive in
STOP mode, so we need to enable weak 2P5 in STOP
mode when 2P5 LDO is disabled.For RBC settings, there are some rules as below
due to hardware design:1. All interrupts must be masked during operating
RBC registers;
2. At least 2 CKIL(32K) cycles is needed after the
RBC setting is changed.Signed-off-by: Anson Huang
Signed-off-by: Shawn Guo -
Enable periphery charge pump for well biasing
at suspend to reduce periphery leakage.Signed-off-by: Anson Huang
Signed-off-by: Shawn Guo
09 Apr, 2013
2 commits
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According to the recent i.MX6 Quad technical reference manual, mode 0x4 (100b)
of the CCM_CS2DCR register (address 0x020C402C) bits [11-9] and [14-12] select
the PLL3 clock, and not the PLL3 PFD1 540M clock. In our code, the PLL3 root
clock is named 'pll3_usb_otg', select this instead of the 540M clock.Signed-off-by: Dirk Behme
Signed-off-by: Shawn Guo -
While booting from device tree, imx6q used to provide twd clock lookup
by calling clk_register_clkdev() in clock driver. However, the commit
bd60345 (ARM: use device tree to get smp_twd clock) forces DT boot to
look up the clock from device tree. It causes the failure below when
twd driver tries to get the clock, and hence kernel has to calibrate the
local timer frequency.smp_twd: clock not found -2
...
Calibrating local timer... 396.13MHz.Fix the regression by providing twd clock lookup from device tree, and
remove the unused twd clk_register_clkdev() call from clock driver.Signed-off-by: Shawn Guo
11 Mar, 2013
1 commit
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We always boot from PLL1, so let's have pll1_sys in the clks_init_on
list to have clk prepare/enable use count match the hardware status,
so that drivers managing pll1_sys like cpufreq can get the use count
right from the start.Reported-by: Dirk Behme
Signed-off-by: Shawn Guo
20 Feb, 2013
1 commit
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This resolves one non-obvious merge conflict between the imx cpuidle
patches and the imx DT changes for 3.9.Conflicts:
arch/arm/mach-imx/mach-imx6q.cSigned-off-by: Arnd Bergmann
10 Feb, 2013
1 commit
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This mxs usbphy is only needs to be on after system boots
up, and software never needs to control it anymore.
Meanwhile, usbphy's parent needs to be notified if usb
is suspend or not. So we design below mxs usbphy usage:- usbphy1_gate and usbphy2_gate:
Their parents are dummy clock, we only needs to enable
it after system boots up.
- usbphy1 and usbphy2
Usage reserved bit for this clock, in that case, the refcount
will be updated, but without hardware changing.Signed-off-by: Peter Chen
Signed-off-by: Shawn Guo
30 Jan, 2013
1 commit
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Add WAIT mode (ARM core clock gating) support to imx6q cpuidle driver.
As WAIT mode is broken on imx6q TO 1.0 and 1.1, it only enables the
support for revision 1.2 with chicken bit set.Signed-off-by: Shawn Guo
29 Jan, 2013
1 commit
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imx6q_clock_map_io() becomes an empty function since imx6q clock driver
is moved to common clock framework. It's used nowhere now. Remove it.Signed-off-by: Shawn Guo