mmc: sdhci-pxa: add platform code for UHS signaling

Marvell controller requires 1.8V bit in UHS control register 2 be set when doing UHS. eMMC does not require 1.8V for DDR. add platform code to handle this. Signed-off-by: Philip Rakity <prakity@marvell.com> Reviewed-by: Arindam Nath <arindam.nath@amd.com> Signed-off-by: Chris Ball <cjb@laptop.org>

mmc: sdhci-pxa: add platform code for UHS signaling
Marvell controller requires 1.8V bit in UHS control register 2 be set when doing UHS. eMMC does not require 1.8V for DDR. add platform code to handle this. Signed-off-by: Philip Rakity <prakity@marvell.com> Reviewed-by: Arindam Nath <arindam.nath@amd.com> Signed-off-by: Chris Ball <cjb@laptop.org>
Philip Rakity · Chris Ball
1 parent 6322cdd0eb
Showing 1 changed file with 41 additions and 0 deletions Side-by-side Diff
drivers/mmc/host/sdhci-pxa.c
@@ -69,7 +69,45 @@
 	}
 }
  
+static int set_uhs_signaling(struct sdhci_host *host, unsigned int uhs)
+{
+	u16 ctrl_2;
+
+	/*
+	 * Set V18_EN -- UHS modes do not work without this.
+	 * does not change signaling voltage
+	 */
+	ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+
+	/* Select Bus Speed Mode for host */
+	ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
+	switch (uhs) {
+	case MMC_TIMING_UHS_SDR12:
+		ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
+		break;
+	case MMC_TIMING_UHS_SDR25:
+		ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
+		break;
+	case MMC_TIMING_UHS_SDR50:
+		ctrl_2 |= SDHCI_CTRL_UHS_SDR50 | SDHCI_CTRL_VDD_180;
+		break;
+	case MMC_TIMING_UHS_SDR104:
+		ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_VDD_180;
+		break;
+	case MMC_TIMING_UHS_DDR50:
+		ctrl_2 |= SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180;
+		break;
+	}
+
+	sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
+	pr_debug("%s:%s uhs = %d, ctrl_2 = %04X\n",
+		__func__, mmc_hostname(host->mmc), uhs, ctrl_2);
+
+	return 0;
+}
+
 static struct sdhci_ops sdhci_pxa_ops = {
+	.set_uhs_signaling = set_uhs_signaling,
 	.set_clock = set_clock,
 };
  
@@ -140,6 +178,9 @@
  
 	if (pdata->quirks)
 		host->quirks |= pdata->quirks;
+
+	/* enable 1/8V DDR capable */
+	host->mmc->caps |= MMC_CAP_1_8V_DDR;
  
 	/* If slot design supports 8 bit data, indicate this to MMC. */
 	if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT)
...	...	@@ -69,7 +69,45 @@
69	69	}
70	70	}
71	71
	72	+static int set_uhs_signaling(struct sdhci_host *host, unsigned int uhs)
	73	+{
	74	+ u16 ctrl_2;
	75	+
	76	+ /*
	77	+ * Set V18_EN -- UHS modes do not work without this.
	78	+ * does not change signaling voltage
	79	+ */
	80	+ ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
	81	+
	82	+ /* Select Bus Speed Mode for host */
	83	+ ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
	84	+ switch (uhs) {
	85	+ case MMC_TIMING_UHS_SDR12:
	86	+ ctrl_2 \|= SDHCI_CTRL_UHS_SDR12;
	87	+ break;
	88	+ case MMC_TIMING_UHS_SDR25:
	89	+ ctrl_2 \|= SDHCI_CTRL_UHS_SDR25;
	90	+ break;
	91	+ case MMC_TIMING_UHS_SDR50:
	92	+ ctrl_2 \|= SDHCI_CTRL_UHS_SDR50 \| SDHCI_CTRL_VDD_180;
	93	+ break;
	94	+ case MMC_TIMING_UHS_SDR104:
	95	+ ctrl_2 \|= SDHCI_CTRL_UHS_SDR104 \| SDHCI_CTRL_VDD_180;
	96	+ break;
	97	+ case MMC_TIMING_UHS_DDR50:
	98	+ ctrl_2 \|= SDHCI_CTRL_UHS_DDR50 \| SDHCI_CTRL_VDD_180;
	99	+ break;
	100	+ }
	101	+
	102	+ sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
	103	+ pr_debug("%s:%s uhs = %d, ctrl_2 = %04X\n",
	104	+ __func__, mmc_hostname(host->mmc), uhs, ctrl_2);
	105	+
	106	+ return 0;
	107	+}
	108	+
72	109	static struct sdhci_ops sdhci_pxa_ops = {
	110	+ .set_uhs_signaling = set_uhs_signaling,
73	111	.set_clock = set_clock,
74	112	};
75	113
...	...	@@ -140,6 +178,9 @@
140	178
141	179	if (pdata->quirks)
142	180	host->quirks \|= pdata->quirks;
	181	+
	182	+ /* enable 1/8V DDR capable */
	183	+ host->mmc->caps \|= MMC_CAP_1_8V_DDR;
143	184
144	185	/* If slot design supports 8 bit data, indicate this to MMC. */
145	186	if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT)