ARM: OMAP: AM33XX: Add OPP table for PG2.1 AM335x

Add OPP table for MPU voltage domain. Changes from PG2.0: 1. The Operating voltage for Nitro Mode is 1.35v 2. PG 2.1 SoC has a new efuse sma register which describes the device's ARM maximum frequency capabilities and package type. Upon parsing this register, the supported maximum frequency is obtained. Note: If this register is not populated or the data is invalid (package type), then we revert back to PG 2.0 OPP list. Signed-off-by: Hebbar Gururaja <gururaja.hebbar@ti.com>

ARM: OMAP: AM33XX: Add OPP table for PG2.1 AM335x
Add OPP table for MPU voltage domain. Changes from PG2.0: 1. The Operating voltage for Nitro Mode is 1.35v 2. PG 2.1 SoC has a new efuse sma register which describes the device's ARM maximum frequency capabilities and package type. Upon parsing this register, the supported maximum frequency is obtained. Note: If this register is not populated or the data is invalid (package type), then we revert back to PG 2.0 OPP list. Signed-off-by: Hebbar Gururaja <gururaja.hebbar@ti.com>
Hebbar Gururaja · Eric Lee
1 parent 506c079b84
Showing 1 changed file with 123 additions and 4 deletions Side-by-side Diff
arch/arm/mach-omap2/opp3xxx_data.c
@@ -18,6 +18,7 @@
  * GNU General Public License for more details.
  */
 #include <linux/module.h>
+#include <linux/io.h>
  
 #include <plat/cpu.h>
  
  
@@ -197,12 +198,72 @@
 				AM33XX_ES2_0_VDD_MPU_OPPNITRO_UV),
 };
  
+#define AM33XX_ES2_1_VDD_MPU_OPP50_UV		950000
+#define AM33XX_ES2_1_VDD_MPU_OPP100_UV		1100000
+#define AM33XX_ES2_1_VDD_MPU_OPPTURBO_UV	1260000
+#define AM33XX_ES2_1_VDD_MPU_OPPNITRO_UV	1350000
+
+#define OPP_50_INDEX		0
+#define OPP_100_INDEX		1
+#define OPP_TURBO_INDEX		2
+#define OPP_NITRO_INDEX		3
+
+
+/* From AM335x TRM, SPRUH73H, Section 9.3.50 */
+#define AM33XX_EFUSE_SMA_OFFSET	0x7fc
+
+/*
+ * Bits [17-16] indicates package type
+ * 00 - reserved
+ * 01 - ZCZ
+ * 10 - ZCE
+ * 11 - reserved
+ */
+#define PACKAGE_TYPE_MASK	0x3
+#define PACKAGE_TYPE_SHFT	16
+
+#define PACKAGE_TYPE_ZCZ	0x1
+#define PACKAGE_TYPE_ZCE	0x2
+
+/*
+ * Bits [12:0] are OPP Disabled bits,
+ * 1 = OPP is disabled and not available,
+ * 0 = OPP available.
+ */
+#define MAX_FREQ_MASK		0x1fff
+#define MAX_FREQ_SHFT		0
+
+#define OPP_50_300MHZ_ZCZ_BIT		4
+#define OPP_100_600MHZ_ZCZ_BIT		6
+#define OPP_TURBO_800MHZ_ZCZ_BIT	8
+#define OPP_NITRO_1GHZ_ZCZ_BIT		9
+
+#define OPP_50_300MHZ_ZCE_BIT		5
+#define OPP_100_600MHZ_ZCE_BIT		6
+
+
+static struct omap_opp_def __initdata am33xx_es2_1_opp_list[] = {
+	/* MPU OPP1 - OPP50 */
+	OPP_INITIALIZER("mpu", false,  300000000,
+				AM33XX_ES2_1_VDD_MPU_OPP50_UV),
+	/* MPU OPP2 - OPP100 */
+	OPP_INITIALIZER("mpu", false,  600000000,
+				AM33XX_ES2_1_VDD_MPU_OPP100_UV),
+	/* MPU OPP3 - OPPTurbo */
+	OPP_INITIALIZER("mpu", false, 800000000,
+				AM33XX_ES2_1_VDD_MPU_OPPTURBO_UV),
+	/* MPU OPP4 - OPPNitro */
+	OPP_INITIALIZER("mpu", false, 1000000000,
+				AM33XX_ES2_1_VDD_MPU_OPPNITRO_UV),
+};
+
 /**
  * omap3_opp_init() - initialize omap3 opp table
  */
 int __init omap3_opp_init(void)
 {
 	int r = -ENODEV;
+	u32 rev, val, package_type, max_freq;
  
 	if (!cpu_is_omap34xx())
 		return r;
  
  
  
@@ -211,16 +272,74 @@
 		r = omap_init_opp_table(omap36xx_opp_def_list,
 			ARRAY_SIZE(omap36xx_opp_def_list));
 	else if (cpu_is_am33xx()) {
-		if (omap_rev() == AM335X_REV_ES1_0)
+		rev = omap_rev();
+		switch (rev) {
+		case AM335X_REV_ES1_0:
 			r = omap_init_opp_table(am33xx_es1_0_opp_def_list,
 				ARRAY_SIZE(am33xx_es1_0_opp_def_list));
-		else
+			break;
+
+		case AM335X_REV_ES2_1:
+			/*
+			 * First read efuse sma reg to detect package type and
+			 * supported frequency
+			 */
+			val =
+			readl(AM33XX_CTRL_REGADDR(AM33XX_EFUSE_SMA_OFFSET));
+
+			package_type = (val >> PACKAGE_TYPE_SHFT) &
+							PACKAGE_TYPE_MASK;
+			max_freq = val & MAX_FREQ_MASK;
+
+			if (package_type == PACKAGE_TYPE_ZCZ) {
+				if (max_freq & OPP_50_300MHZ_ZCZ_BIT)
+					am33xx_es2_1_opp_list[OPP_50_INDEX].
+						default_available = true;
+
+				if (max_freq & OPP_100_600MHZ_ZCZ_BIT)
+					am33xx_es2_1_opp_list[OPP_100_INDEX].
+						default_available = true;
+
+				if (max_freq & OPP_TURBO_800MHZ_ZCZ_BIT)
+					am33xx_es2_1_opp_list[OPP_TURBO_INDEX].
+						default_available = true;
+
+				if (max_freq & OPP_NITRO_1GHZ_ZCZ_BIT)
+					am33xx_es2_1_opp_list[OPP_NITRO_INDEX].
+						default_available = true;
+			} else if (package_type == PACKAGE_TYPE_ZCE) {
+				if (max_freq & OPP_50_300MHZ_ZCE_BIT)
+					am33xx_es2_1_opp_list[OPP_50_INDEX].
+						default_available = true;
+
+				if (max_freq & OPP_100_600MHZ_ZCE_BIT)
+					am33xx_es2_1_opp_list[OPP_100_INDEX].
+						default_available = true;
+			} else {
+				/*
+				* if package type is not detected fall back to
+				* PG 2.0 OPP settings
+				*/
+				r =
+				omap_init_opp_table(am33xx_es2_0_opp_def_list,
+					ARRAY_SIZE(am33xx_es2_0_opp_def_list));
+				break;
+			}
+
+			r = omap_init_opp_table(am33xx_es2_1_opp_list,
+				ARRAY_SIZE(am33xx_es2_1_opp_list));
+			break;
+
+		case AM335X_REV_ES2_0:
+		/* FALLTHROUGH */
+		default:
 			r = omap_init_opp_table(am33xx_es2_0_opp_def_list,
 				ARRAY_SIZE(am33xx_es2_0_opp_def_list));
-	}
-	else
+		}
+	 } else {
 		r = omap_init_opp_table(omap34xx_opp_def_list,
 			ARRAY_SIZE(omap34xx_opp_def_list));
+	}
  
 	return r;
 }
...	...	@@ -18,6 +18,7 @@
18	18	* GNU General Public License for more details.
19	19	*/
20	20	#include <linux/module.h>
	21	+#include <linux/io.h>
21	22
22	23	#include <plat/cpu.h>
23	24
24	25
...	...	@@ -197,12 +198,72 @@
197	198	AM33XX_ES2_0_VDD_MPU_OPPNITRO_UV),
198	199	};
199	200
	201	+#define AM33XX_ES2_1_VDD_MPU_OPP50_UV 950000
	202	+#define AM33XX_ES2_1_VDD_MPU_OPP100_UV 1100000
	203	+#define AM33XX_ES2_1_VDD_MPU_OPPTURBO_UV 1260000
	204	+#define AM33XX_ES2_1_VDD_MPU_OPPNITRO_UV 1350000
	205	+
	206	+#define OPP_50_INDEX 0
	207	+#define OPP_100_INDEX 1
	208	+#define OPP_TURBO_INDEX 2
	209	+#define OPP_NITRO_INDEX 3
	210	+
	211	+
	212	+/* From AM335x TRM, SPRUH73H, Section 9.3.50 */
	213	+#define AM33XX_EFUSE_SMA_OFFSET 0x7fc
	214	+
	215	+/*
	216	+ * Bits [17-16] indicates package type
	217	+ * 00 - reserved
	218	+ * 01 - ZCZ
	219	+ * 10 - ZCE
	220	+ * 11 - reserved
	221	+ */
	222	+#define PACKAGE_TYPE_MASK 0x3
	223	+#define PACKAGE_TYPE_SHFT 16
	224	+
	225	+#define PACKAGE_TYPE_ZCZ 0x1
	226	+#define PACKAGE_TYPE_ZCE 0x2
	227	+
	228	+/*
	229	+ * Bits [12:0] are OPP Disabled bits,
	230	+ * 1 = OPP is disabled and not available,
	231	+ * 0 = OPP available.
	232	+ */
	233	+#define MAX_FREQ_MASK 0x1fff
	234	+#define MAX_FREQ_SHFT 0
	235	+
	236	+#define OPP_50_300MHZ_ZCZ_BIT 4
	237	+#define OPP_100_600MHZ_ZCZ_BIT 6
	238	+#define OPP_TURBO_800MHZ_ZCZ_BIT 8
	239	+#define OPP_NITRO_1GHZ_ZCZ_BIT 9
	240	+
	241	+#define OPP_50_300MHZ_ZCE_BIT 5
	242	+#define OPP_100_600MHZ_ZCE_BIT 6
	243	+
	244	+
	245	+static struct omap_opp_def __initdata am33xx_es2_1_opp_list[] = {
	246	+ /* MPU OPP1 - OPP50 */
	247	+ OPP_INITIALIZER("mpu", false, 300000000,
	248	+ AM33XX_ES2_1_VDD_MPU_OPP50_UV),
	249	+ /* MPU OPP2 - OPP100 */
	250	+ OPP_INITIALIZER("mpu", false, 600000000,
	251	+ AM33XX_ES2_1_VDD_MPU_OPP100_UV),
	252	+ /* MPU OPP3 - OPPTurbo */
	253	+ OPP_INITIALIZER("mpu", false, 800000000,
	254	+ AM33XX_ES2_1_VDD_MPU_OPPTURBO_UV),
	255	+ /* MPU OPP4 - OPPNitro */
	256	+ OPP_INITIALIZER("mpu", false, 1000000000,
	257	+ AM33XX_ES2_1_VDD_MPU_OPPNITRO_UV),
	258	+};
	259	+
200	260	/**
201	261	* omap3_opp_init() - initialize omap3 opp table
202	262	*/
203	263	int __init omap3_opp_init(void)
204	264	{
205	265	int r = -ENODEV;
	266	+ u32 rev, val, package_type, max_freq;
206	267
207	268	if (!cpu_is_omap34xx())
208	269	return r;
209	270
210	271
211	272
...	...	@@ -211,16 +272,74 @@
211	272	r = omap_init_opp_table(omap36xx_opp_def_list,
212	273	ARRAY_SIZE(omap36xx_opp_def_list));
213	274	else if (cpu_is_am33xx()) {
214		- if (omap_rev() == AM335X_REV_ES1_0)
	275	+ rev = omap_rev();
	276	+ switch (rev) {
	277	+ case AM335X_REV_ES1_0:
215	278	r = omap_init_opp_table(am33xx_es1_0_opp_def_list,
216	279	ARRAY_SIZE(am33xx_es1_0_opp_def_list));
217		- else
	280	+ break;
	281	+
	282	+ case AM335X_REV_ES2_1:
	283	+ /*
	284	+ * First read efuse sma reg to detect package type and
	285	+ * supported frequency
	286	+ */
	287	+ val =
	288	+ readl(AM33XX_CTRL_REGADDR(AM33XX_EFUSE_SMA_OFFSET));
	289	+
	290	+ package_type = (val >> PACKAGE_TYPE_SHFT) &
	291	+ PACKAGE_TYPE_MASK;
	292	+ max_freq = val & MAX_FREQ_MASK;
	293	+
	294	+ if (package_type == PACKAGE_TYPE_ZCZ) {
	295	+ if (max_freq & OPP_50_300MHZ_ZCZ_BIT)
	296	+ am33xx_es2_1_opp_list[OPP_50_INDEX].
	297	+ default_available = true;
	298	+
	299	+ if (max_freq & OPP_100_600MHZ_ZCZ_BIT)
	300	+ am33xx_es2_1_opp_list[OPP_100_INDEX].
	301	+ default_available = true;
	302	+
	303	+ if (max_freq & OPP_TURBO_800MHZ_ZCZ_BIT)
	304	+ am33xx_es2_1_opp_list[OPP_TURBO_INDEX].
	305	+ default_available = true;
	306	+
	307	+ if (max_freq & OPP_NITRO_1GHZ_ZCZ_BIT)
	308	+ am33xx_es2_1_opp_list[OPP_NITRO_INDEX].
	309	+ default_available = true;
	310	+ } else if (package_type == PACKAGE_TYPE_ZCE) {
	311	+ if (max_freq & OPP_50_300MHZ_ZCE_BIT)
	312	+ am33xx_es2_1_opp_list[OPP_50_INDEX].
	313	+ default_available = true;
	314	+
	315	+ if (max_freq & OPP_100_600MHZ_ZCE_BIT)
	316	+ am33xx_es2_1_opp_list[OPP_100_INDEX].
	317	+ default_available = true;
	318	+ } else {
	319	+ /*
	320	+ * if package type is not detected fall back to
	321	+ * PG 2.0 OPP settings
	322	+ */
	323	+ r =
	324	+ omap_init_opp_table(am33xx_es2_0_opp_def_list,
	325	+ ARRAY_SIZE(am33xx_es2_0_opp_def_list));
	326	+ break;
	327	+ }
	328	+
	329	+ r = omap_init_opp_table(am33xx_es2_1_opp_list,
	330	+ ARRAY_SIZE(am33xx_es2_1_opp_list));
	331	+ break;
	332	+
	333	+ case AM335X_REV_ES2_0:
	334	+ /* FALLTHROUGH */
	335	+ default:
218	336	r = omap_init_opp_table(am33xx_es2_0_opp_def_list,
219	337	ARRAY_SIZE(am33xx_es2_0_opp_def_list));
220		- }
221		- else
	338	+ }
	339	+ } else {
222	340	r = omap_init_opp_table(omap34xx_opp_def_list,
223	341	ARRAY_SIZE(omap34xx_opp_def_list));
	342	+ }
224	343
225	344	return r;
226	345	}