30 Nov, 2011
15 commits
-
Signed-off-by: Vaibhav Bedia
-
Replace clk_set_rate with omap_device_scale
in target function. This provides the ability
to change voltage as well as frequency as per
OPP tablesSigned-off-by: Afzal Mohammed
-
dvfs.h is required by omap cpufreq driver that
lives in drivers folder, so move it to plat/
directory. Also move voltage.h, vc.h & vp.h
similarly to have clean header file inclusionsSigned-off-by: Afzal Mohammed
-
We use a single frequency table for multiple CPUs. But, with
OMAP4, since we have multiple CPUs, the cpu_init call for CPU1
causes freq_table previously allocated for CPU0 to be overwritten.
In addition, we dont free the table on exit path.We solve this by maintaining an atomic type counter to ensure
just a single table exists at a given time.Signed-off-by: Nishanth Menon
Signed-off-by: Kevin Hilman
[vaibhav.bedia@ti.com: Pull in for AM33xx]
Signed-off-by: Vaibhav Bedia -
Release the mpu_clk in fail paths.
Reported-by: Todd Poynor
Signed-off-by: Nishanth Menon
Signed-off-by: Kevin Hilman
[vaibhav.bedia@ti.com: Pull in for AM33xx]
Signed-off-by: Vaibhav Bedia -
OMAP2 is the only family using clk_[init|exit]_cpufreq_table, however,
the cpufreq code does not currently use clk_init_cpufreq_table. As a
result, it is unusuable for OMAP2 and only usable only on platforms
using OPP library.Remove the unbalanced clk_exit_cpufreq_table(). Any platforms where
OPPs are not availble will fail on init because a freq table will not
be properly initialized.Signed-off-by: Nishanth Menon
[khilman@ti.com: changelog edits, and graceful failure mode changes]
Signed-off-by: Kevin Hilman
[vaibhav.bedia@ti.com: Pull in for AM33xx]
Signed-off-by: Vaibhav Bedia -
OMAP2+ all have frequency tables, hence the hacks we had for older
silicon do not need to be carried forward. As part of this change,
use cpufreq_frequency_table_target to find the best match for
frequency requested.Signed-off-by: Nishanth Menon
Signed-off-by: Kevin Hilman
[vaibhav.bedia@ti.com: Pull in for AM33xx]
Signed-off-by: Vaibhav Bedia -
if we do not have mpu_dev we normally fail in cpu_init. It is better
to fail driver registration if the devices are not available.Signed-off-by: Nishanth Menon
Signed-off-by: Kevin Hilman
[vaibhav.bedia@ti.com: Pull in for AM33xx]
Signed-off-by: Vaibhav Bedia
[afzal@ti.com: use 'omap_device_get_by_hwmod_name' for 'mpu_dev']
Signed-off-by: Afzal Mohammed -
Clk name does'nt need to dynamically detected during clk init.
move them off to driver initialization, if we dont have a clk name,
there is no point in registering the driver anyways. The actual clk
get and put is left at cpu_init and exit functions.Signed-off-by: Nishanth Menon
Signed-off-by: Kevin Hilman
[vaibhav.bedia@ti.com: Pull in for AM33xx]
Signed-off-by: Vaibhav Bedia -
Sometimes, bootloaders starts up with a frequency which is not
in the OPP table. At cpu_init, policy->cur contains the frequency
we pick at boot. It is possible that system might have fixed
it's boot frequency later on as part of power initialization.
After this condition, the first call to omap_target results in the
following:omap_getspeed(actual device frequency) != policy->cur(frequency that
cpufreq thinks that the system is at), and it is possible that
freqs.old == freqs.new (because the governor requested a scale down).We exit without triggering the notifiers in the current code, which
does'nt let code which depends on cpufreq_notify_transition to have
accurate information as to what the system frequency is.Instead, we do a normal transition if policy->cur is wrong, then,
freqs.old will be the actual cpu frequency, freqs.new will be the
actual new cpu frequency and all required notifiers have the accurate
information.Acked-by: Nishanth Menon
Signed-off-by: Colin Cross
Signed-off-by: Kevin Hilman
[vaibhav.bedia@ti.com: Pull in for AM33xx]
Signed-off-by: Vaibhav Bedia -
Enable all CPUs in the shared policy in the CPU init callback.
Otherwise, the governor CPUFREQ_GOV_START event is invoked with
a policy that only includes the first CPU, leaving other CPUs
uninitialized by the governor.Signed-off-by: Todd Poynor
Acked-by: Santosh Shilimkar
Signed-off-by: Kevin Hilman
[vaibhav.bedia@ti.com: Pull in for AM33xx]
Signed-off-by: Vaibhav Bedia -
On OMAP SMP configuartion, both processors share the voltage
and clock. So both CPUs needs to be scaled together and hence
needs software co-ordination.Also, update lpj with reference value to avoid progressive error.
Adjust _both_ the per-cpu loops_per_jiffy and global lpj. Calibrate
them with with reference to the initial values to avoid a
progressively bigger and bigger error in the value over time.While at this, re-use the notifiers for UP/SMP since on UP machine or
UP_ON_SMP policy->cpus mask would contain only the boot CPU.Based on initial SMP support by Santosh Shilimkar.
Signed-off-by: Russell King
Signed-off-by: Santosh Shilimkar
[khilman@ti.com: due to overlap/rework, combined original Santosh patch
and Russell's rework]
Signed-off-by: Kevin Hilman
[vaibhav.bedia@ti.com: Pull in for AM33xx]
Signed-off-by: Vaibhav Bedia -
Move OMAP cpufreq driver from arch/arm/mach-omap2 into
drivers/cpufreq, along with a few cleanups:- generalize support for better handling of different SoCs in the OMAP
- use OPP layer instead of OMAP clock internals for frequency table initSigned-off-by: Santosh Shilimkar
[khilman@ti.com: move to drivers]
Signed-off-by: Kevin Hilman
[vaibhav.bedia@ti.com: Pull in for AM33xx]
Signed-off-by: Vaibhav Bedia -
DMA support for MCSPI transfer enabled and removed unwanted flag
dma_not_enabled as DMA feature is enabled in omap2_mcspi.Signed-off-by: Philip, Avinash
-
Support for DMA transmission on MCSPI added.
1. MCSPI TX and RX registers are not 256-bit aligned address, as
required for Constant address mode in DAM and SAM in EDMA, causing EDMA
error generation condition. With this commit SAM and DAM are set to
Increment address mode.
2. SPI uses EDMA AB synchronized mode for transmission and EDMA A
synchronized mode for reception, which can be used to handle large chunk
of data above 64KB with single EDMA completion interrupt.Signed-off-by: Philip, Avinash
28 Nov, 2011
12 commits
-
14 bytes of ECC is provided for every 512 byte even though 13 byte is the
actual requirement. This is to synchronize the ECC layout with U-boot.
Extra byte is cleared to 0.Signed-off-by: Philip, Avinash
Signed-off-by: Hebbar, Gururaja -
1. BCH8 ECC support is enabled.
2. Support for BCH8 error correction using ELM module is added.
3. ECC positions updated for BCH8 in synchronized with U-boot.
4. Corrected GPMC settings for BCH8 ECC scheme.Signed-off-by: Philip, Avinash
Signed-off-by: Hebbar, Gururaja -
GPL module license is added to remove warnings on inserting as module.
Signed-off-by: Philip, Avinash
Signed-off-by: Hebbar, Gururaja -
bch error correction (t=4 and t=8) for 512 bytes support added.
Tested in omap-3630 es-1.1 silicon.Need to select the bch-ecc from board file. E.g.
arch/arm/mach-omap2/board-flash.c: board_nand_init()
board_nand_data.ecc_opt = OMAP_ECC_BCH4_CODE_HWThis patch has dependency on -
http://www.mail-archive.com/linux-omap@vger.kernel.org/msg42658.htmlSigned-off-by: Parth Mauria Saxena
Signed-off-by: Sukumar Ghorai
Signed-off-by: Sriramakrishnan A G
Signed-off-by: Abhilash K V
Signed-off-by: Philip, Avinash
Signed-off-by: Hebbar, Gururaja -
Count of selector voltage is required for regulator_set_voltage
to work via set_voltage_sel. VDD1/2 currently have it as zero,
so regulator_set_voltage won't work for VDD1/2.
Update count (n_voltages) for VDD1/2.Output Voltage = (step value * 12.5 mV + 562.5 mV) * gain
With above expr, number of voltages that can be selected is
step value count * gain countconstant for gain count will be called VDD1_2_NUM_VOLT_COARSE
existing constant for step value count is VDD1_2_NUM_VOLTS,
use VDD1_2_NUM_VOLT_FINE instead to make clear that step value
is not the only component in deciding selectable voltage countSigned-off-by: Afzal Mohammed
-
TPS65910 can be used even if interrupt is unused.
Hence let probe succeed in case interrupt can't be
configured and let Kernel only to complain about itSigned-off-by: Afzal Mohammed
-
Create an array of fixed size for the platform to pass regulator
initalization data through.Passing an array of pointers to init data also allows more flexible
definition of init data as well as prevents reading past the end of the
array should the platform define an incorrectly sized array.Signed-off-by: Kyle Manna
-
Move the regulator defintions to the header so that platform board file
can use them to configure specific regulators.Signed-off-by: Kyle Manna
-
The tps65910.h file depends on linux/gpio.h. Move the include from the
source file to the tps65910.h header file.Signed-off-by: Kyle Manna
-
Fix a typo that clobbers other interrupts in an unobvious way.
Signed-off-by: Kyle Manna
-
Attempt to read the first register of the device, if there is no
device return -ENODEVSigned-off-by: Kyle Manna
Signed-off-by: Afzal Mohammed -
This patch adds support for lis33ldlh digital accelerometer to the
lis3lv02d driver family. Adds ID field for detecting the lis33ldlh
module, based on this ID field lis3lv02d driver will export the
lis33ldlh module functionality.Also exports g_range parameter to user space for run-time value
change. User must give 2/4/8 value depends on requirement.Signed-off-by: Anil Kumar Ch
24 Nov, 2011
1 commit
-
This patch is added to remove unwanted dmtimer re enabling
code after reseting timer status register. Also, some additional
cleanup is done in this patch.Signed-off-by: Chandan Nath
23 Nov, 2011
3 commits
-
CPSW module includes an interrupt pacing block that can
be programmed to throttle the rate at which interrupts are
generated. This patch implements interrupt pacing logic that can
be controlled through the ethtool interface(only rx_coalesce_usecs
param is honored)Signed-off-by: Chandan Nath
-
This patch is added to route CPSW interrupts through ICSS module.
CPSW CPSW_RX and CPSW_TX interrupts are not directly used from CPSW
and instead they are routed through Timer module. This is done as an
software workaround for enabling interrupt pacing feature. As interrupt
Pacing works on C0_RX_PULSE interrupt connection to A8 INTC, which is
not connected to Cortex A8 interrupt controller directly due to hw issue,
it prevents interrupt pacing to work in AM33xx EVM. Therefore, Timer
capture module is used to pickup these interrupts and routed to A8 INTC.Signed-off-by: Chandan Nath
Signed-off-by: Afzal Mohammed -
Channel status was wrongly set to FREE while it should be done just before
calling dma_completion.Merge to:
commit 26be0d11e79728339e4e627dc27d6894bcb5de82
usb: musb: cppi41dma: yield cpu in tx fifo empty workqueue
22 Nov, 2011
2 commits
-
Added AM33XX dependency for UIO_PRUSS driver to build in Kconfig. ICSS memory map base and length were added in am33xx.h Other PRU specific resources like ICSS IRQs for AM33XX, uio_pruss driver register were added to devices.c
Signed-off-by: Amit Shah
-
Disable SRAM export in UIO till consolidated SRAM support available for AM33XX
Signed-off-by: Amit Shah
21 Nov, 2011
1 commit
-
This patch cleans-up the driver based on internal lpr review comments.
Also modified the code which can be fit for both alpha and beta am335x
EVM's.Signed-off-by: Anil Kumar Ch
18 Nov, 2011
2 commits
-
cpu_is_omap34xx() is true for am335x. However, not all gpio code
is common between omap34xx & am335x.Signed-off-by: Hebbar, Gururaja
-
Unable to flush musb Tx endpoint fifo during disconnect while i/o
in progress. The workaround is to set only fifoflush bit and clear
other bits in tx-csr register.Signed-off-by: Ravi B
17 Nov, 2011
2 commits
-
Tx FIFO empty reschedules the workqueue without cpu yield and that
would can cause high cpu uses. Fix by using cond_resched(). -
merge to cc42fb36 (musb: Add workqueue for URB giveback)
the giveback workqueue has only succesfull completed
URBs, it is safe to giveback URBs without taking
musb spinlocks.Signed-off-by: Ravi B
Signed-off-by: Ajay Kumar Gupta
16 Nov, 2011
1 commit
-
Bosch D_CAN controller is a full-CAN implementation which is compliant
to CAN protocol version 2.0 part A and B. Bosch D_CAN user manual can be
obtained from:http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/can/d_can_users_manual_111.pdf
This patch adds the support for this controller.
The following are the design choices made while writing the controller
driver:
1. Interface Register set IF1 has be used for transmit and IF2 is used for
receive message objects.
2. Out of the total Message objects available, half of it are kept aside for RX
purposes and the rest for TX purposes.
3. NAPI implementation is such that both the TX and RX paths functions
in polling mode.This patch adds the dcan driver support to am335x chip.
Signed-off-by: Anil Kumar Ch
15 Nov, 2011
1 commit
-
This patch adds support for pressure measurement configurations
on TSC. Along with X and Y co-ordinates pressure is also reported
to the sub-system.Signed-off-by: Patil, Rachna
