14 Dec, 2020
12 commits
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This reverts commit 3d65a3518149d33e289b5417d7a4a175b4ef0737.
The i.MX8MP A0 silicon will not be supported, so revert the SW workaround
for A0 to provide more robust & clean code support for i.MX8MP.Signed-off-by: Jacky Bai
Tested-by: Jian Li -
…rq numbers for imx8mp"
This reverts commit 2d0e3291c68c3229a7e4d45dede51ebcbac7dea2.
The i.MX8MP A0 silicon will not be supported, so revert the SW workaround
for A0 to provide more robust & clean code support for i.MX8MP.Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Tested-by: Jian Li <jian.li@nxp.com> -
Since commit 5cebfd2d47c214 "arm64: Kill __smp_cross_call and co",
the workaround for ERR11171 for i.MX8MQ needs a different approach.
Remove all the smp_cross_call references and make sure the workaround
is happening only on 8MQ and if the TF-A supports it.Signed-off-by: Abel Vesa
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For i.MX8MP, the max irq numbers is 160, so correct the max irq number
in GPCv2 driver to Fix the IRQ number get failure issue if requested
irq number > 128.Signed-off-by: Jacky Bai
Reviewed-by: Anson Huang
(cherry picked from commit 2d0e3291c68c3229a7e4d45dede51ebcbac7dea2) -
Add the wait mode workaround on i.MX8MP. it is just
a provisional patch for Alpha release. it will be
dropped in the future. As all the changes in this
patch need to be revered for that time, just including
all the changes of dts & driver in one patch to make
it more easier to track all the changes.Coresight probe has some conlict with the IPI workaround.
it is meaningless to put effort on resolve such conflict,
and Coresight is not an must feature for Alpha release,
disable the Coresight support directly.Signed-off-by: Jacky Bai
Reviewed-by: Anson Huang
(cherry picked from commit 3d65a3518149d33e289b5417d7a4a175b4ef0737) -
Fix below build error when CONFIG_SMP is NOT selected:
drivers/irqchip/irq-imx-gpcv2.c: In function "imx_gpcv2_wake_request_fixup":
drivers/irqchip/irq-imx-gpcv2.c:123:2: error: implicit declaration of function
"set_smp_cross_call" [-Werror=implicit-function-declaration]
123 | set_smp_cross_call(imx_gpcv2_raise_softirq);
| ^~~~~~~~~~~~~~~~~~
cc1: some warnings being treated as errors
make[3]: *** [drivers/irqchip/irq-imx-gpcv2.o] Error 1Signed-off-by: Anson Huang
Reviewed-by: Robin Gong -
As of now, if somebody masks/unmasks any irq while the set_wake goes
to TF-A, the masking/unmasking might be overwritten. So add new irq_chip ops
that implement the masking, unmasking, set_wake and set_affinity and each
calls into TF-A internally. Also add the ERR11171 knob that allows
initializing the core wake-up workaround by registering our own
smp_cross_call funtion and call the old one from within. The ERR11171 knob
gets enabled by default if the machine is i.MX8MQ.Signed-off-by: Abel Vesa
Reviewed-by: Jacky Bai -
Fix below build warning when built with imx_v6_v7_defconfig:
drivers/irqchip/irq-imx-gpcv2.c: In function 'imx_gpcv2_irq_set_wake':
drivers/irqchip/irq-imx-gpcv2.c:129:23: warning: unused variable 'res' [-Wunused-variable]
struct arm_smccc_res res;
^Signed-off-by: Anson Huang
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The wakeup irq info need to be provided to ATF side, then
ATF side can config the correct wakeup IRQ when entering
suspend.Signed-off-by: Jacky Bai
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Fix below build error when built with imx_v6_v7_defconfig:
drivers/irqchip/irq-imx-gpcv2.c: In function 'imx_gpcv2_wake_request_fixup':
drivers/irqchip/irq-imx-gpcv2.c:112:28: error: '__smp_cross_call' undeclared (first use in this function); did you mean 'set_smp_cross_call'?
__gic_v3_smp_cross_call = __smp_cross_call;
^~~~~~~~~~~~~~~~
set_smp_cross_call
drivers/irqchip/irq-imx-gpcv2.c:112:28: note: each undeclared identifier is reported only once for each function it appears inSigned-off-by: Anson Huang
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Not all EL3 have the FSL_SIP_CONFIG_GPC_CORE_WAKE, therefore disable
the cpuidle to avoid all the cores going to sleep ending up with a
hang. This allows all the EL3 implementations to work with i.MX8MQ
even if they do not support core wake-up through GPC as a workaround.Signed-off-by: Abel Vesa
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i.MX8MQ is missing the wake_request signals from GIC to GPCv2. This indirectly
breaks cpuidle support due to inability to wake target cores on IPIs.Here is the link to the errata (see e11171):
https://www.nxp.com/docs/en/errata/IMX8MDQLQ_0N14W.pdf
Now, in order to fix this, we can trigger IRQ 32 (hwirq 0) to all the cores by
setting 12th bit in IOMUX_GPR1 register. In order to control the target cores
only, that is, not waking up all the cores every time, we can unmask/mask the
IRQ 32 in the first GPC IMR register. So basically we can leave the IOMUX_GPR1
12th bit always set and just play with the masking and unmasking the IRO 32 for
each independent core.Since EL3 is the one that deals with powering down/up the cores, and since the
cores wake up in EL3, EL3 should be the one to control the IMRs in this case.
This implies we need to get into EL3 on every IPI to do the unmasking, leaving
the masking to be done on the power-up sequence by the core itself.In order to be able to get into EL3 on each IPI, we 'hijack' the registered smp
cross call handler, in this case the gic_raise_softirq which is registered by
the irq-gic-v3 driver and register our own handler instead. This new handler is
basically a wrapper over the hijacked handler plus the call into EL3.To get into EL3, we use a custom vendor SIP id added just for this purpose.
All of this is conditional for i.MX8MQ only.
Signed-off-by: Abel Vesa
24 Aug, 2020
1 commit
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Replace the existing /* fall through */ comments and its variants with
the new pseudo-keyword macro fallthrough[1]. Also, remove unnecessary
fall-through markings when it is the case.[1] https://www.kernel.org/doc/html/v5.7/process/deprecated.html?highlight=fallthrough#implicit-switch-case-fall-through
Signed-off-by: Gustavo A. R. Silva
02 Aug, 2019
1 commit
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…az/arm-platforms into irq/urgent
Pull irqchip fixes from Marc Zyngier:
A small bunch of fixes from the irqchip department:
- Fix a couple of UAF on error paths (RZA1, GICv3 ITS)
- Fix iMX GPCv2 trigger setting
- Add missing of_node_put on error path in MBIGEN
- Add another bunch of /* fall-through */ to silence warnings
26 Jul, 2019
1 commit
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The GPCv2 is a stacked IRQ controller below the ARM GIC. It doesn't
care about the IRQ type itself, but needs to forward the type to the
parent IRQ controller, so this one can be configured correctly.Signed-off-by: Lucas Stach
Signed-off-by: Marc Zyngier
19 Jun, 2019
1 commit
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Based on 2 normalized pattern(s):
this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license version 2 as
published by the free software foundationthis program is free software you can redistribute it and or modify
it under the terms of the gnu general public license version 2 as
published by the free software foundation #extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-only
has been chosen to replace the boilerplate/reference in 4122 file(s).
Signed-off-by: Thomas Gleixner
Reviewed-by: Enrico Weigelt
Reviewed-by: Kate Stewart
Reviewed-by: Allison Randal
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de
Signed-off-by: Greg Kroah-Hartman
18 Dec, 2018
1 commit
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The GPC node on i.MX8MQ can not claim to be compatible with the i.MX7D
GPC, as the power gating part has some significant differences. Thus we
can not rely on the irqchip being probed with the old compatible.Signed-off-by: Lucas Stach
Signed-off-by: Marc Zyngier
15 Dec, 2018
1 commit
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The -Wimplicit-fallthrough option requires that the /* fall through */
comment is placed in the 'case' statement that falls through, rather
than in the following one. Case seems to matter as well.Reported-by: Stephen Rothwell
Signed-off-by: Marc Zyngier
13 Dec, 2018
5 commits
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Add code needed to support i.MX8MQ.
Cc: Thomas Gleixner
Cc: Jason Cooper
Cc: Marc Zyngier
Cc: cphealy@gmail.com
Cc: l.stach@pengutronix.de
Cc: Leonard Crestez
Cc: "A.s. Dong"
Cc: Richard Zhu
Cc: linux-imx@nxp.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Andrey Smirnov
Signed-off-by: Marc Zyngier -
Make error messages more consistent by making sure each starts with
"%pOF:".Cc: Thomas Gleixner
Cc: Jason Cooper
Cc: Marc Zyngier
Cc: cphealy@gmail.com
Cc: l.stach@pengutronix.de
Cc: Leonard Crestez
Cc: "A.s. Dong"
Cc: Richard Zhu
Cc: linux-imx@nxp.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Andrey Smirnov
Signed-off-by: Marc Zyngier -
Convert all instances of 1 << x to BIT(x) for consistency with other
kernel code.Cc: Thomas Gleixner
Cc: Jason Cooper
Cc: Marc Zyngier
Cc: cphealy@gmail.com
Cc: l.stach@pengutronix.de
Cc: Leonard Crestez
Cc: "A.s. Dong"
Cc: Richard Zhu
Cc: linux-imx@nxp.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Andrey Smirnov
Signed-off-by: Marc Zyngier -
Move identical offset calculation code into a small helper function
and make use of it in the rest of the code.Cc: Thomas Gleixner
Cc: Jason Cooper
Cc: Marc Zyngier
Cc: cphealy@gmail.com
Cc: l.stach@pengutronix.de
Cc: Leonard Crestez
Cc: "A.s. Dong"
Cc: Richard Zhu
Cc: linux-imx@nxp.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Andrey Smirnov
Signed-off-by: Marc Zyngier -
Varaible 'reg' in imx_gpcv2_irq_set_wake() has no users. Remove it.
Cc: Thomas Gleixner
Cc: Jason Cooper
Cc: Marc Zyngier
Cc: cphealy@gmail.com
Cc: l.stach@pengutronix.de
Cc: Leonard Crestez
Cc: "A.s. Dong"
Cc: Richard Zhu
Cc: linux-imx@nxp.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Andrey Smirnov
Signed-off-by: Marc Zyngier
11 Mar, 2018
1 commit
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imx_gpcv2_get_wakeup_source() is not used anywhere, so remove it.
This fixes the following sparse warning:
drivers/irqchip/irq-imx-gpcv2.c:34:5: warning: symbol 'imx_gpcv2_get_wakeup_source' was not declared. Should it be static?
Fixes: e324c4dc4a59 ("irqchip/imx-gpcv2: IMX GPCv2 driver for wakeup sources")
Signed-off-by: Fabio Estevam
Signed-off-by: Marc Zyngier
23 Aug, 2017
1 commit
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Now that we have a custom printf format specifier, convert users of
full_name to use %pOF instead. This is preparation to remove storing
of the full path string for each node.Cc: Thomas Gleixner
Cc: Jason Cooper
Cc: Lee Jones
Cc: Stefan Wahren
Cc: Florian Fainelli
Cc: Ray Jui
Cc: Scott Branden
Cc: bcm-kernel-feedback-list@broadcom.com
Cc: Sylvain Lemieux
Cc: Maxime Coquelin
Cc: Chen-Yu Tsai
Cc: Thierry Reding
Cc: Jonathan Hunter
Cc: Michal Simek
Cc: "Sören Brinkmann"
Cc: linux-rpi-kernel@lists.infradead.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-mediatek@lists.infradead.org
Cc: linux-tegra@vger.kernel.org
Acked-by: Eric Anholt
Acked-by: Baruch Siach
Acked-by: Vladimir Zapolskiy
Acked-by: Matthias Brugger
Acked-by: Alexandre Torgue
Acked-by: Maxime Ripard
Signed-off-by: Rob Herring
Signed-off-by: Marc Zyngier
22 Jun, 2017
1 commit
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struct irq_domain_ops is not modified, so it can be made const.
Signed-off-by: Tobias Klauser
Signed-off-by: Marc Zyngier
20 Apr, 2017
1 commit
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Pick up upstream fixes to avoid conflicts with pending patches.
14 Apr, 2017
1 commit
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The raw_spinlock in the IMX GPCV2 interupt chip is not initialized before
usage. That results in a lockdep splat:INFO: trying to register non-static key.
the code is fine but needs lockdep annotation.
turning off the locking correctness validator.Add the missing raw_spin_lock_init() to the setup code.
Fixes: e324c4dc4a59 ("irqchip/imx-gpcv2: IMX GPCv2 driver for wakeup sources")
Signed-off-by: Tyler Baker
Reviewed-by: Fabio Estevam
Cc: jason@lakedaemon.net
Cc: marc.zyngier@arm.com
Cc: shawnguo@kernel.org
Cc: andrew.smirnov@gmail.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: stable@vger.kernel.org
Link: http://lkml.kernel.org/r/20170413222731.5917-1-tyler.baker@linaro.org
Signed-off-by: Thomas Gleixner
12 Apr, 2017
1 commit
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Clear OF_POPULATED flag, so that GPC power domain driver[1] can be
bound to "gpc" node as well.[1] https://lkml.org/lkml/2017/3/28/835
Cc: yurovsky@gmail.com
Cc: Thomas Gleixner
Cc: Jason Cooper
Signed-off-by: Andrey Smirnov
Signed-off-by: Marc Zyngier
14 Oct, 2015
2 commits
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Since we now have a generic data structure to express an
interrupt specifier, convert all hierarchical irqchips that
are OF based to use a fwnode_handle as part of their alloc
and xlate (which becomes translate) callbacks.As most of these drivers have dependencies (they exchange IRQ
specifiers), change them all in a single, massive patch...Signed-off-by: Marc Zyngier
Reviewed-and-tested-by: Hanjun Guo
Tested-by: Lorenzo Pieralisi
Cc:
Cc: Tomasz Nowicki
Cc: Suravee Suthikulpanit
Cc: Graeme Gregory
Cc: Jake Oshins
Cc: Jiang Liu
Cc: Jason Cooper
Cc: Rafael J. Wysocki
Link: http://lkml.kernel.org/r/1444737105-31573-6-git-send-email-marc.zyngier@arm.com
Signed-off-by: Thomas Gleixner -
The struct irq_domain contains a "struct device_node *" field
(of_node) that is almost the only link between the irqdomain
and the device tree infrastructure.In order to prepare for the removal of that field, convert all
users to use irq_domain_get_of_node() instead.Signed-off-by: Marc Zyngier
Reviewed-and-tested-by: Hanjun Guo
Tested-by: Lorenzo Pieralisi
Cc:
Cc: Tomasz Nowicki
Cc: Suravee Suthikulpanit
Cc: Graeme Gregory
Cc: Jake Oshins
Cc: Jiang Liu
Cc: Jason Cooper
Cc: Rafael J. Wysocki
Link: http://lkml.kernel.org/r/1444737105-31573-2-git-send-email-marc.zyngier@arm.com
Signed-off-by: Thomas Gleixner
25 Aug, 2015
1 commit
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IMX7D contains a new version of GPC IP block (GPCv2). It has two major
functions: power management and wakeup source management.When the system is in WFI (wait for interrupt) mode, the GPC block
will be the first block on the platform to be activated and signaled.In normal wait mode during cpu idle, the system can be woken up by any
enabled interrupts. In standby or suspend mode, the system can only be
wokem up by the pre-defined wakeup sources.Based-on-patch-by: Anson Huang
Signed-off-by: Shenwei Wang
Cc:
Cc:
Cc:
Link: http://lkml.kernel.org/r/1440443055-7291-1-git-send-email-shenwei.wang@freescale.com
Signed-off-by: Thomas Gleixner
