Eric Lee / smarc-fsl-linux-kernel

01 Apr, 2015

2 commits

  • f8fd30ebd   MIPS: Hibernate: Restructure files and functions ... Browse Code »

    This patch has no functional changes, it just to keep the assembler
    code to a minimum. Files and functions naming is borrowed from X86.

    Signed-off-by: Huacai Chen
    Cc: Steven J. Hill
    Cc: linux-mips@linux-mips.org
    Cc: Fuxin Zhang
    Cc: Zhangjin Wu
    Patchwork: https://patchwork.linux-mips.org/patch/9616/
    Signed-off-by: Ralf Baechle

    Huacai Chen
     
  • 2a21dc7c1   MIPS: Hibernate: flush TLB entries earlier ... Browse Code »

    We found that TLB mismatch not only happens after kernel resume, but
    also happens during snapshot restore. So move it to the beginning of
    swsusp_arch_suspend().

    Signed-off-by: Huacai Chen
    Cc:
    Cc: Steven J. Hill
    Cc: linux-mips@linux-mips.org
    Cc: Fuxin Zhang
    Cc: Zhangjin Wu
    Cc: stable@vger.kernel.org
    Patchwork: https://patchwork.linux-mips.org/patch/9621/
    Signed-off-by: Ralf Baechle

    Huacai Chen
     

10 Oct, 2014

1 commit

  • 7f8998c7a   nosave: consolidate __nosave_{begin,end} in <asm/sections.h> ... Browse Code »

    The different architectures used their own (and different) declarations:

    extern __visible const void __nosave_begin, __nosave_end;
    extern const void __nosave_begin, __nosave_end;
    extern long __nosave_begin, __nosave_end;

    Consolidate them using the first variant in .

    Signed-off-by: Geert Uytterhoeven
    Cc: Russell King
    Cc: Ralf Baechle
    Cc: Benjamin Herrenschmidt
    Cc: Martin Schwidefsky
    Cc: "David S. Miller"
    Cc: Guan Xuetao
    Cc: Thomas Gleixner
    Cc: Ingo Molnar
    Cc: "H. Peter Anvin"
    Signed-off-by: Andrew Morton
    Signed-off-by: Linus Torvalds

    Geert Uytterhoeven
     

31 Mar, 2014

1 commit

  • c14af233f   MIPS: Hibernate: Flush TLB entries in swsusp_arch_resume() ... Browse Code »

    The original MIPS hibernate code flushes cache and TLB entries in
    swsusp_arch_resume(). But they are removed in Commit 44eeab67416711
    (MIPS: Hibernation: Remove SMP TLB and cacheflushing code.). A cross-
    CPU flush is surely unnecessary because all but the local CPU have
    already been disabled. But a local flush (at least the TLB flush) is
    needed. When we do hibernation on Loongson-3 with an E1000E NIC, it is
    very easy to produce a kernel panic (kernel page fault, or unaligned
    access). The root cause is E1000E driver use vzalloc_node() to allocate
    pages, the stale TLB entries of the booting kernel will be misused by
    the resumed target kernel.

    Signed-off-by: Huacai Chen
    Cc: John Crispin
    Cc: Steven J. Hill
    Cc: Aurelien Jarno
    Cc: linux-mips@linux-mips.org
    Cc: Fuxin Zhang
    Cc: Zhangjin Wu
    Cc: stable@vger.kernel.org
    Patchwork: https://patchwork.linux-mips.org/patch/6643/
    Signed-off-by: Ralf Baechle

    Huacai Chen
     

01 Feb, 2013

1 commit

  • 703422879   MIPS: Whitespace cleanup. ... Browse Code »

    Having received another series of whitespace patches I decided to do this
    once and for all rather than dealing with this kind of patches trickling
    in forever.

    Signed-off-by: Ralf Baechle

    Ralf Baechle
     

29 Dec, 2012

1 commit

11 May, 2011

1 commit

  • f850548ef   MIPS: Hibernation: Fixes for PAGE_SIZE >= 64kb ... Browse Code »

    PAGE_SIZE >= 64kb (1 << 16) is too big to be the immediate of the
    addiu/daddiu instruction, so, use addu/daddu instruction instead.

    The following compiling error is fixed:

    AS arch/mips/power/hibernate.o
    arch/mips/power/hibernate.S: Assembler messages:
    arch/mips/power/hibernate.S:38: Error: expression out of range
    make[2]: *** [arch/mips/power/hibernate.o] Error 1
    make[1]: *** [arch/mips/power] Error 2

    Reported-by: Roman Mamedov
    Signed-off-by: Wu Zhangjin
    To: linux-mips@linux-mips.org
    Patchwork: https://patchwork.linux-mips.org/patch/2313/
    Signed-off-by: Ralf Baechle

    Wu Zhangjin
     

27 Feb, 2010

1 commit

18 Sep, 2009

1 commit

  • a0b54e256   MIPS: Use PAGE_SIZE in assembly instead of _PAGE_SIZE. ... Browse Code »

    Now that PAGE_SIZE is available to assembly directly, there is no need
    to separately expose it as _PAGE_SIZE through asm-offsets.

    In addition, remove _PAGE_SHIFT from asm-offsets, since it was never
    needed, and is not used anywhere.

    Signed-off-by: Nelson Elhage
    Signed-off-by: Tim Abbott
    Signed-off-by: Ralf Baechle

    Nelson Elhage
     

25 Jun, 2009

1 commit

  • 44eeab674   MIPS: Hibernation: Remove SMP TLB and cacheflushing code. ... Browse Code »

    We can't perform any flushes on SMP from swsusp_arch_resume because
    interrupts are disabled. A cross-CPU flush is unnecessary anyway
    because all but the local CPU have already been disabled. A local
    flush is not needed either because we didn't change any mappings. So
    just delete the code.

    Signed-off-by: Ralf Baechle

    Ralf Baechle
     

17 Jun, 2009

1 commit

  • 363c55cae   MIPS: Add hibernation support ... Browse Code »

    [Ralf: SMP support requires CPU hotplugging which MIPS currently doesn't
    support. As implemented in this patch cache and tlb flushing will also be
    invoked with interrupts disabled so smp_call_function() will blow up in
    charming ways. So limit to !SMP.]

    Reviewed-by: Pavel Machek
    Reviewed-by: Yan Hua
    Reviewed-by: Arnaud Patard
    Reviewed-by: Atsushi Nemoto
    Signed-off-by: Wu Zhangjin
    Signed-off-by: Hu Hongbing
    Signed-off-by: Ralf Baechle

    Wu Zhangjin