Blame view
include/configs/socfpga_cyclone5.h
6.57 KB
777544085 ARM: Add Altera S... |
1 2 3 |
/* * Copyright (C) 2012 Altera Corporation <www.altera.com> * |
1a4596601 Add GPL-2.0+ SPDX... |
4 |
* SPDX-License-Identifier: GPL-2.0+ |
777544085 ARM: Add Altera S... |
5 6 7 8 9 |
*/ #ifndef __CONFIG_H #define __CONFIG_H #include <asm/arch/socfpga_base_addrs.h> |
5d649d2b0 socfpga: Adding S... |
10 |
#include "../../board/altera/socfpga/pinmux_config.h" |
dc4d4aa14 socfpga: Adding S... |
11 |
#include "../../board/altera/socfpga/iocsr_config.h" |
ddfeb0aaf socfpga: Adding C... |
12 |
#include "../../board/altera/socfpga/pll_config.h" |
777544085 ARM: Add Altera S... |
13 14 15 16 |
/* * High level configuration */ |
31ad864e4 socfpga: Adding c... |
17 18 |
/* Virtual target or real hardware */ #define CONFIG_SOCFPGA_VIRTUAL_TARGET |
777544085 ARM: Add Altera S... |
19 20 |
#define CONFIG_ARMV7 |
777544085 ARM: Add Altera S... |
21 22 23 24 25 26 |
#define CONFIG_SYS_DCACHE_OFF #undef CONFIG_USE_IRQ #define CONFIG_MISC_INIT_R #define CONFIG_SINGLE_BOOTLOADER #define CONFIG_SOCFPGA |
31ad864e4 socfpga: Adding c... |
27 28 |
/* base address for .text section */ #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET |
777544085 ARM: Add Altera S... |
29 |
#define CONFIG_SYS_TEXT_BASE 0x08000040 |
31ad864e4 socfpga: Adding c... |
30 31 32 |
#else #define CONFIG_SYS_TEXT_BASE 0x01000040 #endif |
777544085 ARM: Add Altera S... |
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 |
#define CONFIG_SYS_LOAD_ADDR 0x7fc0 /* Console I/O Buffer Size */ #define CONFIG_SYS_CBSIZE 256 /* Monitor Command Prompt */ #define CONFIG_SYS_PROMPT "SOCFPGA_CYCLONE5 # " #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) /* * Display CPU and Board Info */ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO /* * Enable early stage initialization at C environment */ #define CONFIG_BOARD_EARLY_INIT_F /* flat device tree */ #define CONFIG_OF_LIBFDT /* skip updating the FDT blob */ #define CONFIG_FDT_BLOB_SKIP_UPDATE /* Initial Memory map size for Linux, minus 4k alignment for DFT blob */ #define CONFIG_SYS_BOOTMAPSZ ((256*1024*1024) - (4*1024)) #define CONFIG_SPL_RAM_DEVICE |
e05e5de7f arm: move C runti... |
61 |
#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR |
777544085 ARM: Add Altera S... |
62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 |
#define CONFIG_SYS_SPL_MALLOC_START ((unsigned long) (&__malloc_start)) #define CONFIG_SYS_SPL_MALLOC_SIZE (&__malloc_end - &__malloc_start) /* * Memory allocation (MALLOC) */ /* Room required on the stack for the environment data */ #define CONFIG_ENV_SIZE 1024 /* Size of DRAM reserved for malloc() use */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) /* SP location before relocation, must use scratch RAM */ #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 /* Reserving 0x100 space at back of scratch RAM for debug info */ #define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - 0x100) /* Stack pointer prior relocation, must situated at on-chip RAM */ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - \ GENERATED_GBL_DATA_SIZE) /* * Command line configuration. */ #define CONFIG_SYS_NO_FLASH #include <config_cmd_default.h> /* FAT file system support */ #define CONFIG_CMD_FAT /* * Misc */ #define CONFIG_DOS_PARTITION 1 #ifdef CONFIG_SPL_BUILD #undef CONFIG_PARTITIONS #endif /* * Environment setup */ /* Delay before automatically booting the default image */ #define CONFIG_BOOTDELAY 3 /* Enable auto completion of commands using TAB */ #define CONFIG_AUTO_COMPLETE /* use "hush" command parser */ #define CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " #define CONFIG_CMD_RUN #define CONFIG_BOOTCOMMAND "run ramboot" /* * arguments passed to the bootm command. The value of * CONFIG_BOOTARGS goes into the environment value "bootargs". * Do note the value will overide also the chosen node in FDT blob. */ #define CONFIG_BOOTARGS "console=ttyS0,57600,mem=256M@0x0" #define CONFIG_EXTRA_ENV_SETTINGS \ "verify=n\0" \ |
5368c55d4 COMMON: Use __str... |
125 |
"loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ |
777544085 ARM: Add Altera S... |
126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 |
"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \ "bootm ${loadaddr} - ${fdt_addr}\0" \ "bootimage=uImage\0" \ "fdt_addr=100\0" \ "fsloadcmd=ext2load\0" \ "bootm ${loadaddr} - ${fdt_addr}\0" \ "qspiroot=/dev/mtdblock0\0" \ "qspirootfstype=jffs2\0" \ "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ " root=${qspiroot} rw rootfstype=${qspirootfstype};"\ "bootm ${loadaddr} - ${fdt_addr}\0" /* using environment setting for stdin, stdout, stderr */ #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Enable the call to overwrite_console() */ #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE /* Enable overwrite of previous console environment settings */ #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE /* max number of command args */ #define CONFIG_SYS_MAXARGS 16 /* * Hardware drivers */ /* * SDRAM Memory Map */ /* We have 1 bank of DRAM */ #define CONFIG_NR_DRAM_BANKS 1 /* SDRAM Bank #1 */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* SDRAM memory size */ |
31ad864e4 socfpga: Adding c... |
161 |
#define PHYS_SDRAM_1_SIZE 0x40000000 |
777544085 ARM: Add Altera S... |
162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 |
#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_MEMTEST_START 0x00000000 #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE /* * NS16550 Configuration */ #define UART0_BASE SOCFPGA_UART0_ADDRESS #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE -4 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK #define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550_COM1 UART0_BASE |
777544085 ARM: Add Altera S... |
177 |
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} |
31ad864e4 socfpga: Adding c... |
178 179 180 181 182 183 |
#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET #define V_NS16550_CLK 1000000 #else #define V_NS16550_CLK 100000000 #endif #define CONFIG_BAUDRATE 115200 |
777544085 ARM: Add Altera S... |
184 185 186 187 188 189 190 191 192 193 194 195 |
/* * FLASH */ #define CONFIG_SYS_NO_FLASH /* * L4 OSC1 Timer 0 */ /* This timer use eosc1 where the clock frequency is fixed * throughout any condition */ #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS |
777544085 ARM: Add Altera S... |
196 197 |
/* reload value when timer count to zero */ #define TIMER_LOAD_VAL 0xFFFFFFFF |
31ad864e4 socfpga: Adding c... |
198 |
/* Timer info */ |
31ad864e4 socfpga: Adding c... |
199 |
#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET |
23ab7ee0f ARM: socfpga: con... |
200 |
#define CONFIG_SYS_TIMER_RATE 2400000 |
31ad864e4 socfpga: Adding c... |
201 |
#else |
23ab7ee0f ARM: socfpga: con... |
202 |
#define CONFIG_SYS_TIMER_RATE 25000000 |
31ad864e4 socfpga: Adding c... |
203 |
#endif |
2cc0ea72e socfpga: timer ac... |
204 |
#define CONFIG_SYS_TIMER_COUNTS_DOWN |
23ab7ee0f ARM: socfpga: con... |
205 |
#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) |
777544085 ARM: Add Altera S... |
206 207 208 209 |
#define CONFIG_ENV_IS_NOWHERE /* |
05b884b5c socfpga: Adding D... |
210 211 212 213 214 215 216 217 218 219 220 |
* L4 Watchdog */ #define CONFIG_HW_WATCHDOG #define CONFIG_HW_WATCHDOG_TIMEOUT_MS 2000 #define CONFIG_DESIGNWARE_WATCHDOG #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS /* Clocks source frequency to watchdog timer */ #define CONFIG_DW_WDT_CLOCK_KHZ 25000 /* |
777544085 ARM: Add Altera S... |
221 222 223 224 |
* SPL "Second Program Loader" aka Initial Software */ /* Enable building of SPL globally */ |
777544085 ARM: Add Altera S... |
225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 |
#define CONFIG_SPL_FRAMEWORK /* TEXT_BASE for linking the SPL binary */ #define CONFIG_SPL_TEXT_BASE 0xFFFF0000 /* Stack size for SPL */ #define CONFIG_SPL_STACK_SIZE (4 * 1024) /* MALLOC size for SPL */ #define CONFIG_SPL_MALLOC_SIZE (5 * 1024) #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_BOARD_INIT #define CHUNKSZ_CRC32 (1 * 1024) #define CONFIG_CRC32_VERIFY /* Linker script for SPL */ #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds" /* Support for common/libcommon.o in SPL binary */ #define CONFIG_SPL_LIBCOMMON_SUPPORT /* Support for lib/libgeneric.o in SPL binary */ #define CONFIG_SPL_LIBGENERIC_SUPPORT |
05b884b5c socfpga: Adding D... |
250 251 |
/* Support for watchdog */ #define CONFIG_SPL_WATCHDOG_SUPPORT |
777544085 ARM: Add Altera S... |
252 |
#endif /* __CONFIG_H */ |