/*
   * Copyright 2018 NXP
   *
   * SPDX-License-Identifier:	GPL-2.0+
   */
  
  #include <common.h>
  #include <malloc.h>
  #include <errno.h>
  #include <asm/io.h>
  #include <miiphy.h>
  #include <netdev.h>
  #include <asm/mach-imx/iomux-v3.h>
  #include <asm-generic/gpio.h>
  #include <fsl_esdhc.h>
  #include <mmc.h>
  #include <asm/arch/imx8mm_pins.h>
  #include <asm/arch/sys_proto.h>
  #include <asm/mach-imx/gpio.h>
  #include <asm/mach-imx/mxc_i2c.h>
  #include <asm/arch/clock.h>
  #include <spl.h>
  #include <asm/mach-imx/dma.h>
  #include <power/pmic.h>
  #include <power/bd71837.h>

  #include "../common/tcpc.h"

  #include <usb.h>

  #include <sec_mipi_dsim.h>
  #include <imx_mipi_dsi_bridge.h>
  #include <mipi_dsi_panel.h>
  #include <asm/mach-imx/video.h>

  
  DECLARE_GLOBAL_DATA_PTR;
  
  #define UART_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_FSEL1)

  #define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)

  
  static iomux_v3_cfg_t const uart_pads[] = {
  	IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  	IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  };

  static iomux_v3_cfg_t const wdog_pads[] = {
  	IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
  };

  #ifdef CONFIG_FSL_FSPI
  #define QSPI_PAD_CTRL	(PAD_CTL_DSE2 | PAD_CTL_HYS)
  static iomux_v3_cfg_t const qspi_pads[] = {
  	IMX8MM_PAD_NAND_ALE_QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL | PAD_CTL_PE | PAD_CTL_PUE),
  	IMX8MM_PAD_NAND_CE0_B_QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL),
  
  	IMX8MM_PAD_NAND_DATA00_QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
  	IMX8MM_PAD_NAND_DATA01_QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
  	IMX8MM_PAD_NAND_DATA02_QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
  	IMX8MM_PAD_NAND_DATA03_QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
  };
  
  int board_qspi_init(void)
  {
  	imx_iomux_v3_setup_multiple_pads(qspi_pads, ARRAY_SIZE(qspi_pads));
  
  	set_clk_qspi();
  
  	return 0;
  }
  #endif
  
  #ifdef CONFIG_MXC_SPI
  #define SPI_PAD_CTRL	(PAD_CTL_DSE2 | PAD_CTL_HYS)
  static iomux_v3_cfg_t const ecspi1_pads[] = {
  	IMX8MM_PAD_ECSPI1_SCLK_ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
  	IMX8MM_PAD_ECSPI1_MOSI_ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
  	IMX8MM_PAD_ECSPI1_MISO_ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
  	IMX8MM_PAD_ECSPI1_SS0_GPIO5_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL),
  };
  
  static iomux_v3_cfg_t const ecspi2_pads[] = {
  	IMX8MM_PAD_ECSPI2_SCLK_ECSPI2_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
  	IMX8MM_PAD_ECSPI2_MOSI_ECSPI2_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
  	IMX8MM_PAD_ECSPI2_MISO_ECSPI2_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
  	IMX8MM_PAD_ECSPI2_SS0_GPIO5_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
  };
  
  static void setup_spi(void)
  {
  	imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
  	imx_iomux_v3_setup_multiple_pads(ecspi2_pads, ARRAY_SIZE(ecspi2_pads));
  	gpio_request(IMX_GPIO_NR(5, 9), "ECSPI1 CS");
  	gpio_request(IMX_GPIO_NR(5, 13), "ECSPI2 CS");
  }
  
  int board_spi_cs_gpio(unsigned bus, unsigned cs)
  {
  	if (bus == 0)
  		return IMX_GPIO_NR(5, 9);
  	else
  		return IMX_GPIO_NR(5, 13);
  }
  #endif
  
  #ifdef CONFIG_NAND_MXS
  #define NAND_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_FSEL2 | PAD_CTL_HYS)
  #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL2 | PAD_CTL_PUE)
  static iomux_v3_cfg_t const gpmi_pads[] = {
  	IMX8MM_PAD_NAND_ALE_RAWNAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
  	IMX8MM_PAD_NAND_CE0_B_RAWNAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  	IMX8MM_PAD_NAND_CLE_RAWNAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL),
  	IMX8MM_PAD_NAND_DATA00_RAWNAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  	IMX8MM_PAD_NAND_DATA01_RAWNAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  	IMX8MM_PAD_NAND_DATA02_RAWNAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  	IMX8MM_PAD_NAND_DATA03_RAWNAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  	IMX8MM_PAD_NAND_DATA04_RAWNAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  	IMX8MM_PAD_NAND_DATA05_RAWNAND_DATA05	| MUX_PAD_CTRL(NAND_PAD_CTRL),
  	IMX8MM_PAD_NAND_DATA06_RAWNAND_DATA06	| MUX_PAD_CTRL(NAND_PAD_CTRL),
  	IMX8MM_PAD_NAND_DATA07_RAWNAND_DATA07	| MUX_PAD_CTRL(NAND_PAD_CTRL),
  	IMX8MM_PAD_NAND_RE_B_RAWNAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  	IMX8MM_PAD_NAND_READY_B_RAWNAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL),
  	IMX8MM_PAD_NAND_WE_B_RAWNAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  	IMX8MM_PAD_NAND_WP_B_RAWNAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  };
  
  static void setup_gpmi_nand(void)
  {
  	imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));

  }
  #endif
  
  int board_early_init_f(void)
  {

  	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
  
  	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
  
  	set_wdog_reset(wdog);

  	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));

  #ifdef CONFIG_NAND_MXS
  	setup_gpmi_nand(); /* SPL will call the board_early_init_f */
  #endif

  	return 0;
  }
  
  #ifdef CONFIG_BOARD_POSTCLK_INIT
  int board_postclk_init(void)
  {
  	/* TODO */
  	return 0;
  }
  #endif
  
  int dram_init(void)
  {

  	/* rom_pointer[1] contains the size of TEE occupies */
  	if (rom_pointer[1])
  		gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1];
  	else
  		gd->ram_size = PHYS_SDRAM_SIZE;

  
  	return 0;
  }
  
  #ifdef CONFIG_OF_BOARD_SETUP
  int ft_board_setup(void *blob, bd_t *bd)
  {
  	return 0;
  }
  #endif
  
  #ifdef CONFIG_FEC_MXC
  #define FEC_RST_PAD IMX_GPIO_NR(4, 22)
  static iomux_v3_cfg_t const fec1_rst_pads[] = {
  	IMX8MM_PAD_SAI2_RXC_GPIO4_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
  };
  
  static void setup_iomux_fec(void)
  {
  	imx_iomux_v3_setup_multiple_pads(fec1_rst_pads,
  					 ARRAY_SIZE(fec1_rst_pads));
  
  	gpio_request(FEC_RST_PAD, "fec1_rst");
  	gpio_direction_output(FEC_RST_PAD, 0);
  	udelay(500);
  	gpio_direction_output(FEC_RST_PAD, 1);
  }
  
  static int setup_fec(void)
  {
  	struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
  		= (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
  
  	setup_iomux_fec();
  
  	/* Use 125M anatop REF_CLK1 for ENET1, not from external */
  	clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
  			IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT, 0);
  	return set_clk_enet(ENET_125MHZ);
  }
  
  int board_phy_config(struct phy_device *phydev)
  {
  	/* enable rgmii rxc skew and phy mode select to RGMII copper */
  	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
  	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
  
  	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
  	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
  	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
  	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
  
  	if (phydev->drv->config)
  		phydev->drv->config(phydev);
  	return 0;
  }
  #endif

  #ifdef CONFIG_USB_TCPC
  struct tcpc_port port1;
  struct tcpc_port port2;

  static int setup_pd_switch(uint8_t i2c_bus, uint8_t addr)
  {
  	struct udevice *bus;
  	struct udevice *i2c_dev = NULL;
  	int ret;
  	uint8_t valb;
  
  	ret = uclass_get_device_by_seq(UCLASS_I2C, i2c_bus, &bus);
  	if (ret) {
  		printf("%s: Can't find bus
  ", __func__);
  		return -EINVAL;
  	}
  
  	ret = dm_i2c_probe(bus, addr, 0, &i2c_dev);
  	if (ret) {
  		printf("%s: Can't find device id=0x%x
  ",
  			__func__, addr);
  		return -ENODEV;
  	}
  
  	ret = dm_i2c_read(i2c_dev, 0xB, &valb, 1);
  	if (ret) {
  		printf("%s dm_i2c_read failed, err %d
  ", __func__, ret);
  		return -EIO;
  	}
  	valb |= 0x4; /* Set DB_EXIT to exit dead battery mode */
  	ret = dm_i2c_write(i2c_dev, 0xB, (const uint8_t *)&valb, 1);
  	if (ret) {
  		printf("%s dm_i2c_write failed, err %d
  ", __func__, ret);
  		return -EIO;
  	}
  
  	/* Set OVP threshold to 23V */
  	valb = 0x6;
  	ret = dm_i2c_write(i2c_dev, 0x8, (const uint8_t *)&valb, 1);
  	if (ret) {
  		printf("%s dm_i2c_write failed, err %d
  ", __func__, ret);
  		return -EIO;
  	}
  
  	return 0;
  }

  int pd_switch_snk_enable(struct tcpc_port *port)

  {

  	if (port == &port1) {
  		debug("Setup pd switch on port 1
  ");
  		return setup_pd_switch(1, 0x72);
  	} else if (port == &port2) {
  		debug("Setup pd switch on port 2
  ");
  		return setup_pd_switch(1, 0x73);
  	} else
  		return -EINVAL;
  }

  struct tcpc_port_config port1_config = {
  	.i2c_bus = 1, /*i2c2*/
  	.addr = 0x50,
  	.port_type = TYPEC_PORT_UFP,
  	.max_snk_mv = 5000,
  	.max_snk_ma = 3000,
  	.max_snk_mw = 40000,
  	.op_snk_mv = 9000,
  	.switch_setup_func = &pd_switch_snk_enable,
  };

  struct tcpc_port_config port2_config = {
  	.i2c_bus = 1, /*i2c2*/
  	.addr = 0x52,
  	.port_type = TYPEC_PORT_UFP,
  	.max_snk_mv = 5000,
  	.max_snk_ma = 3000,
  	.max_snk_mw = 40000,
  	.op_snk_mv = 9000,
  	.switch_setup_func = &pd_switch_snk_enable,
  };
  
  static int setup_typec(void)
  {
  	int ret;

  	debug("tcpc_init port 2
  ");

  	ret = tcpc_init(&port2, port2_config, NULL);
  	if (ret) {
  		printf("%s: tcpc port2 init failed, err=%d
  ",
  		       __func__, ret);
  	} else if (tcpc_pd_sink_check_charging(&port2)) {
  		/* Disable PD for USB1, since USB2 has priority */
  		port1_config.disable_pd = true;
  		printf("Power supply on USB2
  ");
  	}

  	debug("tcpc_init port 1
  ");

  	ret = tcpc_init(&port1, port1_config, NULL);
  	if (ret) {
  		printf("%s: tcpc port1 init failed, err=%d
  ",
  		       __func__, ret);
  	} else {
  		if (!port1_config.disable_pd)
  			printf("Power supply on USB1
  ");
  		return ret;
  	}
  
  	return ret;
  }

  
  int board_usb_init(int index, enum usb_init_type init)
  {
  	int ret = 0;

  	struct tcpc_port *port_ptr;

  	debug("board_usb_init %d, type %d
  ", index, init);

  	if (index == 0)
  		port_ptr = &port1;
  	else
  		port_ptr = &port2;
  
  	imx8m_usb_power(index, true);
  
  	if (init == USB_INIT_HOST)
  		tcpc_setup_dfp_mode(port_ptr);
  	else
  		tcpc_setup_ufp_mode(port_ptr);

  
  	return ret;
  }
  
  int board_usb_cleanup(int index, enum usb_init_type init)
  {
  	int ret = 0;

  	debug("board_usb_cleanup %d, type %d
  ", index, init);

  	if (init == USB_INIT_HOST) {
  		if (index == 0)
  			ret = tcpc_disable_src_vbus(&port1);
  		else
  			ret = tcpc_disable_src_vbus(&port2);
  	}
  
  	imx8m_usb_power(index, false);
  	return ret;
  }

  
  int board_ehci_usb_phy_mode(struct udevice *dev)
  {
  	int ret = 0;
  	enum typec_cc_polarity pol;
  	enum typec_cc_state state;
  	struct tcpc_port *port_ptr;
  
  	if (dev->seq == 0)
  		port_ptr = &port1;
  	else
  		port_ptr = &port2;
  
  	tcpc_setup_ufp_mode(port_ptr);
  
  	ret = tcpc_get_cc_status(port_ptr, &pol, &state);
  	if (!ret) {
  		if (state == TYPEC_STATE_SRC_RD_RA || state == TYPEC_STATE_SRC_RD)
  			return USB_INIT_HOST;
  	}
  
  	return USB_INIT_DEVICE;
  }

  #endif

  int board_init(void)
  {

  #ifdef CONFIG_USB_TCPC
  	setup_typec();
  #endif

  #ifdef CONFIG_MXC_SPI
  	setup_spi();
  #endif
  
  #ifdef CONFIG_FEC_MXC
  	setup_fec();
  #endif
  
  #ifdef CONFIG_FSL_FSPI
  	board_qspi_init();
  #endif

  	return 0;
  }
  
  int board_mmc_get_env_dev(int devno)
  {
  	return devno - 1;
  }
  
  int mmc_map_to_kernel_blk(int devno)
  {
  	return devno + 1;
  }

  #ifdef CONFIG_VIDEO_MXS
  
  #define ADV7535_MAIN 0x3d
  #define ADV7535_DSI_CEC 0x3c
  
  static const struct sec_mipi_dsim_plat_data imx8mm_mipi_dsim_plat_data = {
  	.version	= 0x1060200,
  	.max_data_lanes = 4,
  	.max_data_rate  = 1500000000ULL,
  	.reg_base = MIPI_DSI_BASE_ADDR,
  	.gpr_base = CSI_BASE_ADDR + 0x8000,
  };
  
  static int adv7535_i2c_reg_write(struct udevice *dev, uint addr, uint mask, uint data)
  {
  	uint8_t valb;
  	int err;
  
  	if (mask != 0xff) {
  		err = dm_i2c_read(dev, addr, &valb, 1);
  		if (err)
  			return err;
  
  		valb &= ~mask;
  		valb |= data;
  	} else {
  		valb = data;
  	}
  
  	err = dm_i2c_write(dev, addr, &valb, 1);
  	return err;
  }
  
  static int adv7535_i2c_reg_read(struct udevice *dev, uint8_t addr, uint8_t *data)
  {
  	uint8_t valb;
  	int err;
  
  	err = dm_i2c_read(dev, addr, &valb, 1);
  	if (err)
  		return err;
  
  	*data = (int)valb;
  	return 0;
  }
  
  static void adv7535_init(void)
  {
  	struct udevice *bus, *main_dev, *cec_dev;
  	int i2c_bus = 1;
  	int ret;
  	uint8_t val;
  
  	ret = uclass_get_device_by_seq(UCLASS_I2C, i2c_bus, &bus);
  	if (ret) {
  		printf("%s: No bus %d
  ", __func__, i2c_bus);
  		return;
  	}
  
  	ret = dm_i2c_probe(bus, ADV7535_MAIN, 0, &main_dev);
  	if (ret) {
  		printf("%s: Can't find device id=0x%x, on bus %d
  ",
  			__func__, ADV7535_MAIN, i2c_bus);
  		return;
  	}
  
  	ret = dm_i2c_probe(bus, ADV7535_DSI_CEC, 0, &cec_dev);
  	if (ret) {
  		printf("%s: Can't find device id=0x%x, on bus %d
  ",
  			__func__, ADV7535_MAIN, i2c_bus);
  		return;
  	}
  
  	adv7535_i2c_reg_read(main_dev, 0x00, &val);
  	debug("Chip revision: 0x%x (expected: 0x14)
  ", val);
  	adv7535_i2c_reg_read(cec_dev, 0x00, &val);
  	debug("Chip ID MSB: 0x%x (expected: 0x75)
  ", val);
  	adv7535_i2c_reg_read(cec_dev, 0x01, &val);
  	debug("Chip ID LSB: 0x%x (expected: 0x33)
  ", val);
  
  	/* Power */
  	adv7535_i2c_reg_write(main_dev, 0x41, 0xff, 0x10);
  	/* Initialisation (Fixed) Registers */
  	adv7535_i2c_reg_write(main_dev, 0x16, 0xff, 0x20);
  	adv7535_i2c_reg_write(main_dev, 0x9A, 0xff, 0xE0);
  	adv7535_i2c_reg_write(main_dev, 0xBA, 0xff, 0x70);
  	adv7535_i2c_reg_write(main_dev, 0xDE, 0xff, 0x82);
  	adv7535_i2c_reg_write(main_dev, 0xE4, 0xff, 0x40);
  	adv7535_i2c_reg_write(main_dev, 0xE5, 0xff, 0x80);
  	adv7535_i2c_reg_write(cec_dev, 0x15, 0xff, 0xD0);
  	adv7535_i2c_reg_write(cec_dev, 0x17, 0xff, 0xD0);
  	adv7535_i2c_reg_write(cec_dev, 0x24, 0xff, 0x20);
  	adv7535_i2c_reg_write(cec_dev, 0x57, 0xff, 0x11);
  	/* 4 x DSI Lanes */
  	adv7535_i2c_reg_write(cec_dev, 0x1C, 0xff, 0x40);
  
  	/* DSI Pixel Clock Divider */
  	adv7535_i2c_reg_write(cec_dev, 0x16, 0xff, 0x18);
  
  	/* Enable Internal Timing Generator */
  	adv7535_i2c_reg_write(cec_dev, 0x27, 0xff, 0xCB);
  	/* 1920 x 1080p 60Hz */
  	adv7535_i2c_reg_write(cec_dev, 0x28, 0xff, 0x89); /* total width */
  	adv7535_i2c_reg_write(cec_dev, 0x29, 0xff, 0x80); /* total width */
  	adv7535_i2c_reg_write(cec_dev, 0x2A, 0xff, 0x02); /* hsync */
  	adv7535_i2c_reg_write(cec_dev, 0x2B, 0xff, 0xC0); /* hsync */
  	adv7535_i2c_reg_write(cec_dev, 0x2C, 0xff, 0x05); /* hfp */
  	adv7535_i2c_reg_write(cec_dev, 0x2D, 0xff, 0x80); /* hfp */
  	adv7535_i2c_reg_write(cec_dev, 0x2E, 0xff, 0x09); /* hbp */
  	adv7535_i2c_reg_write(cec_dev, 0x2F, 0xff, 0x40); /* hbp */
  
  	adv7535_i2c_reg_write(cec_dev, 0x30, 0xff, 0x46); /* total height */
  	adv7535_i2c_reg_write(cec_dev, 0x31, 0xff, 0x50); /* total height */
  	adv7535_i2c_reg_write(cec_dev, 0x32, 0xff, 0x00); /* vsync */
  	adv7535_i2c_reg_write(cec_dev, 0x33, 0xff, 0x50); /* vsync */
  	adv7535_i2c_reg_write(cec_dev, 0x34, 0xff, 0x00); /* vfp */
  	adv7535_i2c_reg_write(cec_dev, 0x35, 0xff, 0x40); /* vfp */
  	adv7535_i2c_reg_write(cec_dev, 0x36, 0xff, 0x02); /* vbp */
  	adv7535_i2c_reg_write(cec_dev, 0x37, 0xff, 0x40); /* vbp */
  
  	/* Reset Internal Timing Generator */
  	adv7535_i2c_reg_write(cec_dev, 0x27, 0xff, 0xCB);
  	adv7535_i2c_reg_write(cec_dev, 0x27, 0xff, 0x8B);
  	adv7535_i2c_reg_write(cec_dev, 0x27, 0xff, 0xCB);
  
  	/* HDMI Output */
  	adv7535_i2c_reg_write(main_dev, 0xAF, 0xff, 0x16);
  	/* AVI Infoframe - RGB - 16-9 Aspect Ratio */
  	adv7535_i2c_reg_write(main_dev, 0x55, 0xff, 0x02);
  	adv7535_i2c_reg_write(main_dev, 0x56, 0xff, 0x0);
  
  	/*  GC Packet Enable */
  	adv7535_i2c_reg_write(main_dev, 0x40, 0xff, 0x0);
  	/*  GC Colour Depth - 24 Bit */
  	adv7535_i2c_reg_write(main_dev, 0x4C, 0xff, 0x0);
  	/*  Down Dither Output Colour Depth - 8 Bit (default) */
  	adv7535_i2c_reg_write(main_dev, 0x49, 0xff, 0x00);
  
  	/* set low refresh 1080p30 */
  	adv7535_i2c_reg_write(main_dev, 0x4A, 0xff, 0x80); /*should be 0x80 for 1080p60 and 0x8c for 1080p30*/
  
  	/* HDMI Output Enable */
  	adv7535_i2c_reg_write(cec_dev, 0xbe, 0xff, 0x3c);
  	adv7535_i2c_reg_write(cec_dev, 0x03, 0xff, 0x89);
  }
  
  #define DISPLAY_MIX_SFT_RSTN_CSR		0x00
  #define DISPLAY_MIX_CLK_EN_CSR		0x04
  
     /* 'DISP_MIX_SFT_RSTN_CSR' bit fields */
  #define BUS_RSTN_BLK_SYNC_SFT_EN	BIT(6)
  
     /* 'DISP_MIX_CLK_EN_CSR' bit fields */
  #define LCDIF_PIXEL_CLK_SFT_EN		BIT(7)
  #define LCDIF_APB_CLK_SFT_EN		BIT(6)
  
  void disp_mix_bus_rstn_reset(ulong gpr_base, bool reset)
  {
  	if (!reset)
  		/* release reset */
  		setbits_le32(gpr_base + DISPLAY_MIX_SFT_RSTN_CSR, BUS_RSTN_BLK_SYNC_SFT_EN);
  	else
  		/* hold reset */
  		clrbits_le32(gpr_base + DISPLAY_MIX_SFT_RSTN_CSR, BUS_RSTN_BLK_SYNC_SFT_EN);
  }
  
  void disp_mix_lcdif_clks_enable(ulong gpr_base, bool enable)
  {
  	if (enable)
  		/* enable lcdif clks */
  		setbits_le32(gpr_base + DISPLAY_MIX_CLK_EN_CSR, LCDIF_PIXEL_CLK_SFT_EN | LCDIF_APB_CLK_SFT_EN);
  	else
  		/* disable lcdif clks */
  		clrbits_le32(gpr_base + DISPLAY_MIX_CLK_EN_CSR, LCDIF_PIXEL_CLK_SFT_EN | LCDIF_APB_CLK_SFT_EN);
  }
  
  struct mipi_dsi_client_dev adv7535_dev = {
  	.channel	= 0,
  	.lanes = 4,
  	.format  = MIPI_DSI_FMT_RGB888,
  	.mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
  			  MIPI_DSI_MODE_EOT_PACKET | MIPI_DSI_MODE_VIDEO_HSE,
  	.name = "ADV7535",
  };
  
  struct mipi_dsi_client_dev rm67191_dev = {
  	.channel	= 0,
  	.lanes = 4,
  	.format  = MIPI_DSI_FMT_RGB888,
  	.mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
  			  MIPI_DSI_MODE_EOT_PACKET | MIPI_DSI_MODE_VIDEO_HSE,
  };

  #define FSL_SIP_GPC			0xC2000000
  #define FSL_SIP_CONFIG_GPC_PM_DOMAIN	0x3
  #define DISPMIX				9
  #define MIPI				10

  void do_enable_mipi2hdmi(struct display_info_t const *dev)
  {
  	gpio_request(IMX_GPIO_NR(1, 8), "DSI EN");
  	gpio_direction_output(IMX_GPIO_NR(1, 8), 1);
  
  	/* ADV7353 initialization */
  	adv7535_init();

  	/* enable the dispmix & mipi phy power domain */
  	call_imx_sip(FSL_SIP_GPC, FSL_SIP_CONFIG_GPC_PM_DOMAIN, DISPMIX, true, 0);
  	call_imx_sip(FSL_SIP_GPC, FSL_SIP_CONFIG_GPC_PM_DOMAIN, MIPI, true, 0);

  	/* Put lcdif out of reset */
  	disp_mix_bus_rstn_reset(imx8mm_mipi_dsim_plat_data.gpr_base, false);
  	disp_mix_lcdif_clks_enable(imx8mm_mipi_dsim_plat_data.gpr_base, true);
  
  	/* Setup mipi dsim */
  	sec_mipi_dsim_setup(&imx8mm_mipi_dsim_plat_data);
  	imx_mipi_dsi_bridge_attach(&adv7535_dev); /* attach adv7535 device */
  }
  
  void do_enable_mipi_led(struct display_info_t const *dev)
  {
  	gpio_request(IMX_GPIO_NR(1, 8), "DSI EN");
  	gpio_direction_output(IMX_GPIO_NR(1, 8), 0);
  	mdelay(100);
  	gpio_direction_output(IMX_GPIO_NR(1, 8), 1);

  	/* enable the dispmix & mipi phy power domain */
  	call_imx_sip(FSL_SIP_GPC, FSL_SIP_CONFIG_GPC_PM_DOMAIN, DISPMIX, true, 0);
  	call_imx_sip(FSL_SIP_GPC, FSL_SIP_CONFIG_GPC_PM_DOMAIN, MIPI, true, 0);

  	/* Put lcdif out of reset */
  	disp_mix_bus_rstn_reset(imx8mm_mipi_dsim_plat_data.gpr_base, false);
  	disp_mix_lcdif_clks_enable(imx8mm_mipi_dsim_plat_data.gpr_base, true);
  
  	/* Setup mipi dsim */
  	sec_mipi_dsim_setup(&imx8mm_mipi_dsim_plat_data);
  
  	rm67191_init();
  	rm67191_dev.name = displays[1].mode.name;
  	imx_mipi_dsi_bridge_attach(&rm67191_dev); /* attach rm67191 device */
  }

  void board_quiesce_devices(void)
  {
  	gpio_request(IMX_GPIO_NR(1, 8), "DSI EN");
  	gpio_direction_output(IMX_GPIO_NR(1, 8), 0);
  }

  struct display_info_t const displays[] = {{
  	.bus = LCDIF_BASE_ADDR,
  	.addr = 0,
  	.pixfmt = 24,
  	.detect = NULL,
  	.enable	= do_enable_mipi2hdmi,
  	.mode	= {
  		.name			= "MIPI2HDMI",
  		.refresh		= 60,
  		.xres			= 1920,
  		.yres			= 1080,
  		.pixclock		= 6734, /* 148500000 */
  		.left_margin	= 148,
  		.right_margin	= 88,
  		.upper_margin	= 36,
  		.lower_margin	= 4,
  		.hsync_len		= 44,
  		.vsync_len		= 5,
  		.sync			= FB_SYNC_EXT,
  		.vmode			= FB_VMODE_NONINTERLACED
  
  } }, {
  	.bus = LCDIF_BASE_ADDR,
  	.addr = 0,
  	.pixfmt = 24,
  	.detect = NULL,
  	.enable	= do_enable_mipi_led,
  	.mode	= {
  		.name			= "RM67191_OLED",
  		.refresh		= 60,
  		.xres			= 1080,
  		.yres			= 1920,
  		.pixclock		= 7575, /* 132000000 */
  		.left_margin	= 34,
  		.right_margin	= 20,
  		.upper_margin	= 4,
  		.lower_margin	= 10,
  		.hsync_len		= 2,
  		.vsync_len		= 2,
  		.sync			= FB_SYNC_EXT,
  		.vmode			= FB_VMODE_NONINTERLACED
  
  } } };
  size_t display_count = ARRAY_SIZE(displays);
  #endif

  int board_late_init(void)
  {
  #ifdef CONFIG_ENV_IS_IN_MMC
  	board_late_mmc_env_init();
  #endif
  
  	return 0;
  }

  
  #ifdef CONFIG_FSL_FASTBOOT
  #ifdef CONFIG_ANDROID_RECOVERY
  int is_recovery_key_pressing(void)
  {
  	return 0; /*TODO*/
  }
  #endif /*CONFIG_ANDROID_RECOVERY*/
  #endif /*CONFIG_FSL_FASTBOOT*/