Eric Lee / smarc-uboot

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Commit b02221d7cbfe2911ab347813be5155921f08f7f0

Authored by Ye Li
1 parent 6c6206ad1a
Exists in smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga and in 5 other branches smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga

MLK-18243-18: arm: imx: add i.MX8MM EVK board support 

Add i.MX8MM EVK board support
LPDDR4 code is still keep in old coding style to ease updating
if there is no code released.
dts is synced from kernel with sd2 regulator start up delay and off on
delay added.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 01b3f229b188e28b0887c0b32f66e939a50d3a69)
Signed-off-by: Ye Li <ye.li@nxp.com>

Showing 17 changed files with 3137 additions and 1 deletions Side-by-side Diff

arch/arm/dts/Makefile
Diff comments   View file @ b02221d
... ... @@ -430,7 +430,8 @@
430 430  
431 431 dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb \
432 432 fsl-imx8mq-ddr3l-arm2.dtb \
433   - fsl-imx8mq-ddr4-arm2.dtb
  433 + fsl-imx8mq-ddr4-arm2.dtb \
  434 + fsl-imx8mm-evk.dtb
434 435  
435 436 dtb-$(CONFIG_ARCH_IMX8) += fsl-imx8qm-ddr4-arm2.dtb \
436 437 fsl-imx8qm-lpddr4-arm2.dtb \
arch/arm/dts/fsl-imx8mm-evk.dts
Diff comments   View file @ b02221d
  1 +/*
  2 + * Copyright 2018 NXP
  3 + *
  4 + * This program is free software; you can redistribute it and/or
  5 + * modify it under the terms of the GNU General Public License
  6 + * as published by the Free Software Foundation; either version 2
  7 + * of the License, or (at your option) any later version.
  8 + *
  9 + * This program is distributed in the hope that it will be useful,
  10 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12 + * GNU General Public License for more details.
  13 + */
  14 +
  15 +/dts-v1/;
  16 +
  17 +#include "fsl-imx8mm.dtsi"
  18 +
  19 +/ {
  20 + model = "FSL i.MX8MM EVK board";
  21 + compatible = "fsl,imx8mm-evk", "fsl,imx8mm";
  22 +
  23 + chosen {
  24 + bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200";
  25 + stdout-patch = &uart2;
  26 + };
  27 +
  28 + reg_usdhc2_vmmc: regulator-usdhc2 {
  29 + compatible = "regulator-fixed";
  30 + regulator-name = "VSD_3V3";
  31 + regulator-min-microvolt = <3300000>;
  32 + regulator-max-microvolt = <3300000>;
  33 + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
  34 + enable-active-high;
  35 + startup-delay-us = <100>;
  36 + off-on-delay-us = <12000>;
  37 + };
  38 +};
  39 +
  40 +&iomuxc {
  41 + pinctrl-names = "default";
  42 +
  43 + imx8mm-evk {
  44 + pinctrl_fec1: fec1grp {
  45 + fsl,pins = <
  46 + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
  47 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
  48 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
  49 + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
  50 + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
  51 + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
  52 + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
  53 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
  54 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
  55 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
  56 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
  57 + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
  58 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
  59 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
  60 + MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
  61 + >;
  62 + };
  63 +
  64 + pinctrl_flexspi0: flexspi0grp {
  65 + fsl,pins = <
  66 + MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c4
  67 + MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x84
  68 +
  69 + MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x84
  70 + MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x84
  71 + MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x84
  72 + MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x84
  73 + >;
  74 + };
  75 +
  76 + pinctrl_i2c1: i2c1grp {
  77 + fsl,pins = <
  78 + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
  79 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
  80 + >;
  81 + };
  82 +
  83 + pinctrl_i2c2: i2c2grp {
  84 + fsl,pins = <
  85 + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
  86 + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
  87 + >;
  88 + };
  89 +
  90 + pinctrl_i2c3: i2c3grp {
  91 + fsl,pins = <
  92 + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
  93 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
  94 + >;
  95 + };
  96 +
  97 + pinctrl_pmic: pmicirq {
  98 + fsl,pins = <
  99 + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
  100 + >;
  101 + };
  102 +
  103 + pinctrl_uart2: uart1grp {
  104 + fsl,pins = <
  105 + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49
  106 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49
  107 + >;
  108 + };
  109 +
  110 + pinctrl_usdhc2_gpio: usdhc2grpgpio {
  111 + fsl,pins = <
  112 + MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
  113 + >;
  114 + };
  115 +
  116 + pinctrl_usdhc2: usdhc2grp {
  117 + fsl,pins = <
  118 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
  119 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
  120 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
  121 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
  122 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
  123 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
  124 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
  125 + >;
  126 + };
  127 +
  128 + pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
  129 + fsl,pins = <
  130 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
  131 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
  132 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
  133 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
  134 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
  135 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
  136 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
  137 + >;
  138 + };
  139 +
  140 + pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
  141 + fsl,pins = <
  142 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
  143 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
  144 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
  145 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
  146 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
  147 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
  148 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
  149 + >;
  150 + };
  151 +
  152 + pinctrl_usdhc3: usdhc3grp {
  153 + fsl,pins = <
  154 + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190
  155 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
  156 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
  157 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
  158 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
  159 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
  160 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
  161 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
  162 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
  163 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
  164 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
  165 + >;
  166 + };
  167 +
  168 + pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
  169 + fsl,pins = <
  170 + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194
  171 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
  172 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
  173 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
  174 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
  175 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
  176 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
  177 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
  178 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
  179 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
  180 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
  181 + >;
  182 + };
  183 +
  184 + pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
  185 + fsl,pins = <
  186 + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196
  187 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
  188 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
  189 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
  190 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
  191 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
  192 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
  193 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
  194 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
  195 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
  196 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
  197 + >;
  198 + };
  199 +
  200 + pinctrl_wdog: wdoggrp {
  201 + fsl,pins = <
  202 + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
  203 + >;
  204 + };
  205 + };
  206 +};
  207 +
  208 +&i2c1 {
  209 + clock-frequency = <400000>;
  210 + pinctrl-names = "default";
  211 + pinctrl-0 = <&pinctrl_i2c1>;
  212 + status = "okay";
  213 +
  214 + pmic: bd71837@4b {
  215 + reg = <0x4b>;
  216 + compatible = "rohm,bd71837";
  217 + /* PMIC BD71837 PMIC_nINT GPIO1_IO3 */
  218 + pinctrl-0 = <&pinctrl_pmic>;
  219 + gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>;
  220 +
  221 + gpo {
  222 + rohm,drv = <0x0C>; /* 0b0000_1100 all gpos with cmos output mode */
  223 + };
  224 +
  225 + regulators {
  226 + #address-cells = <1>;
  227 + #size-cells = <0>;
  228 +
  229 + bd71837,pmic-buck2-uses-i2c-dvs;
  230 + bd71837,pmic-buck2-dvs-voltage = <1000000>, <900000>, <0>; /* VDD_ARM: Run-Idle */
  231 +
  232 + buck1_reg: regulator@0 {
  233 + reg = <0>;
  234 + regulator-compatible = "buck1";
  235 + regulator-min-microvolt = <700000>;
  236 + regulator-max-microvolt = <1300000>;
  237 + regulator-boot-on;
  238 + regulator-always-on;
  239 + regulator-ramp-delay = <1250>;
  240 + };
  241 +
  242 + buck2_reg: regulator@1 {
  243 + reg = <1>;
  244 + regulator-compatible = "buck2";
  245 + regulator-min-microvolt = <700000>;
  246 + regulator-max-microvolt = <1300000>;
  247 + regulator-boot-on;
  248 + regulator-always-on;
  249 + regulator-ramp-delay = <1250>;
  250 + };
  251 +
  252 + buck3_reg: regulator@2 {
  253 + reg = <2>;
  254 + regulator-compatible = "buck3";
  255 + regulator-min-microvolt = <700000>;
  256 + regulator-max-microvolt = <1300000>;
  257 + };
  258 +
  259 + buck4_reg: regulator@3 {
  260 + reg = <3>;
  261 + regulator-compatible = "buck4";
  262 + regulator-min-microvolt = <700000>;
  263 + regulator-max-microvolt = <1300000>;
  264 + };
  265 +
  266 + buck5_reg: regulator@4 {
  267 + reg = <4>;
  268 + regulator-compatible = "buck5";
  269 + regulator-min-microvolt = <700000>;
  270 + regulator-max-microvolt = <1350000>;
  271 + regulator-boot-on;
  272 + regulator-always-on;
  273 + };
  274 +
  275 + buck6_reg: regulator@5 {
  276 + reg = <5>;
  277 + regulator-compatible = "buck6";
  278 + regulator-min-microvolt = <3000000>;
  279 + regulator-max-microvolt = <3300000>;
  280 + regulator-boot-on;
  281 + regulator-always-on;
  282 + };
  283 +
  284 + buck7_reg: regulator@6 {
  285 + reg = <6>;
  286 + regulator-compatible = "buck7";
  287 + regulator-min-microvolt = <1605000>;
  288 + regulator-max-microvolt = <1995000>;
  289 + regulator-boot-on;
  290 + regulator-always-on;
  291 + };
  292 +
  293 + buck8_reg: regulator@7 {
  294 + reg = <7>;
  295 + regulator-compatible = "buck8";
  296 + regulator-min-microvolt = <800000>;
  297 + regulator-max-microvolt = <1400000>;
  298 + regulator-boot-on;
  299 + regulator-always-on;
  300 + };
  301 +
  302 + ldo1_reg: regulator@8 {
  303 + reg = <8>;
  304 + regulator-compatible = "ldo1";
  305 + regulator-min-microvolt = <3000000>;
  306 + regulator-max-microvolt = <3300000>;
  307 + regulator-boot-on;
  308 + regulator-always-on;
  309 + };
  310 +
  311 + ldo2_reg: regulator@9 {
  312 + reg = <9>;
  313 + regulator-compatible = "ldo2";
  314 + regulator-min-microvolt = <900000>;
  315 + regulator-max-microvolt = <900000>;
  316 + regulator-boot-on;
  317 + regulator-always-on;
  318 + };
  319 +
  320 + ldo3_reg: regulator@10 {
  321 + reg = <10>;
  322 + regulator-compatible = "ldo3";
  323 + regulator-min-microvolt = <1800000>;
  324 + regulator-max-microvolt = <3300000>;
  325 + regulator-boot-on;
  326 + regulator-always-on;
  327 + };
  328 +
  329 + ldo4_reg: regulator@11 {
  330 + reg = <11>;
  331 + regulator-compatible = "ldo4";
  332 + regulator-min-microvolt = <900000>;
  333 + regulator-max-microvolt = <1800000>;
  334 + regulator-boot-on;
  335 + regulator-always-on;
  336 + };
  337 +
  338 + ldo5_reg: regulator@12 {
  339 + reg = <12>;
  340 + regulator-compatible = "ldo5";
  341 + regulator-min-microvolt = <1800000>;
  342 + regulator-max-microvolt = <3300000>;
  343 + };
  344 +
  345 + ldo6_reg: regulator@13 {
  346 + reg = <13>;
  347 + regulator-compatible = "ldo6";
  348 + regulator-min-microvolt = <900000>;
  349 + regulator-max-microvolt = <1800000>;
  350 + regulator-boot-on;
  351 + regulator-always-on;
  352 + };
  353 +
  354 + ldo7_reg: regulator@14 {
  355 + reg = <14>;
  356 + regulator-compatible = "ldo7";
  357 + regulator-min-microvolt = <1800000>;
  358 + regulator-max-microvolt = <3300000>;
  359 + };
  360 + };
  361 + };
  362 +};
  363 +
  364 +&i2c2 {
  365 + clock-frequency = <400000>;
  366 + pinctrl-names = "default";
  367 + pinctrl-0 = <&pinctrl_i2c2>;
  368 + status = "okay";
  369 +};
  370 +
  371 +&i2c3 {
  372 + clock-frequency = <100000>;
  373 + pinctrl-names = "default";
  374 + pinctrl-0 = <&pinctrl_i2c3>;
  375 + status = "okay";
  376 +};
  377 +
  378 +&flexspi0 {
  379 + pinctrl-names = "default";
  380 + pinctrl-0 = <&pinctrl_flexspi0>;
  381 + status = "okay";
  382 +
  383 + flash0: n25q256a@0 {
  384 + reg = <0>;
  385 + #address-cells = <1>;
  386 + #size-cells = <1>;
  387 + compatible = "spi-flash";
  388 + spi-max-frequency = <29000000>;
  389 + spi-nor,ddr-quad-read-dummy = <8>;
  390 + };
  391 +};
  392 +
  393 +&fec1 {
  394 + pinctrl-names = "default";
  395 + pinctrl-0 = <&pinctrl_fec1>;
  396 + phy-mode = "rgmii-id";
  397 + phy-handle = <&ethphy0>;
  398 + fsl,magic-packet;
  399 + status = "okay";
  400 +
  401 + mdio {
  402 + #address-cells = <1>;
  403 + #size-cells = <0>;
  404 +
  405 + ethphy0: ethernet-phy@0 {
  406 + compatible = "ethernet-phy-ieee802.3-c22";
  407 + reg = <0>;
  408 + at803x,led-act-blind-workaround;
  409 + at803x,eee-okay;
  410 + at803x,vddio-1p8v;
  411 + };
  412 + };
  413 +};
  414 +
  415 +&uart2 { /* console */
  416 + pinctrl-names = "default";
  417 + pinctrl-0 = <&pinctrl_uart2>;
  418 + status = "okay";
  419 +};
  420 +
  421 +&usdhc2 {
  422 + pinctrl-names = "default", "state_100mhz", "state_200mhz";
  423 + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
  424 + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
  425 + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
  426 + bus-width = <4>;
  427 + non-removable;
  428 + vmmc-supply = <&reg_usdhc2_vmmc>;
  429 + status = "okay";
  430 +};
  431 +
  432 +&usdhc3 {
  433 + pinctrl-names = "default", "state_100mhz", "state_200mhz";
  434 + pinctrl-0 = <&pinctrl_usdhc3>;
  435 + pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
  436 + pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
  437 + bus-width = <8>;
  438 + non-removable;
  439 + status = "okay";
  440 +};
  441 +
  442 +&wdog1 {
  443 + pinctrl-names = "default";
  444 + pinctrl-0 = <&pinctrl_wdog>;
  445 + fsl,ext-reset-output;
  446 + status = "okay";
  447 +};
  448 +
  449 +&A53_0 {
  450 + arm-supply = <&buck2_reg>;
  451 +};
arch/arm/mach-imx/imx8m/Kconfig
Diff comments   View file @ b02221d
... ... @@ -32,6 +32,11 @@
32 32 select IMX8MQ
33 33 select SUPPORT_SPL
34 34  
  35 +config TARGET_IMX8MM_EVK
  36 + bool "imx8mm evk"
  37 + select IMX8MM
  38 + select SUPPORT_SPL
  39 +
35 40 endchoice
36 41  
37 42 config SYS_SOC
... ... @@ -39,6 +44,7 @@
39 44  
40 45 source "board/freescale/imx8mq_evk/Kconfig"
41 46 source "board/freescale/imx8mq_arm2/Kconfig"
  47 +source "board/freescale/imx8mm_evk/Kconfig"
42 48  
43 49 endif
board/freescale/imx8mm_evk/Kconfig
Diff comments   View file @ b02221d
  1 +if TARGET_IMX8MM_EVK
  2 +
  3 +config SYS_BOARD
  4 + default "imx8mm_evk"
  5 +
  6 +config SYS_VENDOR
  7 + default "freescale"
  8 +
  9 +config SYS_CONFIG_NAME
  10 + default "imx8mm_evk"
  11 +
  12 +source "board/freescale/common/Kconfig"
  13 +
  14 +endif
board/freescale/imx8mm_evk/Makefile
Diff comments   View file @ b02221d
  1 +#
  2 +# Copyright 2018 NXP
  3 +#
  4 +# SPDX-License-Identifier: GPL-2.0+
  5 +#
  6 +
  7 +obj-y += imx8mm_evk.o
  8 +
  9 +ifdef CONFIG_SPL_BUILD
  10 +obj-y += spl.o
  11 +obj-y += ddr/
  12 +endif
board/freescale/imx8mm_evk/ddr/Makefile
Diff comments   View file @ b02221d
  1 +#
  2 +# Copyright 2018 NXP
  3 +#
  4 +# SPDX-License-Identifier: GPL-2.0+
  5 +#
  6 +
  7 +ifdef CONFIG_SPL_BUILD
  8 +obj-y += helper.o
  9 +obj-y += lpddr4_cfg_umctl2_m845.o
  10 +obj-y += lpddr4_phyinit_train_3000mts_fw09.o
  11 +obj-y += lpddr4_pmu_training_3000mts_fw09.o
  12 +obj-y += lpddr4_phyinit_task.o
  13 +endif
board/freescale/imx8mm_evk/ddr/ddr.h
Diff comments   View file @ b02221d
  1 +/*
  2 + * Copyright 2018 NXP
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + * Common file for ddr code
  6 + */
  7 +
  8 +#ifndef __M845S_DDR_H_
  9 +#define __M845S_DDR_H_
  10 +
  11 +#ifdef DDR_DEBUG
  12 +#define ddr_dbg(fmt, ...) printf("DDR: debug:" fmt "\n", ##__VA_ARGS__)
  13 +#else
  14 +#define ddr_dbg(fmt, ...)
  15 +#endif
  16 +
  17 +/*******************************************************************
  18 + Desc: user data type
  19 +
  20 + *******************************************************************/
  21 +enum fw_type {
  22 + FW_1D_IMAGE,
  23 + FW_2D_IMAGE,
  24 +};
  25 +/*******************************************************************
  26 + Desc: prototype
  27 +
  28 + *******************************************************************/
  29 +void ddr_init(void);
  30 +void lpddr4_3000mts_cfg_umctl2(void);
  31 +void ddr_load_train_code(enum fw_type type);
  32 +void dwc_ddrphy_phyinit_userCustom_E_setDfiClk(int pstate);
  33 +void dwc_ddrphy_phyinit_userCustom_J_enterMissionMode(void);
  34 +void dwc_ddrphy_phyinit_userCustom_customPostTrain(void);
  35 +void dwc_ddrphy_phyinit_userCustom_B_startClockResetPhy(void);
  36 +void dwc_ddrphy_phyinit_userCustom_A_bringupPower(void);
  37 +void dwc_ddrphy_phyinit_userCustom_overrideUserInput(void);
  38 +void dwc_ddrphy_phyinit_userCustom_H_readMsgBlock(unsigned long run_2D);
  39 +int dwc_ddrphy_phyinit_userCustom_G_waitFwDone(void);
  40 +void lpddr4_750M_cfg_phy(void);
  41 +
  42 +/*******************************************************************
  43 + Desc: definition
  44 +
  45 + *******************************************************************/
  46 +static inline void reg32_write(unsigned long addr, u32 val)
  47 +{
  48 + writel(val, addr);
  49 +}
  50 +
  51 +static inline uint32_t reg32_read(unsigned long addr)
  52 +{
  53 + return readl(addr);
  54 +}
  55 +
  56 +static inline void reg32setbit(unsigned long addr, u32 bit)
  57 +{
  58 + setbits_le32(addr, (1 << bit));
  59 +}
  60 +#endif
board/freescale/imx8mm_evk/ddr/helper.c
Diff comments   View file @ b02221d
  1 +/*
  2 + * Copyright 2018 NXP
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <common.h>
  8 +#include <spl.h>
  9 +#include <asm/io.h>
  10 +#include <errno.h>
  11 +#include <asm/io.h>
  12 +#include <asm/arch/ddr.h>
  13 +#include <asm/sections.h>
  14 +
  15 +#include "ddr.h"
  16 +
  17 +DECLARE_GLOBAL_DATA_PTR;
  18 +
  19 +#define IMEM_LEN 32768//23400 //byte
  20 +#define DMEM_LEN 16384//1720 //byte
  21 +#define IMEM_2D_OFFSET 49152
  22 +
  23 +#define IMEM_OFFSET_ADDR 0x00050000
  24 +#define DMEM_OFFSET_ADDR 0x00054000
  25 +#define DDR_TRAIN_CODE_BASE_ADDR IP2APB_DDRPHY_IPS_BASE_ADDR(0)
  26 +
  27 +/* We need PHY iMEM PHY is 32KB padded */
  28 +void ddr_load_train_code(enum fw_type type)
  29 +{
  30 + u32 tmp32, i;
  31 + u32 error = 0;
  32 + unsigned long pr_to32, pr_from32;
  33 + unsigned long fw_offset = type ? IMEM_2D_OFFSET : 0;
  34 + unsigned long imem_start = (unsigned long)&_end + fw_offset;
  35 + unsigned long dmem_start = imem_start + IMEM_LEN;
  36 +
  37 + pr_from32 = imem_start;
  38 + pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR;
  39 + for(i = 0x0; i < IMEM_LEN; ){
  40 + tmp32 = readl(pr_from32);
  41 + writew(tmp32 & 0x0000ffff, pr_to32);
  42 + pr_to32 += 4;
  43 + writew((tmp32 >> 16) & 0x0000ffff, pr_to32);
  44 + pr_to32 += 4;
  45 + pr_from32 += 4;
  46 + i += 4;
  47 + }
  48 +
  49 + pr_from32 = dmem_start;
  50 + pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR;
  51 + for(i = 0x0; i < DMEM_LEN;){
  52 + tmp32 = readl(pr_from32);
  53 + writew(tmp32 & 0x0000ffff, pr_to32);
  54 + pr_to32 += 4;
  55 + writew((tmp32 >> 16) & 0x0000ffff, pr_to32);
  56 + pr_to32 += 4;
  57 + pr_from32 += 4;
  58 + i += 4;
  59 + }
  60 +
  61 + printf("check ddr4_pmu_train_imem code\n");
  62 + pr_from32 = imem_start;
  63 + pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR;
  64 + for(i = 0x0; i < IMEM_LEN;){
  65 + tmp32 = (readw(pr_to32) & 0x0000ffff);
  66 + pr_to32 += 4;
  67 + tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16);
  68 +
  69 + if(tmp32 != readl(pr_from32)){
  70 + printf("%lx %lx\n", pr_from32, pr_to32);
  71 + error++;
  72 + }
  73 + pr_from32 += 4;
  74 + pr_to32 += 4;
  75 + i += 4;
  76 + }
  77 + if(error){
  78 + printf("check ddr4_pmu_train_imem code fail=%d\n",error);
  79 + }else{
  80 + printf("check ddr4_pmu_train_imem code pass\n");
  81 + }
  82 +
  83 + printf("check ddr4_pmu_train_dmem code\n");
  84 + pr_from32 = dmem_start;
  85 + pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR;
  86 + for(i = 0x0; i < DMEM_LEN;){
  87 + tmp32 = (readw(pr_to32) & 0x0000ffff);
  88 + pr_to32 += 4;
  89 + tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16);
  90 + if(tmp32 != readl(pr_from32)){
  91 + printf("%lx %lx\n", pr_from32, pr_to32);
  92 + error++;
  93 + }
  94 + pr_from32 += 4;
  95 + pr_to32 += 4;
  96 + i += 4;
  97 + }
  98 +
  99 + if(error){
  100 + printf("check ddr4_pmu_train_dmem code fail=%d",error);
  101 + }else{
  102 + printf("check ddr4_pmu_train_dmem code pass\n");
  103 + }
  104 +}
board/freescale/imx8mm_evk/ddr/lpddr4_cfg_umctl2_m845.c
Diff comments   View file @ b02221d
  1 +/*
  2 + * Copyright 2018 NXP
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <common.h>
  8 +#include <errno.h>
  9 +#include <asm/io.h>
  10 +#include <asm/arch/ddr.h>
  11 +#include <asm/arch/clock.h>
  12 +#include "lpddr4_define.h"
  13 +
  14 +struct ddr_ctl_param
  15 +{
  16 + u32 reg; /*reg address */
  17 + u32 val; /*config param */
  18 +};
  19 +
  20 +static struct ddr_ctl_param ctl_init_cfg[] =
  21 +{
  22 + { .reg =DDRC_DBG1(0), .val = 0x00000001},
  23 + { .reg =DDRC_PWRCTL(0), .val = 0x00000001},
  24 +#ifdef DDR_ONE_RANK
  25 + { .reg =DDRC_MSTR(0), .val = 0xa1080020},
  26 +#else
  27 + { .reg =DDRC_MSTR(0), .val = 0xa3080020},
  28 +#endif
  29 +#ifdef DDR_800M_CFG
  30 + { .reg =DDRC_RFSHTMG(0), .val = 0x006100E0},
  31 +#else
  32 + { .reg =DDRC_RFSHTMG(0), .val = 0x005b00d2},
  33 +#endif
  34 +#ifdef PHY_TRAIN
  35 + { .reg =DDRC_INIT0(0), .val = 0xC003061B},
  36 +#else
  37 +#ifdef DDR_FAST_SIM
  38 + { .reg =DDRC_INIT0(0), .val = 0x00030003},
  39 +#else
  40 + { .reg =DDRC_INIT0(0), .val = 0x0003061B},
  41 +#endif
  42 +#endif
  43 +#ifdef DDR_FAST_SIM
  44 + { .reg =DDRC_INIT1(0), .val = 0x00060000},
  45 +#else
  46 + { .reg =DDRC_INIT1(0), .val = 0x009D0000},
  47 +#endif
  48 + { .reg =DDRC_INIT3(0), .val = 0x00D4002D},
  49 +#ifdef WR_POST_EXT_3200
  50 + { .reg =DDRC_INIT4(0), .val = 0x00330008},
  51 +#else
  52 +
  53 + { .reg =DDRC_INIT4(0), .val = 0x00310000},
  54 +#endif
  55 + { .reg =DDRC_INIT6(0), .val = 0x0066004a},
  56 + { .reg =DDRC_INIT7(0), .val = 0x0006004a},
  57 +
  58 + { .reg =DDRC_DRAMTMG0(0), .val = 0x1A201B22},
  59 + { .reg =DDRC_DRAMTMG1(0), .val = 0x00060633},
  60 + { .reg =DDRC_DRAMTMG3(0), .val = 0x00C0C000},
  61 + { .reg =DDRC_DRAMTMG4(0), .val = 0x0F04080F},
  62 + { .reg =DDRC_DRAMTMG5(0), .val = 0x02040C0C},
  63 + { .reg =DDRC_DRAMTMG6(0), .val = 0x01010007},
  64 + { .reg =DDRC_DRAMTMG7(0), .val = 0x00000401},
  65 + { .reg =DDRC_DRAMTMG12(0), .val = 0x00020600},
  66 + { .reg =DDRC_DRAMTMG13(0), .val = 0x0C100002},
  67 + { .reg =DDRC_DRAMTMG14(0), .val = 0x000000E6},
  68 + { .reg =DDRC_DRAMTMG17(0), .val = 0x00A00050},
  69 +
  70 + { .reg =DDRC_ZQCTL0(0), .val = 0x03200018},
  71 + { .reg =DDRC_ZQCTL1(0), .val = 0x028061A8},
  72 + { .reg =DDRC_ZQCTL2(0), .val = 0x00000000},
  73 +
  74 + { .reg =DDRC_DFITMG0(0), .val = 0x0497820A},
  75 + { .reg =DDRC_DFITMG1(0), .val = 0x00080303},
  76 + { .reg =DDRC_DFIUPD0(0), .val = 0xE0400018},
  77 +
  78 + { .reg =DDRC_DFIUPD1(0), .val = 0x00DF00E4},
  79 + { .reg =DDRC_DFIUPD2(0), .val = 0x80000000},
  80 + { .reg =DDRC_DFIMISC(0), .val = 0x00000011},
  81 + { .reg =DDRC_DFITMG2(0), .val = 0x0000170A},
  82 +
  83 + { .reg =DDRC_DBICTL(0), .val = 0x00000001},
  84 +#ifdef BUG_WR_DFI
  85 + { .reg =DDRC_DFIPHYMSTR(0), .val = 0x00000000},
  86 +#else
  87 + { .reg =DDRC_DFIPHYMSTR(0), .val = 0x00000001},
  88 +#endif
  89 + { .reg =DDRC_RANKCTL(0), .val = 0x00000c99},
  90 + { .reg =DDRC_DRAMTMG2(0), .val = 0x070E171a},
  91 +#ifdef M845S_4GBx2
  92 +#ifdef DDR_ONE_RANK
  93 + { .reg =DDRC_ADDRMAP0(0), .val = 0x0000001f},
  94 +#else
  95 + { .reg =DDRC_ADDRMAP0(0), .val = 0x00000017},
  96 +#endif
  97 + { .reg =DDRC_ADDRMAP1(0), .val = 0x00080808},
  98 + { .reg =DDRC_ADDRMAP2(0), .val = 0x00000000},
  99 + { .reg =DDRC_ADDRMAP3(0), .val = 0x00000000},
  100 + { .reg =DDRC_ADDRMAP4(0), .val = 0x00001f1f},
  101 + { .reg =DDRC_ADDRMAP5(0), .val = 0x07070707},
  102 + { .reg =DDRC_ADDRMAP6(0), .val = 0x07070707},
  103 + { .reg =DDRC_ADDRMAP7(0), .val = 0x00000f0f},
  104 +#else
  105 +#ifdef DDR_ONE_RANK
  106 + { .reg =DDRC_ADDRMAP0(0), .val = 0x0000001f},
  107 +#else
  108 + { .reg =DDRC_ADDRMAP0(0), .val = 0x00000016},
  109 +#endif
  110 + { .reg =DDRC_ADDRMAP1(0), .val = 0x00080808},
  111 + { .reg =DDRC_ADDRMAP2(0), .val = 0x00000000},
  112 + { .reg =DDRC_ADDRMAP3(0), .val = 0x00000000},
  113 + { .reg =DDRC_ADDRMAP4(0), .val = 0x00001f1f},
  114 + { .reg =DDRC_ADDRMAP5(0), .val = 0x07070707},
  115 + { .reg =DDRC_ADDRMAP6(0), .val = 0x0f070707},
  116 + { .reg =DDRC_ADDRMAP7(0), .val = 0x00000f0f},
  117 + { .reg =DDRC_ADDRMAP8(0), .val = 0x00000000},
  118 + { .reg =DDRC_ADDRMAP9(0), .val = 0x0a020b06},
  119 + { .reg =DDRC_ADDRMAP10(0), .val = 0x0a0a0a0a},
  120 + { .reg =DDRC_ADDRMAP11(0), .val = 0x00000000},
  121 +#endif
  122 +
  123 +#ifdef PERF_TEST_2
  124 + { .reg =DDRC_SCHED(0), .val = 0x29001701},
  125 + { .reg =DDRC_SCHED1(0), .val = 0x0000002c},
  126 + { .reg =DDRC_PERFLPR1(0), .val = 0x900093e7},
  127 + { .reg =DDRC_PCCFG(0), .val = 0x00000111},
  128 + { .reg =DDRC_PCFGW_0(0), .val = 0x000072ff},
  129 + { .reg =DDRC_PCFGQOS0_0(0), .val = 0x02100e07},
  130 + { .reg =DDRC_PCFGQOS1_0(0), .val = 0x00620096},
  131 + { .reg =DDRC_PCFGWQOS0_0(0), .val = 0x01100e07},
  132 + { .reg =DDRC_PCFGWQOS1_0(0), .val = 0x0000012c},
  133 +#else
  134 + { .reg =DDRC_SCHED(0), .val = 0x29001701},
  135 + { .reg =DDRC_SCHED1(0), .val = 0x0000002c},
  136 + { .reg =DDRC_PERFHPR1(0), .val = 0x04000030},
  137 + { .reg =DDRC_PERFLPR1(0), .val = 0x900093e7},
  138 + { .reg =DDRC_PCCFG(0), .val = 0x00000111},
  139 + { .reg =DDRC_PCFGW_0(0), .val = 0x000072ff},
  140 + { .reg =DDRC_PCFGQOS0_0(0), .val = 0x02100e07},
  141 + { .reg =DDRC_PCFGQOS1_0(0), .val = 0x00620096},
  142 + { .reg =DDRC_PCFGWQOS0_0(0), .val = 0x01100e07},
  143 + { .reg =DDRC_PCFGWQOS1_0(0), .val = 0x0000012c},
  144 +#endif
  145 +
  146 +#ifdef P1_400
  147 + { .reg =DDRC_FREQ1_DRAMTMG0(0), .val = 0x0d0b010c},
  148 + { .reg =DDRC_FREQ1_DRAMTMG1(0), .val = 0x00030410},
  149 + { .reg =DDRC_FREQ1_DRAMTMG2(0), .val = 0x0305090c},
  150 + { .reg =DDRC_FREQ1_DRAMTMG3(0), .val = 0x00505006},
  151 + { .reg =DDRC_FREQ1_DRAMTMG4(0), .val = 0x05040305},
  152 + { .reg =DDRC_FREQ1_DRAMTMG5(0), .val = 0x0d0e0504},
  153 + { .reg =DDRC_FREQ1_DRAMTMG6(0), .val = 0x0a060004},
  154 + { .reg =DDRC_FREQ1_DRAMTMG7(0), .val = 0x0000090e},
  155 + { .reg =DDRC_FREQ1_DRAMTMG14(0), .val = 0x00000032},
  156 + { .reg =DDRC_FREQ1_DRAMTMG15(0), .val = 0x00000000},
  157 + { .reg =DDRC_FREQ1_DRAMTMG17(0), .val = 0x0036001b},
  158 + { .reg =DDRC_FREQ1_DERATEINT(0), .val = 0x7e9fbeb1},
  159 + { .reg =DDRC_FREQ1_DFITMG0(0), .val = 0x03818200},
  160 + { .reg =DDRC_FREQ1_DFITMG2(0), .val = 0x00000000},
  161 + { .reg =DDRC_FREQ1_RFSHTMG(0), .val = 0x000C001c},
  162 + { .reg =DDRC_FREQ1_INIT3(0), .val = 0x00840000},
  163 + { .reg =DDRC_FREQ1_INIT4(0), .val = 0x00310000},
  164 + { .reg =DDRC_FREQ1_INIT6(0), .val = 0x0066004a},
  165 + { .reg =DDRC_FREQ1_INIT7(0), .val = 0x0006004a},
  166 +#else
  167 +#ifdef WEI_667
  168 + { .reg =DDRC_FREQ1_DRAMTMG0(0), .val = 0x0d0b0107},
  169 + { .reg =DDRC_FREQ1_DRAMTMG1(0), .val = 0x00030410},
  170 + { .reg =DDRC_FREQ1_DRAMTMG2(0), .val = 0x0305080c},
  171 + { .reg =DDRC_FREQ1_DRAMTMG3(0), .val = 0x00505006},
  172 + { .reg =DDRC_FREQ1_DRAMTMG4(0), .val = 0x05040305},
  173 + { .reg =DDRC_FREQ1_DRAMTMG5(0), .val = 0x0f0b0504},
  174 + { .reg =DDRC_FREQ1_DRAMTMG6(0), .val = 0x0e0c000c},
  175 + { .reg =DDRC_FREQ1_DRAMTMG7(0), .val = 0x00000607},
  176 + { .reg =DDRC_FREQ1_DRAMTMG14(0), .val = 0x00000066},
  177 + { .reg =DDRC_FREQ1_DRAMTMG15(0), .val = 0x80000000},
  178 + { .reg =DDRC_FREQ1_DRAMTMG17(0), .val = 0x0036001b},
  179 + { .reg =DDRC_FREQ1_DFITMG0(0), .val = 0x03858202},
  180 + { .reg =DDRC_FREQ1_DFITMG2(0), .val = 0x00000502},
  181 + { .reg =DDRC_FREQ1_DERATEEN(0), .val = 0x00000001},
  182 + { .reg =DDRC_FREQ1_DERATEINT(0), .val = 0x2545eb1c},
  183 + { .reg =DDRC_FREQ1_RFSHTMG(0), .val = 0x0014002f},
  184 + { .reg =DDRC_FREQ1_INIT3(0), .val = 0x00140009},
  185 + { .reg =DDRC_FREQ1_INIT4(0), .val = 0x00310000},
  186 + { .reg =DDRC_FREQ1_INIT6(0), .val = 0x0066004d},
  187 + { .reg =DDRC_FREQ1_INIT7(0), .val = 0x0006004d},
  188 +#else
  189 + { .reg =DDRC_FREQ1_DERATEEN(0), .val = 0x0000000},
  190 + { .reg =DDRC_FREQ1_DERATEINT(0), .val = 0x0800000},
  191 + { .reg =DDRC_FREQ1_RFSHCTL0(0), .val = 0x0210000},
  192 + { .reg =DDRC_FREQ1_RFSHTMG(0), .val = 0x014001E},
  193 + { .reg =DDRC_FREQ1_INIT3(0), .val = 0x0140009},
  194 + { .reg =DDRC_FREQ1_INIT4(0), .val = 0x00310000},
  195 + { .reg =DDRC_FREQ1_INIT6(0), .val = 0x0066004a},
  196 + { .reg =DDRC_FREQ1_INIT7(0), .val = 0x0006004a},
  197 + { .reg =DDRC_FREQ1_DRAMTMG0(0), .val = 0xB070A07},
  198 + { .reg =DDRC_FREQ1_DRAMTMG1(0), .val = 0x003040A},
  199 + { .reg =DDRC_FREQ1_DRAMTMG2(0), .val = 0x305080C},
  200 + { .reg =DDRC_FREQ1_DRAMTMG3(0), .val = 0x0505000},
  201 + { .reg =DDRC_FREQ1_DRAMTMG4(0), .val = 0x3040203},
  202 + { .reg =DDRC_FREQ1_DRAMTMG5(0), .val = 0x2030303},
  203 + { .reg =DDRC_FREQ1_DRAMTMG6(0), .val = 0x2020004},
  204 + { .reg =DDRC_FREQ1_DRAMTMG7(0), .val = 0x0000302},
  205 + { .reg =DDRC_FREQ1_DRAMTMG12(0), .val = 0x0020310},
  206 + { .reg =DDRC_FREQ1_DRAMTMG13(0), .val = 0xA100002},
  207 + { .reg =DDRC_FREQ1_DRAMTMG14(0), .val = 0x0000020},
  208 + { .reg =DDRC_FREQ1_DRAMTMG17(0), .val = 0x0220011},
  209 + { .reg =DDRC_FREQ1_ZQCTL0(0), .val = 0x0A70005},
  210 + { .reg =DDRC_FREQ1_DFITMG0(0), .val = 0x3858202},
  211 + { .reg =DDRC_FREQ1_DFITMG1(0), .val = 0x0000404},
  212 + { .reg =DDRC_FREQ1_DFITMG2(0), .val = 0x0000502},
  213 +#endif
  214 +#endif
  215 + { .reg =DDRC_FREQ2_DRAMTMG0(0), .val = 0x0d0b010c},
  216 + { .reg =DDRC_FREQ2_DRAMTMG1(0), .val = 0x00030410},
  217 + { .reg =DDRC_FREQ2_DRAMTMG2(0), .val = 0x0305090c},
  218 + { .reg =DDRC_FREQ2_DRAMTMG3(0), .val = 0x00505006},
  219 + { .reg =DDRC_FREQ2_DRAMTMG4(0), .val = 0x05040305},
  220 + { .reg =DDRC_FREQ2_DRAMTMG5(0), .val = 0x0d0e0504},
  221 + { .reg =DDRC_FREQ2_DRAMTMG6(0), .val = 0x0a060004},
  222 + { .reg =DDRC_FREQ2_DRAMTMG7(0), .val = 0x0000090e},
  223 + { .reg =DDRC_FREQ2_DRAMTMG14(0), .val = 0x00000032},
  224 + { .reg =DDRC_FREQ2_DRAMTMG17(0), .val = 0x0036001b},
  225 + { .reg =DDRC_FREQ2_DERATEINT(0), .val = 0x7e9fbeb1},
  226 + { .reg =DDRC_FREQ2_DFITMG0(0), .val = 0x03818200},
  227 + { .reg =DDRC_FREQ2_DFITMG2(0), .val = 0x00000000},
  228 + { .reg =DDRC_FREQ2_RFSHTMG(0), .val = 0x00030007},
  229 + { .reg =DDRC_FREQ2_INIT3(0), .val = 0x00840000},
  230 + { .reg =DDRC_FREQ2_INIT4(0), .val = 0x00310000},
  231 + { .reg =DDRC_FREQ2_INIT6(0), .val = 0x0066004a},
  232 + { .reg =DDRC_FREQ2_INIT7(0), .val = 0x0006004a},
  233 +#ifdef DDR_BOOT_P2
  234 + { .reg =DDRC_MSTR2(0), .val = 0x2},
  235 +#else
  236 +#ifdef DDR_BOOT_P1
  237 + { .reg =DDRC_MSTR2(0), .val = 0x1},
  238 +#else
  239 + { .reg =DDRC_MSTR2(0), .val = 0x0},
  240 +#endif
  241 +#endif
  242 + { .reg = DDRC_ODTCFG(0), 0x0b060908},
  243 + { .reg = DDRC_ODTMAP(0), 0x00000000},
  244 + { .reg = DDRC_SCHED(0), 0x29511505},
  245 + { .reg = DDRC_SCHED1(0), 0x0000002c},
  246 + { .reg = DDRC_PERFHPR1(0), 0x5900575b},
  247 + { .reg = DDRC_PERFLPR1(0), 0x00000009},
  248 + { .reg = DDRC_PERFWR1(0), 0x02005574},
  249 + { .reg = DDRC_DBG0(0), 0x00000016},
  250 + { .reg = DDRC_DBG1(0), 0x00000000},
  251 + { .reg = DDRC_DBGCMD(0), 0x00000000},
  252 + { .reg = DDRC_SWCTL(0), 0x00000001},
  253 + { .reg = DDRC_POISONCFG(0), 0x00000011},
  254 + { .reg = DDRC_PCCFG(0), 0x00000111},
  255 + { .reg = DDRC_PCFGR_0(0), 0x000010f3},
  256 + { .reg = DDRC_PCFGW_0(0), 0x000072ff},
  257 + { .reg = DDRC_PCTRL_0(0), 0x00000001},
  258 + { .reg = DDRC_PCFGQOS0_0(0), 0x01110d00},
  259 + { .reg = DDRC_PCFGQOS1_0(0), 0x00620790},
  260 + { .reg = DDRC_PCFGWQOS0_0(0), 0x00100001},
  261 + { .reg = DDRC_PCFGWQOS1_0(0), 0x0000041f},
  262 + { .reg = DDRC_FREQ1_DERATEEN(0), 0x00000202},
  263 + { .reg = DDRC_FREQ1_DERATEINT(0), 0xec78f4b5},
  264 + { .reg = DDRC_FREQ1_RFSHCTL0(0), 0x00618040},
  265 + { .reg = DDRC_FREQ1_RFSHTMG(0), 0x00610090},
  266 +};
  267 +
  268 +void lpddr4_3000mts_cfg_umctl2(void)
  269 +{
  270 + u32 index, reg, val, num;
  271 +
  272 + num = sizeof(ctl_init_cfg)/sizeof(struct ddr_ctl_param);
  273 +
  274 + for (index = 0; index < num; index++) {
  275 + val = ctl_init_cfg[index].val;
  276 + reg = ctl_init_cfg[index].reg;
  277 + writel(val, (void __iomem *)(u64)reg);
  278 + }
  279 +}
board/freescale/imx8mm_evk/ddr/lpddr4_define.h
Diff comments   View file @ b02221d
  1 +/*
  2 + * Copyright 2018 NXP
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#ifndef LPDDR4_DEFINE_H
  8 +#define LPDDR4_DEFINE_H
  9 +
  10 +#include "ddr.h"
  11 +
  12 +#define RUN_ON_SILICON
  13 +#define DFI_BUG_WR
  14 +#define DEVINIT_PHY
  15 +
  16 +#define DDR_ONE_RANK
  17 +#define BUG_WR_DFI
  18 +#define M845S_4GBx2
  19 +
  20 +#ifdef LPDDR4_667MTS
  21 +#define P0_667
  22 +#endif
  23 +#ifdef LPDDR4_1600MTS
  24 +#define P0_1600
  25 +#endif
  26 +#ifdef LPDDR4_DVFS
  27 +#define DVFS_TEST
  28 +#define PHY_TRAIN
  29 +#define DDR_BOOT_P1
  30 +#endif
  31 +#ifdef LPDDR4_RETENTION
  32 +#define NORMAL_RET_EN
  33 +#endif
  34 +
  35 +#ifdef P0_667
  36 +#define P0_DRATE 667
  37 +#else
  38 +#ifdef P0_1600
  39 +#define P0_DRATE 1600
  40 +#else
  41 +#define P0_DRATE 3000
  42 +#endif
  43 +#endif
  44 +
  45 +#define P1_DRATE 667
  46 +#define P2_DRATE 100
  47 +
  48 +#ifdef RUN_ON_SILICON
  49 +#define PHY_TRAIN
  50 +#define ADD_P0_2D_BF_P1
  51 +#ifdef HWFFC
  52 +#define ADD_TRAIN_1D_P2
  53 +#endif
  54 +#else
  55 +#define DDR_FAST_SIM
  56 +#endif
  57 +
  58 +#ifdef PHY_TRAIN
  59 +#define ADD_TRAIN_1D_P0
  60 +#ifdef DVFS_TEST
  61 +#define ADD_TRAIN_1D_P1
  62 +#endif
  63 +#endif
  64 +
  65 +/* define BOOT FREQ, not modify */
  66 +#ifdef DDR_BOOT_P1
  67 +#define BOOT_FREQ P1_DRATE
  68 +#else
  69 +#ifdef DDR_BOOT_P2
  70 +#define BOOT_FREQ P2_DRATE
  71 +#else
  72 +#define BOOT_FREQ P0_DRATE
  73 +#endif
  74 +#endif
  75 +
  76 +/* #define P1_FREQ 167 */
  77 +#ifdef PHY_TRAIN
  78 +#define CLOCK_SWITCH_PLL P0_DRATE
  79 +#else
  80 +#define CLOCK_SWITCH_PLL BOOT_FREQ
  81 +#endif
  82 +
  83 +#define DDR_CSD2_BASE_ADDR 0x80000000
  84 +#define GPC_PU_PWRHSK 0x303A01FC
  85 +
  86 +//----------------------------------------------------------------
  87 +// PHY training feature
  88 +//----------------------------------------------------------------
  89 +#define LPDDR4_HDT_CTL_2D 0xC8 //stage completion
  90 +#define LPDDR4_HDT_CTL_3200_1D 0xC8 //stage completion
  91 +#define LPDDR4_HDT_CTL_400_1D 0xC8 //stage completion
  92 +#define LPDDR4_HDT_CTL_100_1D 0xC8 //stage completion
  93 +
  94 +#define LPDDR4_HDT_CTL_2D 0xC8 //stage completion
  95 +#define LPDDR4_HDT_CTL_3200_1D 0xC8 //stage completion
  96 +#define LPDDR4_HDT_CTL_400_1D 0xC8 //stage completion
  97 +#define LPDDR4_HDT_CTL_100_1D 0xC8 //stage completion
  98 +
  99 +#ifdef RUN_ON_SILICON
  100 +// 400/100 training seq
  101 +#define LPDDR4_TRAIN_SEQ_P2 0x121f
  102 +#define LPDDR4_TRAIN_SEQ_P1 0x121f
  103 +#define LPDDR4_TRAIN_SEQ_P0 0x121f
  104 +#else
  105 +#define LPDDR4_TRAIN_SEQ_P2 0x7
  106 +#define LPDDR4_TRAIN_SEQ_P1 0x7
  107 +#define LPDDR4_TRAIN_SEQ_P0 0x7
  108 +#endif
  109 +
  110 +//2D share & weight
  111 +#define LPDDR4_2D_WEIGHT 0x1f7f
  112 +#define LPDDR4_2D_SHARE 1
  113 +#define LPDDR4_CATRAIN_3200_1d 0
  114 +#define LPDDR4_CATRAIN_400 0
  115 +#define LPDDR4_CATRAIN_100 0
  116 +#define LPDDR4_CATRAIN_3200_2d 0
  117 +
  118 +/* MRS parameter */
  119 +/* for LPDDR4 Rtt */
  120 +#define LPDDR4_RTT40 6
  121 +#define LPDDR4_RTT48 5
  122 +#define LPDDR4_RTT60 4
  123 +#define LPDDR4_RTT80 3
  124 +#define LPDDR4_RTT120 2
  125 +#define LPDDR4_RTT240 1
  126 +#define LPDDR4_RTT_DIS 0
  127 +
  128 +/* for LPDDR4 Ron */
  129 +#define LPDDR4_RON34 7
  130 +#define LPDDR4_RON40 6
  131 +#define LPDDR4_RON48 5
  132 +#define LPDDR4_RON60 4
  133 +#define LPDDR4_RON80 3
  134 +
  135 +#define LPDDR4_PHY_ADDR_RON60 0x1
  136 +#define LPDDR4_PHY_ADDR_RON40 0x3
  137 +#define LPDDR4_PHY_ADDR_RON30 0x7
  138 +#define LPDDR4_PHY_ADDR_RON24 0xf
  139 +#define LPDDR4_PHY_ADDR_RON20 0x1f
  140 +
  141 +/* for read channel */
  142 +#define LPDDR4_RON LPDDR4_RON40 /* MR3[5:3] */
  143 +#define LPDDR4_PHY_RTT 30 /* //30//40//28 */
  144 +/* #define LPDDR4_PHY_VREF_VALUE 27//17//17//20//16///17,//for M845S */
  145 +#define LPDDR4_PHY_VREF_VALUE 17 /*//17//20//16///17,//for M850D*/
  146 +
  147 +/* for write channel */
  148 +#define LPDDR4_PHY_RON 30
  149 +#define LPDDR4_PHY_ADDR_RON LPDDR4_PHY_ADDR_RON40
  150 +#define LPDDR4_RTT_DQ LPDDR4_RTT40
  151 +#define LPDDR4_RTT_CA LPDDR4_RTT40
  152 +#define LPDDR4_RTT_CA_BANK0 LPDDR4_RTT40
  153 +#define LPDDR4_RTT_CA_BANK1 LPDDR4_RTT40
  154 +#define LPDDR4_VREF_VALUE_CA ((1 << 6)|0xd)
  155 +#define LPDDR4_VREF_VALUE_DQ_RANK0 ((1 << 6)|0xd)
  156 +#define LPDDR4_VREF_VALUE_DQ_RANK1 ((1 << 6)|0xd)
  157 +#define LPDDR4_MR22_RANK0 ((0 << 5)|(0 << 4)|(0 << 3)|(LPDDR4_RTT40))
  158 +#define LPDDR4_MR22_RANK1 ((1 << 5)|(0 << 4)|(1 << 3)|(LPDDR4_RTT40))
  159 +#define LPDDR4_MR3_PU_CAL 1
  160 +
  161 +#endif
board/freescale/imx8mm_evk/ddr/lpddr4_phyinit_task.c
Diff comments   View file @ b02221d
  1 +/*
  2 + * Copyright 2018 NXP
  3 + * SPDX-License-Identifier: GPL-2.0+
  4 + */
  5 +
  6 +#include <common.h>
  7 +#include <errno.h>
  8 +#include <asm/io.h>
  9 +#include <asm/arch/ddr.h>
  10 +#include <asm/arch/clock.h>
  11 +#include "lpddr4_define.h"
  12 +
  13 +void dwc_ddrphy_phyinit_userCustom_E_setDfiClk(int pstate)
  14 +{
  15 + if(pstate==2)
  16 + dram_pll_init(DRAM_PLL_OUT_100M);
  17 + else if(pstate==1)
  18 + dram_pll_init(DRAM_PLL_OUT_667M);
  19 + else
  20 + dram_pll_init(DRAM_PLL_OUT_750M);
  21 +}
  22 +
  23 +int dwc_ddrphy_phyinit_userCustom_G_waitFwDone(void)
  24 +{
  25 + volatile unsigned int tmp, tmp_t;
  26 + volatile unsigned int train_ok;
  27 + volatile unsigned int train_fail;
  28 + volatile unsigned int stream_msg;
  29 + int ret = 0;
  30 +
  31 + train_ok = 0;
  32 + train_fail = 0;
  33 + stream_msg = 0;
  34 + while (train_ok == 0 && train_fail == 0) {
  35 + tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0004);
  36 + tmp_t = tmp & 0x01;
  37 + while (tmp_t){
  38 + tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0004);
  39 + tmp_t = tmp & 0x01;
  40 + }
  41 +#ifdef PRINT_PMU
  42 + printf("get the training message\n");
  43 +#endif
  44 + tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0032);
  45 +#ifdef PRINT_PMU
  46 + printf("PMU major stream =0x%x\n",tmp);
  47 +#endif
  48 + if (tmp==0x08) {
  49 + stream_msg = 1;
  50 +
  51 +#ifdef DDR_PRINT_ALL_MESSAGE
  52 + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0031, 0x0);
  53 +
  54 + do {
  55 + tmp_t = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0004);
  56 + }while((tmp_t & 0x1) == 0x0);
  57 + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0031, 0x1);
  58 +
  59 + do {
  60 + tmp_t = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0004);
  61 + }while((tmp_t & 0x1) == 0x1);
  62 +
  63 + /* read_mbox_mssg */
  64 + stream_nb_args = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) +4 * 0xd0032);
  65 +
  66 + /* read_mbox_msb */
  67 + stream_index = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0034);
  68 + stream_index = (stream_index << 16) | stream_nb_args;
  69 +#ifdef PRINT_PMU
  70 + printf("PMU stream_index=0x%x nb_args=%d\n",stream_index, stream_nb_args);
  71 +#endif
  72 +
  73 + stream_arg_pos = 0;
  74 + while (stream_nb_args > 0) {
  75 + /* Need to complete previous handshake first... */
  76 + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0031, 0x0);
  77 + /* poll_mbox_from_uc(1); */
  78 +
  79 + do {
  80 + tmp_t = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0004);
  81 + } while((tmp_t & 0x1) == 0x0);
  82 + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0031, 0x1);
  83 +
  84 + /* Read the next argument... */
  85 + do {
  86 + tmp_t = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0004);
  87 + }while((tmp_t & 0x1) == 0x1);
  88 +
  89 + /* read_mbox_mssg */
  90 + message = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0032);
  91 + /* read_mbox_msb */
  92 + stream_arg_val = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0034);
  93 + stream_arg_val = (stream_arg_val << 16) | message;
  94 +#ifdef PRINT_PMU
  95 + printf("PMU stream_arg[%d]=0x%x\n",stream_arg_pos, stream_arg_val);
  96 +#endif
  97 + stream_nb_args--;
  98 + stream_arg_pos++;
  99 + }
  100 +#endif
  101 + } else if(tmp==0x07) {
  102 + train_ok = 1;
  103 + ret = 0;
  104 + } else if(tmp==0xff) {
  105 + train_fail = 1;
  106 + printf("%c[31;40m",0x1b);
  107 + printf("------- training vt_fail\n");
  108 + printf("%c[0m",0x1b);
  109 +
  110 + ret = -1;
  111 + } else {
  112 + train_ok = 0;
  113 + train_fail = 0;
  114 + stream_msg = 0;
  115 + }
  116 +
  117 + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0031,0x0);
  118 +
  119 + if (stream_msg == 1) {
  120 + tmp_t = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0034);
  121 + tmp_t = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0034);
  122 + }
  123 +
  124 + tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0004);
  125 + tmp_t = tmp & 0x01;
  126 + while(tmp_t==0){
  127 + tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0004);
  128 + tmp_t = tmp & 0x01;
  129 + }
  130 + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0031,0x1);
  131 + }
  132 +
  133 + return ret;
  134 +}
  135 +
  136 +void dwc_ddrphy_phyinit_userCustom_H_readMsgBlock(unsigned long run_2D)
  137 +{
  138 +}
  139 +
  140 +void dwc_ddrphy_phyinit_userCustom_overrideUserInput(void)
  141 +{
  142 +}
  143 +void dwc_ddrphy_phyinit_userCustom_A_bringupPower(void)
  144 +{
  145 +}
  146 +void dwc_ddrphy_phyinit_userCustom_B_startClockResetPhy(void)
  147 +{
  148 +}
  149 +void dwc_ddrphy_phyinit_userCustom_customPostTrain(void)
  150 +{
  151 +}
  152 +void dwc_ddrphy_phyinit_userCustom_J_enterMissionMode(void)
  153 +{
  154 +}
board/freescale/imx8mm_evk/ddr/lpddr4_phyinit_train_3000mts_fw09.c
Diff comments   View file @ b02221d
  1 +/*
  2 + * Copyright 2018 NXP
  3 + * SPDX-License-Identifier: GPL-2.0+
  4 + */
  5 +
  6 +#include <common.h>
  7 +#include <errno.h>
  8 +#include <asm/io.h>
  9 +#include <asm/arch/ddr.h>
  10 +#include <asm/arch/clock.h>
  11 +#include "lpddr4_define.h"
  12 +
  13 +struct ddr_phy_param {
  14 + u32 reg; /* reg address */
  15 + u32 val; /* config param */
  16 +};
  17 +
  18 +
  19 +#define DDR_PHY_FLAG_ADDR 0x00187F00
  20 +
  21 +static struct ddr_phy_param phy_init_cfg[] =
  22 +{
  23 + { .reg = 0x3c000000+4*0x1005f, .val = 0x15f},
  24 + { .reg = 0x3c000000+4*0x1015f, .val = 0x15f},
  25 + { .reg = 0x3c000000+4*0x1105f, .val = 0x15f},
  26 + { .reg = 0x3c000000+4*0x1115f, .val = 0x15f},
  27 + { .reg = 0x3c000000+4*0x1205f, .val = 0x15f},
  28 + { .reg = 0x3c000000+4*0x1215f, .val = 0x15f},
  29 + { .reg = 0x3c000000+4*0x1305f, .val = 0x15f},
  30 + { .reg = 0x3c000000+4*0x1315f, .val = 0x15f},
  31 + { .reg = 0x3c000000+4*0x55, .val = 0x16f},
  32 + { .reg = 0x3c000000+4*0x1055, .val = 0x16f},
  33 + { .reg = 0x3c000000+4*0x2055, .val = 0x16f},
  34 + { .reg = 0x3c000000+4*0x3055, .val = 0x16f},
  35 + { .reg = 0x3c000000+4*0x4055, .val = 0x16f},
  36 + { .reg = 0x3c000000+4*0x5055, .val = 0x16f},
  37 + { .reg = 0x3c000000+4*0x6055, .val = 0x16f},
  38 + { .reg = 0x3c000000+4*0x7055, .val = 0x16f},
  39 + { .reg = 0x3c000000+4*0x8055, .val = 0x16f},
  40 + { .reg = 0x3c000000+4*0x9055, .val = 0x16f},
  41 + { .reg = 0x3c000000+4*0x200c5, .val = 0x19},
  42 + { .reg = 0x3c000000+4*0x2002e, .val = 0x2},
  43 + { .reg = 0x3c000000+4*0x90204, .val = 0x0},
  44 + { .reg = 0x3c000000+4*0x20024, .val = 0xab},
  45 + { .reg = 0x3c000000+4*0x2003a, .val = 0x0},
  46 + { .reg = 0x3c000000+4*0x20056, .val = 0x3},
  47 + { .reg = 0x3c000000+4*0x1004d, .val = 0xe00},
  48 + { .reg = 0x3c000000+4*0x1014d, .val = 0xe00},
  49 + { .reg = 0x3c000000+4*0x1104d, .val = 0xe00},
  50 + { .reg = 0x3c000000+4*0x1114d, .val = 0xe00},
  51 + { .reg = 0x3c000000+4*0x1204d, .val = 0xe00},
  52 + { .reg = 0x3c000000+4*0x1214d, .val = 0xe00},
  53 + { .reg = 0x3c000000+4*0x1304d, .val = 0xe00},
  54 + { .reg = 0x3c000000+4*0x1314d, .val = 0xe00},
  55 + { .reg = 0x3c000000+4*0x10049, .val = 0xfbe},
  56 + { .reg = 0x3c000000+4*0x10149, .val = 0xfbe},
  57 + { .reg = 0x3c000000+4*0x11049, .val = 0xfbe},
  58 + { .reg = 0x3c000000+4*0x11149, .val = 0xfbe},
  59 + { .reg = 0x3c000000+4*0x12049, .val = 0xfbe},
  60 + { .reg = 0x3c000000+4*0x12149, .val = 0xfbe},
  61 + { .reg = 0x3c000000+4*0x13049, .val = 0xfbe},
  62 + { .reg = 0x3c000000+4*0x13149, .val = 0xfbe},
  63 + { .reg = 0x3c000000+4*0x43, .val = 0x63},
  64 + { .reg = 0x3c000000+4*0x1043, .val = 0x63},
  65 + { .reg = 0x3c000000+4*0x2043, .val = 0x63},
  66 + { .reg = 0x3c000000+4*0x3043, .val = 0x63},
  67 + { .reg = 0x3c000000+4*0x4043, .val = 0x63},
  68 + { .reg = 0x3c000000+4*0x5043, .val = 0x63},
  69 + { .reg = 0x3c000000+4*0x6043, .val = 0x63},
  70 + { .reg = 0x3c000000+4*0x7043, .val = 0x63},
  71 + { .reg = 0x3c000000+4*0x8043, .val = 0x63},
  72 + { .reg = 0x3c000000+4*0x9043, .val = 0x63},
  73 + { .reg = 0x3c000000+4*0x20018, .val = 0x3},
  74 + { .reg = 0x3c000000+4*0x20075, .val = 0x4},
  75 + { .reg = 0x3c000000+4*0x20050, .val = 0x0},
  76 + { .reg = 0x3c000000+4*0x20008, .val = 0x2ee},
  77 + { .reg = 0x3c000000+4*0x20088, .val = 0x9},
  78 + { .reg = 0x3c000000+4*0x200b2, .val = 0x1d4},
  79 + { .reg = 0x3c000000+4*0x10043, .val = 0x5a1},
  80 + { .reg = 0x3c000000+4*0x10143, .val = 0x5a1},
  81 + { .reg = 0x3c000000+4*0x11043, .val = 0x5a1},
  82 + { .reg = 0x3c000000+4*0x11143, .val = 0x5a1},
  83 + { .reg = 0x3c000000+4*0x12043, .val = 0x5a1},
  84 + { .reg = 0x3c000000+4*0x12143, .val = 0x5a1},
  85 + { .reg = 0x3c000000+4*0x13043, .val = 0x5a1},
  86 + { .reg = 0x3c000000+4*0x13143, .val = 0x5a1},
  87 + { .reg = 0x3c000000+4*0x200fa, .val = 0x1},
  88 + { .reg = 0x3c000000+4*0x20019, .val = 0x1},
  89 + { .reg = 0x3c000000+4*0x200f0, .val = 0x600},
  90 + { .reg = 0x3c000000+4*0x200f1, .val = 0x0},
  91 + { .reg = 0x3c000000+4*0x200f2, .val = 0x4444},
  92 + { .reg = 0x3c000000+4*0x200f3, .val = 0x8888},
  93 + { .reg = 0x3c000000+4*0x200f4, .val = 0x5655},
  94 + { .reg = 0x3c000000+4*0x200f5, .val = 0x0},
  95 + { .reg = 0x3c000000+4*0x200f6, .val = 0x0},
  96 + { .reg = 0x3c000000+4*0x200f7, .val = 0xf000},
  97 + { .reg = 0x3c000000+4*0x20025, .val = 0x0},
  98 + { .reg = 0x3c000000+4*0x2002d, .val = 0x0},
  99 + { .reg = 0x3c000000+4*0x200c7, .val = 0x21},
  100 + { .reg = 0x3c000000+4*0x200ca, .val = 0x24},
  101 + { .reg = 0x3c000000+4*0x20060, .val = 0x2},
  102 + { .reg = 0x3c000000+4*0xd0000, .val = 0x0},
  103 + { .reg = 0x3c000000+4*0xd0000, .val = 0x1},
  104 +
  105 + { .reg = DDR_PHY_FLAG_ADDR, .val = 0x00},
  106 +
  107 + { .reg = 0x3c000000+4*0xd0000, .val = 0x0},
  108 + { .reg = DDR_PHY_FLAG_ADDR, .val = 0x01},
  109 + { .reg = 0x3c000000+4*0xd0000, .val = 0x0},
  110 +#ifdef RUN_ON_SILICON
  111 + { .reg = 0x3c000000+4*0x54000, .val = 0x0},
  112 +#else
  113 + { .reg = 0x3c000000+4*0x54000, .val = 0x600},
  114 +#endif
  115 + { .reg = 0x3c000000+4*0x54001, .val = 0x0},
  116 + { .reg = 0x3c000000+4*0x54002, .val = 0x0},
  117 + { .reg = 0x3c000000+4*0x54003, .val = 0xbb8},
  118 + { .reg = 0x3c000000+4*0x54004, .val = 0x2},
  119 + { .reg = 0x3c000000+4*0x54005, .val = ((LPDDR4_PHY_RON<<8)|LPDDR4_PHY_RTT)},
  120 + { .reg = 0x3c000000+4*0x54006, .val = LPDDR4_PHY_VREF_VALUE},
  121 + { .reg = 0x3c000000+4*0x54007, .val = 0x0},
  122 +#ifdef RUN_ON_SILICON
  123 + { .reg = 0x3c000000+4*0x54008, .val = 0x131f},
  124 +#else
  125 + { .reg = 0x3c000000+4*0x54008, .val = 0x7},
  126 +#endif
  127 + { .reg = 0x3c000000+4*0x54009, .val = 0xc8},
  128 + { .reg = 0x3c000000+4*0x5400a, .val = 0x0},
  129 + { .reg = 0x3c000000+4*0x5400b, .val = 0x2},
  130 + { .reg = 0x3c000000+4*0x5400c, .val = 0x0},
  131 + { .reg = 0x3c000000+4*0x5400d, .val = 0x100},
  132 + { .reg = 0x3c000000+4*0x5400e, .val = 0x0},
  133 + { .reg = 0x3c000000+4*0x5400f, .val = 0x0},
  134 + { .reg = 0x3c000000+4*0x54010, .val = 0x0},
  135 + { .reg = 0x3c000000+4*0x54011, .val = 0x0},
  136 +#ifdef DDR_ONE_RANK
  137 + { .reg = 0x3c000000+4*0x54012, .val = 0x110},
  138 +#else
  139 + { .reg = 0x3c000000+4*0x54012, .val = 0x310},
  140 +#endif
  141 + { .reg = 0x3c000000+4*0x54013, .val = 0x0},
  142 + { .reg = 0x3c000000+4*0x54014, .val = 0x0},
  143 + { .reg = 0x3c000000+4*0x54015, .val = 0x0},
  144 + { .reg = 0x3c000000+4*0x54016, .val = 0x0},
  145 + { .reg = 0x3c000000+4*0x54017, .val = 0x0},
  146 + { .reg = 0x3c000000+4*0x54018, .val = 0x0},
  147 +
  148 + { .reg = 0x3c000000+4*0x54019, .val = 0x2dd4},
  149 + { .reg = 0x3c000000+4*0x5401a, .val = (((LPDDR4_RON)<<3)|LPDDR4_MR3_PU_CAL)/*0x31*/},
  150 + { .reg = 0x3c000000+4*0x5401b, .val = ((LPDDR4_VREF_VALUE_CA<<8)|(LPDDR4_RTT_CA_BANK0<<4)|LPDDR4_RTT_DQ)/*0x4d66*/},
  151 + { .reg = 0x3c000000+4*0x5401c, .val = ((LPDDR4_VREF_VALUE_DQ_RANK0<<8)|0x08)/*0x4d08*/},
  152 + { .reg = 0x3c000000+4*0x5401d, .val = 0x0},
  153 + { .reg = 0x3c000000+4*0x5401e, .val = LPDDR4_MR22_RANK0/*0x16*/},
  154 + { .reg = 0x3c000000+4*0x5401f, .val = 0x2dd4},
  155 + { .reg = 0x3c000000+4*0x54020, .val = (((LPDDR4_RON)<<3)|LPDDR4_MR3_PU_CAL)/*0x31*/},
  156 + { .reg = 0x3c000000+4*0x54021, .val = ((LPDDR4_VREF_VALUE_CA<<8)|(LPDDR4_RTT_CA_BANK1<<4)|LPDDR4_RTT_DQ)/*0x4d66*/},
  157 + { .reg = 0x3c000000+4*0x54022, .val = ((LPDDR4_VREF_VALUE_DQ_RANK1<<8)|0x08)/*0x4d08*/},
  158 + { .reg = 0x3c000000+4*0x54023, .val = 0x0},
  159 + { .reg = 0x3c000000+4*0x54024, .val = LPDDR4_MR22_RANK1/*0x16*/},
  160 +
  161 + { .reg = 0x3c000000+4*0x54025, .val = 0x0},
  162 + { .reg = 0x3c000000+4*0x54026, .val = 0x0},
  163 + { .reg = 0x3c000000+4*0x54027, .val = 0x0},
  164 + { .reg = 0x3c000000+4*0x54028, .val = 0x0},
  165 + { .reg = 0x3c000000+4*0x54029, .val = 0x0},
  166 + { .reg = 0x3c000000+4*0x5402a, .val = 0x0},
  167 + { .reg = 0x3c000000+4*0x5402b, .val = 0x1000},
  168 +#ifdef DDR_ONE_RANK
  169 + { .reg = 0x3c000000+4*0x5402c, .val = 0x1},
  170 +#else
  171 + { .reg = 0x3c000000+4*0x5402c, .val = 0x3},
  172 +#endif
  173 + { .reg = 0x3c000000+4*0x5402d, .val = 0x0},
  174 + { .reg = 0x3c000000+4*0x5402e, .val = 0x0},
  175 + { .reg = 0x3c000000+4*0x5402f, .val = 0x0},
  176 + { .reg = 0x3c000000+4*0x54030, .val = 0x0},
  177 + { .reg = 0x3c000000+4*0x54031, .val = 0x0},
  178 +
  179 + { .reg = 0x3c000000+4*0x54032, .val = 0xd400},
  180 + { .reg = 0x3c000000+4*0x54033, .val = ((((LPDDR4_RON)<<3)|LPDDR4_MR3_PU_CAL)<<8)|0x2d/*0x312d*/},
  181 + { .reg = 0x3c000000+4*0x54034, .val = (((LPDDR4_RTT_CA_BANK0<<4)|LPDDR4_RTT_DQ)<<8)/*0x4600*/},
  182 + { .reg = 0x3c000000+4*0x54035, .val = (0x0800|LPDDR4_VREF_VALUE_CA)/*0x084d*/},
  183 + { .reg = 0x3c000000+4*0x54036, .val = LPDDR4_VREF_VALUE_DQ_RANK0/*0x4d*/},
  184 + { .reg = 0x3c000000+4*0x54037, .val = (LPDDR4_MR22_RANK0<<8)/*0x1600*/},
  185 + { .reg = 0x3c000000+4*0x54038, .val = 0xd400},
  186 + { .reg = 0x3c000000+4*0x54039, .val = ((((LPDDR4_RON)<<3)|LPDDR4_MR3_PU_CAL)<<8)|0x2d/*0x312d*/},
  187 + { .reg = 0x3c000000+4*0x5403a, .val = (((LPDDR4_RTT_CA_BANK1<<4)|LPDDR4_RTT_DQ)<<8)/*0x4600*/},
  188 + { .reg = 0x3c000000+4*0x5403b, .val = (0x0800|LPDDR4_VREF_VALUE_CA)/*0x084d*/},
  189 + { .reg = 0x3c000000+4*0x5403c, .val = LPDDR4_VREF_VALUE_DQ_RANK1/*0x4d*/},
  190 + { .reg = 0x3c000000+4*0x5403d, .val = (LPDDR4_MR22_RANK1<<8)/*0x1600*/},
  191 + { .reg = 0x3c000000+4*0xd0000, .val = 0x1},
  192 + { .reg = 0x3c000000+4*0xd0000, .val = 0x1},
  193 + { .reg = 0x3c000000+4*0xd0099, .val = 0x9},
  194 + { .reg = 0x3c000000+4*0xd0099, .val = 0x1},
  195 + { .reg = 0x3c000000+4*0xd0099, .val = 0x0},
  196 +
  197 + { .reg = DDR_PHY_FLAG_ADDR, .val = 0x02},
  198 +
  199 + { .reg = 0x3c000000+4*0xd0099, .val = 0x1},
  200 + { .reg = 0x3c000000+4*0xd0000, .val = 0x0},
  201 +
  202 + { .reg = DDR_PHY_FLAG_ADDR, .val = 0x03},
  203 +
  204 + { .reg = 0x3c000000+4*0xd0000, .val = 0x1},
  205 +
  206 + { .reg = DDR_PHY_FLAG_ADDR, .val = 0x04},
  207 +
  208 + { .reg = 0x3c000000+4*0xd0000, .val = 0x0},
  209 + { .reg = 0x3c000000+4*0xd0000, .val = 0x1},
  210 +
  211 +
  212 +
  213 + { .reg = 0x3c000000+4*0xd0000, .val = 0x0},
  214 +
  215 + { .reg = DDR_PHY_FLAG_ADDR, .val = 0x05},
  216 +
  217 +
  218 + { .reg = 0x3c000000+4*0xd0000, .val = 0x0},
  219 +#ifdef RUN_ON_SILICON
  220 + { .reg = 0x3c000000+4*0x54000, .val = 0x0},
  221 +#else
  222 + { .reg = 0x3c000000+4*0x54000, .val = 0x600},
  223 +#endif
  224 + { .reg = 0x3c000000+4*0x54001, .val = 0x0},
  225 + { .reg = 0x3c000000+4*0x54002, .val = 0x0},
  226 + { .reg = 0x3c000000+4*0x54003, .val = 0xbb8},
  227 + { .reg = 0x3c000000+4*0x54004, .val = 0x2},
  228 +
  229 + { .reg = 0x3c000000+4*0x54005, .val = ((LPDDR4_PHY_RON<<8)|LPDDR4_PHY_RTT)},
  230 + { .reg = 0x3c000000+4*0x54006, .val = LPDDR4_PHY_VREF_VALUE},
  231 +
  232 + { .reg = 0x3c000000+4*0x54007, .val = 0x0},
  233 +#ifdef RUN_ON_SILICON
  234 + { .reg = 0x3c000000+4*0x54008, .val = 0x61},
  235 +#else
  236 + { .reg = 0x3c000000+4*0x54008, .val = 0x1},
  237 +#endif
  238 + { .reg = 0x3c000000+4*0x54009, .val = 0xc8},
  239 + { .reg = 0x3c000000+4*0x5400a, .val = 0x0},
  240 + { .reg = 0x3c000000+4*0x5400b, .val = 0x2},
  241 + { .reg = 0x3c000000+4*0x5400c, .val = 0x0},
  242 + { .reg = 0x3c000000+4*0x5400d, .val = 0x100},
  243 + { .reg = 0x3c000000+4*0x5400e, .val = 0x0},
  244 + { .reg = 0x3c000000+4*0x5400f, .val = 0x100},
  245 +
  246 + { .reg = 0x3c000000+4*0x54010, .val = LPDDR4_2D_WEIGHT},
  247 +
  248 + { .reg = 0x3c000000+4*0x54011, .val = 0x0},
  249 +#ifdef DDR_ONE_RANK
  250 + { .reg = 0x3c000000+4*0x54012, .val = 0x110},
  251 +#else
  252 + { .reg = 0x3c000000+4*0x54012, .val = 0x310},
  253 +#endif
  254 + { .reg = 0x3c000000+4*0x54013, .val = 0x0},
  255 + { .reg = 0x3c000000+4*0x54014, .val = 0x0},
  256 + { .reg = 0x3c000000+4*0x54015, .val = 0x0},
  257 + { .reg = 0x3c000000+4*0x54016, .val = 0x0},
  258 + { .reg = 0x3c000000+4*0x54017, .val = 0x0},
  259 + { .reg = 0x3c000000+4*0x54018, .val = 0x0},
  260 +
  261 + { .reg = 0x3c000000+4*0x54019, .val = 0x2dd4},
  262 + { .reg = 0x3c000000+4*0x5401a, .val = (((LPDDR4_RON)<<3)|LPDDR4_MR3_PU_CAL)/*0x31*/},
  263 + { .reg = 0x3c000000+4*0x5401b, .val = ((LPDDR4_VREF_VALUE_CA<<8)|(LPDDR4_RTT_CA_BANK0<<4)|LPDDR4_RTT_DQ)/*0x4d46*/},
  264 + { .reg = 0x3c000000+4*0x5401c, .val = ((LPDDR4_VREF_VALUE_DQ_RANK0<<8)|0x08)/*0x4d08*/},
  265 + { .reg = 0x3c000000+4*0x5401d, .val = 0x0},
  266 + { .reg = 0x3c000000+4*0x5401e, .val = LPDDR4_MR22_RANK0/*0x16*/},
  267 + { .reg = 0x3c000000+4*0x5401f, .val = 0x2dd4},
  268 + { .reg = 0x3c000000+4*0x54020, .val = (((LPDDR4_RON)<<3)|LPDDR4_MR3_PU_CAL)/*0x31*/},
  269 + { .reg = 0x3c000000+4*0x54021, .val = ((LPDDR4_VREF_VALUE_CA<<8)|(LPDDR4_RTT_CA_BANK1<<4)|LPDDR4_RTT_DQ)/*0x4d46*/},
  270 + { .reg = 0x3c000000+4*0x54022, .val = ((LPDDR4_VREF_VALUE_DQ_RANK1<<8)|0x08)/*0x4d08*/},
  271 + { .reg = 0x3c000000+4*0x54023, .val = 0x0},
  272 + { .reg = 0x3c000000+4*0x54024, .val = LPDDR4_MR22_RANK1/*0x16*/},
  273 +
  274 + { .reg = 0x3c000000+4*0x54025, .val = 0x0},
  275 + { .reg = 0x3c000000+4*0x54026, .val = 0x0},
  276 + { .reg = 0x3c000000+4*0x54027, .val = 0x0},
  277 + { .reg = 0x3c000000+4*0x54028, .val = 0x0},
  278 + { .reg = 0x3c000000+4*0x54029, .val = 0x0},
  279 + { .reg = 0x3c000000+4*0x5402a, .val = 0x0},
  280 + { .reg = 0x3c000000+4*0x5402b, .val = 0x1000},
  281 +#ifdef DDR_ONE_RANK
  282 + { .reg = 0x3c000000+4*0x5402c, .val = 0x1},
  283 +#else
  284 + { .reg = 0x3c000000+4*0x5402c, .val = 0x3},
  285 +#endif
  286 + { .reg = 0x3c000000+4*0x5402d, .val = 0x0},
  287 + { .reg = 0x3c000000+4*0x5402e, .val = 0x0},
  288 + { .reg = 0x3c000000+4*0x5402f, .val = 0x0},
  289 + { .reg = 0x3c000000+4*0x54030, .val = 0x0},
  290 + { .reg = 0x3c000000+4*0x54031, .val = 0x0},
  291 +
  292 + { .reg = 0x3c000000+4*0x54032, .val = 0xd400},
  293 + { .reg = 0x3c000000+4*0x54033, .val = ((((LPDDR4_RON)<<3)|LPDDR4_MR3_PU_CAL)<<8)|0x2d/*0x312d*/},
  294 + { .reg = 0x3c000000+4*0x54034, .val = (((LPDDR4_RTT_CA_BANK0<<4)|LPDDR4_RTT_DQ)<<8)/*0x4600*/},
  295 + { .reg = 0x3c000000+4*0x54035, .val = (0x0800|LPDDR4_VREF_VALUE_CA)/*0x084d*/},
  296 + { .reg = 0x3c000000+4*0x54036, .val = LPDDR4_VREF_VALUE_DQ_RANK0/*0x4d*/},
  297 + { .reg = 0x3c000000+4*0x54037, .val = (LPDDR4_MR22_RANK0<<8)/*0x1600*/},
  298 + { .reg = 0x3c000000+4*0x54038, .val = 0xd400},
  299 + { .reg = 0x3c000000+4*0x54039, .val = ((((LPDDR4_RON)<<3)|LPDDR4_MR3_PU_CAL)<<8)|0x2d/*0x312d*/},
  300 + { .reg = 0x3c000000+4*0x5403a, .val = (((LPDDR4_RTT_CA_BANK1<<4)|LPDDR4_RTT_DQ)<<8)/*0x4600*/},
  301 + { .reg = 0x3c000000+4*0x5403b, .val = (0x0800|LPDDR4_VREF_VALUE_CA)/*0x084d*/},
  302 + { .reg = 0x3c000000+4*0x5403c, .val = LPDDR4_VREF_VALUE_DQ_RANK1/*0x4d*/},
  303 + { .reg = 0x3c000000+4*0x5403d, .val = (LPDDR4_MR22_RANK1<<8)/*0x1600*/},
  304 +
  305 + { .reg = 0x3c000000+4*0xd0000, .val = 0x1},
  306 + { .reg = 0x3c000000+4*0xd0000, .val = 0x1},
  307 + { .reg = 0x3c000000+4*0xd0099, .val = 0x9},
  308 + { .reg = 0x3c000000+4*0xd0099, .val = 0x1},
  309 + { .reg = 0x3c000000+4*0xd0099, .val = 0x0},
  310 +
  311 + { .reg = DDR_PHY_FLAG_ADDR, .val = 0x06},
  312 +
  313 + { .reg = 0x3c000000+4*0xd0099, .val = 0x1},
  314 + { .reg = 0x3c000000+4*0xd0000, .val = 0x0},
  315 +
  316 + { .reg = DDR_PHY_FLAG_ADDR, .val = 0x07},
  317 +
  318 + { .reg = 0x3c000000+4*0xd0000, .val = 0x1},
  319 +
  320 + { .reg = 0x3c000000+4*0xd0000, .val = 0x0},
  321 +
  322 + { .reg = 0x3c000000+4*0x90000, .val = 0x10},
  323 + { .reg = 0x3c000000+4*0x90001, .val = 0x400},
  324 + { .reg = 0x3c000000+4*0x90002, .val = 0x10e},
  325 + { .reg = 0x3c000000+4*0x90003, .val = 0x0},
  326 + { .reg = 0x3c000000+4*0x90004, .val = 0x0},
  327 + { .reg = 0x3c000000+4*0x90005, .val = 0x8},
  328 + { .reg = 0x3c000000+4*0x90029, .val = 0xb},
  329 + { .reg = 0x3c000000+4*0x9002a, .val = 0x480},
  330 + { .reg = 0x3c000000+4*0x9002b, .val = 0x109},
  331 + { .reg = 0x3c000000+4*0x9002c, .val = 0x8},
  332 + { .reg = 0x3c000000+4*0x9002d, .val = 0x448},
  333 + { .reg = 0x3c000000+4*0x9002e, .val = 0x139},
  334 + { .reg = 0x3c000000+4*0x9002f, .val = 0x8},
  335 + { .reg = 0x3c000000+4*0x90030, .val = 0x478},
  336 + { .reg = 0x3c000000+4*0x90031, .val = 0x109},
  337 + { .reg = 0x3c000000+4*0x90032, .val = 0x0},
  338 + { .reg = 0x3c000000+4*0x90033, .val = 0xe8},
  339 + { .reg = 0x3c000000+4*0x90034, .val = 0x109},
  340 + { .reg = 0x3c000000+4*0x90035, .val = 0x2},
  341 + { .reg = 0x3c000000+4*0x90036, .val = 0x10},
  342 + { .reg = 0x3c000000+4*0x90037, .val = 0x139},
  343 + { .reg = 0x3c000000+4*0x90038, .val = 0xf},
  344 + { .reg = 0x3c000000+4*0x90039, .val = 0x7c0},
  345 + { .reg = 0x3c000000+4*0x9003a, .val = 0x139},
  346 + { .reg = 0x3c000000+4*0x9003b, .val = 0x44},
  347 + { .reg = 0x3c000000+4*0x9003c, .val = 0x630},
  348 + { .reg = 0x3c000000+4*0x9003d, .val = 0x159},
  349 + { .reg = 0x3c000000+4*0x9003e, .val = 0x14f},
  350 + { .reg = 0x3c000000+4*0x9003f, .val = 0x630},
  351 + { .reg = 0x3c000000+4*0x90040, .val = 0x159},
  352 + { .reg = 0x3c000000+4*0x90041, .val = 0x47},
  353 + { .reg = 0x3c000000+4*0x90042, .val = 0x630},
  354 + { .reg = 0x3c000000+4*0x90043, .val = 0x149},
  355 + { .reg = 0x3c000000+4*0x90044, .val = 0x4f},
  356 + { .reg = 0x3c000000+4*0x90045, .val = 0x630},
  357 + { .reg = 0x3c000000+4*0x90046, .val = 0x179},
  358 + { .reg = 0x3c000000+4*0x90047, .val = 0x8},
  359 + { .reg = 0x3c000000+4*0x90048, .val = 0xe0},
  360 + { .reg = 0x3c000000+4*0x90049, .val = 0x109},
  361 + { .reg = 0x3c000000+4*0x9004a, .val = 0x0},
  362 + { .reg = 0x3c000000+4*0x9004b, .val = 0x7c8},
  363 + { .reg = 0x3c000000+4*0x9004c, .val = 0x109},
  364 + { .reg = 0x3c000000+4*0x9004d, .val = 0x0},
  365 + { .reg = 0x3c000000+4*0x9004e, .val = 0x1},
  366 + { .reg = 0x3c000000+4*0x9004f, .val = 0x8},
  367 + { .reg = 0x3c000000+4*0x90050, .val = 0x0},
  368 + { .reg = 0x3c000000+4*0x90051, .val = 0x45a},
  369 + { .reg = 0x3c000000+4*0x90052, .val = 0x9},
  370 + { .reg = 0x3c000000+4*0x90053, .val = 0x0},
  371 + { .reg = 0x3c000000+4*0x90054, .val = 0x448},
  372 + { .reg = 0x3c000000+4*0x90055, .val = 0x109},
  373 + { .reg = 0x3c000000+4*0x90056, .val = 0x40},
  374 + { .reg = 0x3c000000+4*0x90057, .val = 0x630},
  375 + { .reg = 0x3c000000+4*0x90058, .val = 0x179},
  376 + { .reg = 0x3c000000+4*0x90059, .val = 0x1},
  377 + { .reg = 0x3c000000+4*0x9005a, .val = 0x618},
  378 + { .reg = 0x3c000000+4*0x9005b, .val = 0x109},
  379 + { .reg = 0x3c000000+4*0x9005c, .val = 0x40c0},
  380 + { .reg = 0x3c000000+4*0x9005d, .val = 0x630},
  381 + { .reg = 0x3c000000+4*0x9005e, .val = 0x149},
  382 + { .reg = 0x3c000000+4*0x9005f, .val = 0x8},
  383 + { .reg = 0x3c000000+4*0x90060, .val = 0x4},
  384 + { .reg = 0x3c000000+4*0x90061, .val = 0x48},
  385 + { .reg = 0x3c000000+4*0x90062, .val = 0x4040},
  386 + { .reg = 0x3c000000+4*0x90063, .val = 0x630},
  387 + { .reg = 0x3c000000+4*0x90064, .val = 0x149},
  388 + { .reg = 0x3c000000+4*0x90065, .val = 0x0},
  389 + { .reg = 0x3c000000+4*0x90066, .val = 0x4},
  390 + { .reg = 0x3c000000+4*0x90067, .val = 0x48},
  391 + { .reg = 0x3c000000+4*0x90068, .val = 0x40},
  392 + { .reg = 0x3c000000+4*0x90069, .val = 0x630},
  393 + { .reg = 0x3c000000+4*0x9006a, .val = 0x149},
  394 + { .reg = 0x3c000000+4*0x9006b, .val = 0x10},
  395 + { .reg = 0x3c000000+4*0x9006c, .val = 0x4},
  396 + { .reg = 0x3c000000+4*0x9006d, .val = 0x18},
  397 + { .reg = 0x3c000000+4*0x9006e, .val = 0x0},
  398 + { .reg = 0x3c000000+4*0x9006f, .val = 0x4},
  399 + { .reg = 0x3c000000+4*0x90070, .val = 0x78},
  400 + { .reg = 0x3c000000+4*0x90071, .val = 0x549},
  401 + { .reg = 0x3c000000+4*0x90072, .val = 0x630},
  402 + { .reg = 0x3c000000+4*0x90073, .val = 0x159},
  403 + { .reg = 0x3c000000+4*0x90074, .val = 0xd49},
  404 + { .reg = 0x3c000000+4*0x90075, .val = 0x630},
  405 + { .reg = 0x3c000000+4*0x90076, .val = 0x159},
  406 + { .reg = 0x3c000000+4*0x90077, .val = 0x94a},
  407 + { .reg = 0x3c000000+4*0x90078, .val = 0x630},
  408 + { .reg = 0x3c000000+4*0x90079, .val = 0x159},
  409 + { .reg = 0x3c000000+4*0x9007a, .val = 0x441},
  410 + { .reg = 0x3c000000+4*0x9007b, .val = 0x630},
  411 + { .reg = 0x3c000000+4*0x9007c, .val = 0x149},
  412 + { .reg = 0x3c000000+4*0x9007d, .val = 0x42},
  413 + { .reg = 0x3c000000+4*0x9007e, .val = 0x630},
  414 + { .reg = 0x3c000000+4*0x9007f, .val = 0x149},
  415 + { .reg = 0x3c000000+4*0x90080, .val = 0x1},
  416 + { .reg = 0x3c000000+4*0x90081, .val = 0x630},
  417 + { .reg = 0x3c000000+4*0x90082, .val = 0x149},
  418 + { .reg = 0x3c000000+4*0x90083, .val = 0x0},
  419 + { .reg = 0x3c000000+4*0x90084, .val = 0xe0},
  420 + { .reg = 0x3c000000+4*0x90085, .val = 0x109},
  421 + { .reg = 0x3c000000+4*0x90086, .val = 0xa},
  422 + { .reg = 0x3c000000+4*0x90087, .val = 0x10},
  423 + { .reg = 0x3c000000+4*0x90088, .val = 0x109},
  424 + { .reg = 0x3c000000+4*0x90089, .val = 0x9},
  425 + { .reg = 0x3c000000+4*0x9008a, .val = 0x3c0},
  426 + { .reg = 0x3c000000+4*0x9008b, .val = 0x149},
  427 + { .reg = 0x3c000000+4*0x9008c, .val = 0x9},
  428 + { .reg = 0x3c000000+4*0x9008d, .val = 0x3c0},
  429 + { .reg = 0x3c000000+4*0x9008e, .val = 0x159},
  430 + { .reg = 0x3c000000+4*0x9008f, .val = 0x18},
  431 + { .reg = 0x3c000000+4*0x90090, .val = 0x10},
  432 + { .reg = 0x3c000000+4*0x90091, .val = 0x109},
  433 + { .reg = 0x3c000000+4*0x90092, .val = 0x0},
  434 + { .reg = 0x3c000000+4*0x90093, .val = 0x3c0},
  435 + { .reg = 0x3c000000+4*0x90094, .val = 0x109},
  436 + { .reg = 0x3c000000+4*0x90095, .val = 0x18},
  437 + { .reg = 0x3c000000+4*0x90096, .val = 0x4},
  438 + { .reg = 0x3c000000+4*0x90097, .val = 0x48},
  439 + { .reg = 0x3c000000+4*0x90098, .val = 0x18},
  440 + { .reg = 0x3c000000+4*0x90099, .val = 0x4},
  441 + { .reg = 0x3c000000+4*0x9009a, .val = 0x58},
  442 + { .reg = 0x3c000000+4*0x9009b, .val = 0xa},
  443 + { .reg = 0x3c000000+4*0x9009c, .val = 0x10},
  444 + { .reg = 0x3c000000+4*0x9009d, .val = 0x109},
  445 + { .reg = 0x3c000000+4*0x9009e, .val = 0x2},
  446 + { .reg = 0x3c000000+4*0x9009f, .val = 0x10},
  447 + { .reg = 0x3c000000+4*0x900a0, .val = 0x109},
  448 + { .reg = 0x3c000000+4*0x900a1, .val = 0x5},
  449 + { .reg = 0x3c000000+4*0x900a2, .val = 0x7c0},
  450 + { .reg = 0x3c000000+4*0x900a3, .val = 0x109},
  451 + { .reg = 0x3c000000+4*0x900a4, .val = 0x10},
  452 + { .reg = 0x3c000000+4*0x900a5, .val = 0x10},
  453 + { .reg = 0x3c000000+4*0x900a6, .val = 0x109},
  454 + { .reg = 0x3c000000+4*0x40000, .val = 0x811},
  455 + { .reg = 0x3c000000+4*0x40020, .val = 0x880},
  456 + { .reg = 0x3c000000+4*0x40040, .val = 0x0},
  457 + { .reg = 0x3c000000+4*0x40060, .val = 0x0},
  458 + { .reg = 0x3c000000+4*0x40001, .val = 0x4008},
  459 + { .reg = 0x3c000000+4*0x40021, .val = 0x83},
  460 + { .reg = 0x3c000000+4*0x40041, .val = 0x4f},
  461 + { .reg = 0x3c000000+4*0x40061, .val = 0x0},
  462 + { .reg = 0x3c000000+4*0x40002, .val = 0x4040},
  463 + { .reg = 0x3c000000+4*0x40022, .val = 0x83},
  464 + { .reg = 0x3c000000+4*0x40042, .val = 0x51},
  465 + { .reg = 0x3c000000+4*0x40062, .val = 0x0},
  466 + { .reg = 0x3c000000+4*0x40003, .val = 0x811},
  467 + { .reg = 0x3c000000+4*0x40023, .val = 0x880},
  468 + { .reg = 0x3c000000+4*0x40043, .val = 0x0},
  469 + { .reg = 0x3c000000+4*0x40063, .val = 0x0},
  470 + { .reg = 0x3c000000+4*0x40004, .val = 0x720},
  471 + { .reg = 0x3c000000+4*0x40024, .val = 0xf},
  472 + { .reg = 0x3c000000+4*0x40044, .val = 0x1740},
  473 + { .reg = 0x3c000000+4*0x40064, .val = 0x0},
  474 + { .reg = 0x3c000000+4*0x40005, .val = 0x16},
  475 + { .reg = 0x3c000000+4*0x40025, .val = 0x83},
  476 + { .reg = 0x3c000000+4*0x40045, .val = 0x4b},
  477 + { .reg = 0x3c000000+4*0x40065, .val = 0x0},
  478 + { .reg = 0x3c000000+4*0x40006, .val = 0x716},
  479 + { .reg = 0x3c000000+4*0x40026, .val = 0xf},
  480 + { .reg = 0x3c000000+4*0x40046, .val = 0x2001},
  481 + { .reg = 0x3c000000+4*0x40066, .val = 0x0},
  482 + { .reg = 0x3c000000+4*0x40007, .val = 0x716},
  483 + { .reg = 0x3c000000+4*0x40027, .val = 0xf},
  484 + { .reg = 0x3c000000+4*0x40047, .val = 0x2800},
  485 + { .reg = 0x3c000000+4*0x40067, .val = 0x0},
  486 + { .reg = 0x3c000000+4*0x40008, .val = 0x716},
  487 + { .reg = 0x3c000000+4*0x40028, .val = 0xf},
  488 + { .reg = 0x3c000000+4*0x40048, .val = 0xf00},
  489 + { .reg = 0x3c000000+4*0x40068, .val = 0x0},
  490 + { .reg = 0x3c000000+4*0x40009, .val = 0x720},
  491 + { .reg = 0x3c000000+4*0x40029, .val = 0xf},
  492 + { .reg = 0x3c000000+4*0x40049, .val = 0x1400},
  493 + { .reg = 0x3c000000+4*0x40069, .val = 0x0},
  494 + { .reg = 0x3c000000+4*0x4000a, .val = 0xe08},
  495 + { .reg = 0x3c000000+4*0x4002a, .val = 0xc15},
  496 + { .reg = 0x3c000000+4*0x4004a, .val = 0x0},
  497 + { .reg = 0x3c000000+4*0x4006a, .val = 0x0},
  498 + { .reg = 0x3c000000+4*0x4000b, .val = 0x623},
  499 + { .reg = 0x3c000000+4*0x4002b, .val = 0x15},
  500 + { .reg = 0x3c000000+4*0x4004b, .val = 0x0},
  501 + { .reg = 0x3c000000+4*0x4006b, .val = 0x0},
  502 + { .reg = 0x3c000000+4*0x4000c, .val = 0x4028},
  503 + { .reg = 0x3c000000+4*0x4002c, .val = 0x80},
  504 + { .reg = 0x3c000000+4*0x4004c, .val = 0x0},
  505 + { .reg = 0x3c000000+4*0x4006c, .val = 0x0},
  506 + { .reg = 0x3c000000+4*0x4000d, .val = 0xe08},
  507 + { .reg = 0x3c000000+4*0x4002d, .val = 0xc1a},
  508 + { .reg = 0x3c000000+4*0x4004d, .val = 0x0},
  509 + { .reg = 0x3c000000+4*0x4006d, .val = 0x0},
  510 + { .reg = 0x3c000000+4*0x4000e, .val = 0x623},
  511 + { .reg = 0x3c000000+4*0x4002e, .val = 0x1a},
  512 + { .reg = 0x3c000000+4*0x4004e, .val = 0x0},
  513 + { .reg = 0x3c000000+4*0x4006e, .val = 0x0},
  514 + { .reg = 0x3c000000+4*0x4000f, .val = 0x4040},
  515 + { .reg = 0x3c000000+4*0x4002f, .val = 0x80},
  516 + { .reg = 0x3c000000+4*0x4004f, .val = 0x0},
  517 + { .reg = 0x3c000000+4*0x4006f, .val = 0x0},
  518 + { .reg = 0x3c000000+4*0x40010, .val = 0x2604},
  519 + { .reg = 0x3c000000+4*0x40030, .val = 0x15},
  520 + { .reg = 0x3c000000+4*0x40050, .val = 0x0},
  521 + { .reg = 0x3c000000+4*0x40070, .val = 0x0},
  522 + { .reg = 0x3c000000+4*0x40011, .val = 0x708},
  523 + { .reg = 0x3c000000+4*0x40031, .val = 0x5},
  524 + { .reg = 0x3c000000+4*0x40051, .val = 0x0},
  525 + { .reg = 0x3c000000+4*0x40071, .val = 0x2002},
  526 + { .reg = 0x3c000000+4*0x40012, .val = 0x8},
  527 + { .reg = 0x3c000000+4*0x40032, .val = 0x80},
  528 + { .reg = 0x3c000000+4*0x40052, .val = 0x0},
  529 + { .reg = 0x3c000000+4*0x40072, .val = 0x0},
  530 + { .reg = 0x3c000000+4*0x40013, .val = 0x2604},
  531 + { .reg = 0x3c000000+4*0x40033, .val = 0x1a},
  532 + { .reg = 0x3c000000+4*0x40053, .val = 0x0},
  533 + { .reg = 0x3c000000+4*0x40073, .val = 0x0},
  534 + { .reg = 0x3c000000+4*0x40014, .val = 0x708},
  535 + { .reg = 0x3c000000+4*0x40034, .val = 0xa},
  536 + { .reg = 0x3c000000+4*0x40054, .val = 0x0},
  537 + { .reg = 0x3c000000+4*0x40074, .val = 0x2002},
  538 + { .reg = 0x3c000000+4*0x40015, .val = 0x4040},
  539 + { .reg = 0x3c000000+4*0x40035, .val = 0x80},
  540 + { .reg = 0x3c000000+4*0x40055, .val = 0x0},
  541 + { .reg = 0x3c000000+4*0x40075, .val = 0x0},
  542 + { .reg = 0x3c000000+4*0x40016, .val = 0x60a},
  543 + { .reg = 0x3c000000+4*0x40036, .val = 0x15},
  544 + { .reg = 0x3c000000+4*0x40056, .val = 0x1200},
  545 + { .reg = 0x3c000000+4*0x40076, .val = 0x0},
  546 + { .reg = 0x3c000000+4*0x40017, .val = 0x61a},
  547 + { .reg = 0x3c000000+4*0x40037, .val = 0x15},
  548 + { .reg = 0x3c000000+4*0x40057, .val = 0x1300},
  549 + { .reg = 0x3c000000+4*0x40077, .val = 0x0},
  550 + { .reg = 0x3c000000+4*0x40018, .val = 0x60a},
  551 + { .reg = 0x3c000000+4*0x40038, .val = 0x1a},
  552 + { .reg = 0x3c000000+4*0x40058, .val = 0x1200},
  553 + { .reg = 0x3c000000+4*0x40078, .val = 0x0},
  554 + { .reg = 0x3c000000+4*0x40019, .val = 0x642},
  555 + { .reg = 0x3c000000+4*0x40039, .val = 0x1a},
  556 + { .reg = 0x3c000000+4*0x40059, .val = 0x1300},
  557 + { .reg = 0x3c000000+4*0x40079, .val = 0x0},
  558 + { .reg = 0x3c000000+4*0x4001a, .val = 0x4808},
  559 + { .reg = 0x3c000000+4*0x4003a, .val = 0x880},
  560 + { .reg = 0x3c000000+4*0x4005a, .val = 0x0},
  561 + { .reg = 0x3c000000+4*0x4007a, .val = 0x0},
  562 + { .reg = 0x3c000000+4*0x900a7, .val = 0x0},
  563 + { .reg = 0x3c000000+4*0x900a8, .val = 0x790},
  564 + { .reg = 0x3c000000+4*0x900a9, .val = 0x11a},
  565 + { .reg = 0x3c000000+4*0x900aa, .val = 0x8},
  566 + { .reg = 0x3c000000+4*0x900ab, .val = 0x7aa},
  567 + { .reg = 0x3c000000+4*0x900ac, .val = 0x2a},
  568 + { .reg = 0x3c000000+4*0x900ad, .val = 0x10},
  569 + { .reg = 0x3c000000+4*0x900ae, .val = 0x7b2},
  570 + { .reg = 0x3c000000+4*0x900af, .val = 0x2a},
  571 + { .reg = 0x3c000000+4*0x900b0, .val = 0x0},
  572 + { .reg = 0x3c000000+4*0x900b1, .val = 0x7c8},
  573 + { .reg = 0x3c000000+4*0x900b2, .val = 0x109},
  574 + { .reg = 0x3c000000+4*0x900b3, .val = 0x10},
  575 + { .reg = 0x3c000000+4*0x900b4, .val = 0x2a8},
  576 + { .reg = 0x3c000000+4*0x900b5, .val = 0x129},
  577 + { .reg = 0x3c000000+4*0x900b6, .val = 0x8},
  578 + { .reg = 0x3c000000+4*0x900b7, .val = 0x370},
  579 + { .reg = 0x3c000000+4*0x900b8, .val = 0x129},
  580 + { .reg = 0x3c000000+4*0x900b9, .val = 0xa},
  581 + { .reg = 0x3c000000+4*0x900ba, .val = 0x3c8},
  582 + { .reg = 0x3c000000+4*0x900bb, .val = 0x1a9},
  583 + { .reg = 0x3c000000+4*0x900bc, .val = 0xc},
  584 + { .reg = 0x3c000000+4*0x900bd, .val = 0x408},
  585 + { .reg = 0x3c000000+4*0x900be, .val = 0x199},
  586 + { .reg = 0x3c000000+4*0x900bf, .val = 0x14},
  587 + { .reg = 0x3c000000+4*0x900c0, .val = 0x790},
  588 + { .reg = 0x3c000000+4*0x900c1, .val = 0x11a},
  589 + { .reg = 0x3c000000+4*0x900c2, .val = 0x8},
  590 + { .reg = 0x3c000000+4*0x900c3, .val = 0x4},
  591 + { .reg = 0x3c000000+4*0x900c4, .val = 0x18},
  592 + { .reg = 0x3c000000+4*0x900c5, .val = 0xe},
  593 + { .reg = 0x3c000000+4*0x900c6, .val = 0x408},
  594 + { .reg = 0x3c000000+4*0x900c7, .val = 0x199},
  595 + { .reg = 0x3c000000+4*0x900c8, .val = 0x8},
  596 + { .reg = 0x3c000000+4*0x900c9, .val = 0x8568},
  597 + { .reg = 0x3c000000+4*0x900ca, .val = 0x108},
  598 + { .reg = 0x3c000000+4*0x900cb, .val = 0x18},
  599 + { .reg = 0x3c000000+4*0x900cc, .val = 0x790},
  600 + { .reg = 0x3c000000+4*0x900cd, .val = 0x16a},
  601 + { .reg = 0x3c000000+4*0x900ce, .val = 0x8},
  602 + { .reg = 0x3c000000+4*0x900cf, .val = 0x1d8},
  603 + { .reg = 0x3c000000+4*0x900d0, .val = 0x169},
  604 + { .reg = 0x3c000000+4*0x900d1, .val = 0x10},
  605 + { .reg = 0x3c000000+4*0x900d2, .val = 0x8558},
  606 + { .reg = 0x3c000000+4*0x900d3, .val = 0x168},
  607 + { .reg = 0x3c000000+4*0x900d4, .val = 0x70},
  608 + { .reg = 0x3c000000+4*0x900d5, .val = 0x788},
  609 + { .reg = 0x3c000000+4*0x900d6, .val = 0x16a},
  610 + { .reg = 0x3c000000+4*0x900d7, .val = 0x1ff8},
  611 + { .reg = 0x3c000000+4*0x900d8, .val = 0x85a8},
  612 + { .reg = 0x3c000000+4*0x900d9, .val = 0x1e8},
  613 + { .reg = 0x3c000000+4*0x900da, .val = 0x50},
  614 + { .reg = 0x3c000000+4*0x900db, .val = 0x798},
  615 + { .reg = 0x3c000000+4*0x900dc, .val = 0x16a},
  616 + { .reg = 0x3c000000+4*0x900dd, .val = 0x60},
  617 + { .reg = 0x3c000000+4*0x900de, .val = 0x7a0},
  618 + { .reg = 0x3c000000+4*0x900df, .val = 0x16a},
  619 + { .reg = 0x3c000000+4*0x900e0, .val = 0x8},
  620 + { .reg = 0x3c000000+4*0x900e1, .val = 0x8310},
  621 + { .reg = 0x3c000000+4*0x900e2, .val = 0x168},
  622 + { .reg = 0x3c000000+4*0x900e3, .val = 0x8},
  623 + { .reg = 0x3c000000+4*0x900e4, .val = 0xa310},
  624 + { .reg = 0x3c000000+4*0x900e5, .val = 0x168},
  625 + { .reg = 0x3c000000+4*0x900e6, .val = 0xa},
  626 + { .reg = 0x3c000000+4*0x900e7, .val = 0x408},
  627 + { .reg = 0x3c000000+4*0x900e8, .val = 0x169},
  628 + { .reg = 0x3c000000+4*0x900e9, .val = 0x6e},
  629 + { .reg = 0x3c000000+4*0x900ea, .val = 0x0},
  630 + { .reg = 0x3c000000+4*0x900eb, .val = 0x68},
  631 + { .reg = 0x3c000000+4*0x900ec, .val = 0x0},
  632 + { .reg = 0x3c000000+4*0x900ed, .val = 0x408},
  633 + { .reg = 0x3c000000+4*0x900ee, .val = 0x169},
  634 + { .reg = 0x3c000000+4*0x900ef, .val = 0x0},
  635 + { .reg = 0x3c000000+4*0x900f0, .val = 0x8310},
  636 + { .reg = 0x3c000000+4*0x900f1, .val = 0x168},
  637 + { .reg = 0x3c000000+4*0x900f2, .val = 0x0},
  638 + { .reg = 0x3c000000+4*0x900f3, .val = 0xa310},
  639 + { .reg = 0x3c000000+4*0x900f4, .val = 0x168},
  640 + { .reg = 0x3c000000+4*0x900f5, .val = 0x1ff8},
  641 + { .reg = 0x3c000000+4*0x900f6, .val = 0x85a8},
  642 + { .reg = 0x3c000000+4*0x900f7, .val = 0x1e8},
  643 + { .reg = 0x3c000000+4*0x900f8, .val = 0x68},
  644 + { .reg = 0x3c000000+4*0x900f9, .val = 0x798},
  645 + { .reg = 0x3c000000+4*0x900fa, .val = 0x16a},
  646 + { .reg = 0x3c000000+4*0x900fb, .val = 0x78},
  647 + { .reg = 0x3c000000+4*0x900fc, .val = 0x7a0},
  648 + { .reg = 0x3c000000+4*0x900fd, .val = 0x16a},
  649 + { .reg = 0x3c000000+4*0x900fe, .val = 0x68},
  650 + { .reg = 0x3c000000+4*0x900ff, .val = 0x790},
  651 + { .reg = 0x3c000000+4*0x90100, .val = 0x16a},
  652 + { .reg = 0x3c000000+4*0x90101, .val = 0x8},
  653 + { .reg = 0x3c000000+4*0x90102, .val = 0x8b10},
  654 + { .reg = 0x3c000000+4*0x90103, .val = 0x168},
  655 + { .reg = 0x3c000000+4*0x90104, .val = 0x8},
  656 + { .reg = 0x3c000000+4*0x90105, .val = 0xab10},
  657 + { .reg = 0x3c000000+4*0x90106, .val = 0x168},
  658 + { .reg = 0x3c000000+4*0x90107, .val = 0xa},
  659 + { .reg = 0x3c000000+4*0x90108, .val = 0x408},
  660 + { .reg = 0x3c000000+4*0x90109, .val = 0x169},
  661 + { .reg = 0x3c000000+4*0x9010a, .val = 0x58},
  662 + { .reg = 0x3c000000+4*0x9010b, .val = 0x0},
  663 + { .reg = 0x3c000000+4*0x9010c, .val = 0x68},
  664 + { .reg = 0x3c000000+4*0x9010d, .val = 0x0},
  665 + { .reg = 0x3c000000+4*0x9010e, .val = 0x408},
  666 + { .reg = 0x3c000000+4*0x9010f, .val = 0x169},
  667 + { .reg = 0x3c000000+4*0x90110, .val = 0x0},
  668 + { .reg = 0x3c000000+4*0x90111, .val = 0x8b10},
  669 + { .reg = 0x3c000000+4*0x90112, .val = 0x168},
  670 + { .reg = 0x3c000000+4*0x90113, .val = 0x0},
  671 + { .reg = 0x3c000000+4*0x90114, .val = 0xab10},
  672 + { .reg = 0x3c000000+4*0x90115, .val = 0x168},
  673 + { .reg = 0x3c000000+4*0x90116, .val = 0x0},
  674 + { .reg = 0x3c000000+4*0x90117, .val = 0x1d8},
  675 + { .reg = 0x3c000000+4*0x90118, .val = 0x169},
  676 + { .reg = 0x3c000000+4*0x90119, .val = 0x80},
  677 + { .reg = 0x3c000000+4*0x9011a, .val = 0x790},
  678 + { .reg = 0x3c000000+4*0x9011b, .val = 0x16a},
  679 + { .reg = 0x3c000000+4*0x9011c, .val = 0x18},
  680 + { .reg = 0x3c000000+4*0x9011d, .val = 0x7aa},
  681 + { .reg = 0x3c000000+4*0x9011e, .val = 0x6a},
  682 + { .reg = 0x3c000000+4*0x9011f, .val = 0xa},
  683 + { .reg = 0x3c000000+4*0x90120, .val = 0x0},
  684 + { .reg = 0x3c000000+4*0x90121, .val = 0x1e9},
  685 + { .reg = 0x3c000000+4*0x90122, .val = 0x8},
  686 + { .reg = 0x3c000000+4*0x90123, .val = 0x8080},
  687 + { .reg = 0x3c000000+4*0x90124, .val = 0x108},
  688 + { .reg = 0x3c000000+4*0x90125, .val = 0xf},
  689 + { .reg = 0x3c000000+4*0x90126, .val = 0x408},
  690 + { .reg = 0x3c000000+4*0x90127, .val = 0x169},
  691 + { .reg = 0x3c000000+4*0x90128, .val = 0xc},
  692 + { .reg = 0x3c000000+4*0x90129, .val = 0x0},
  693 + { .reg = 0x3c000000+4*0x9012a, .val = 0x68},
  694 + { .reg = 0x3c000000+4*0x9012b, .val = 0x9},
  695 + { .reg = 0x3c000000+4*0x9012c, .val = 0x0},
  696 + { .reg = 0x3c000000+4*0x9012d, .val = 0x1a9},
  697 + { .reg = 0x3c000000+4*0x9012e, .val = 0x0},
  698 + { .reg = 0x3c000000+4*0x9012f, .val = 0x408},
  699 + { .reg = 0x3c000000+4*0x90130, .val = 0x169},
  700 + { .reg = 0x3c000000+4*0x90131, .val = 0x0},
  701 + { .reg = 0x3c000000+4*0x90132, .val = 0x8080},
  702 + { .reg = 0x3c000000+4*0x90133, .val = 0x108},
  703 + { .reg = 0x3c000000+4*0x90134, .val = 0x8},
  704 + { .reg = 0x3c000000+4*0x90135, .val = 0x7aa},
  705 + { .reg = 0x3c000000+4*0x90136, .val = 0x6a},
  706 + { .reg = 0x3c000000+4*0x90137, .val = 0x0},
  707 + { .reg = 0x3c000000+4*0x90138, .val = 0x8568},
  708 + { .reg = 0x3c000000+4*0x90139, .val = 0x108},
  709 + { .reg = 0x3c000000+4*0x9013a, .val = 0xb7},
  710 + { .reg = 0x3c000000+4*0x9013b, .val = 0x790},
  711 + { .reg = 0x3c000000+4*0x9013c, .val = 0x16a},
  712 + { .reg = 0x3c000000+4*0x9013d, .val = 0x1f},
  713 + { .reg = 0x3c000000+4*0x9013e, .val = 0x0},
  714 + { .reg = 0x3c000000+4*0x9013f, .val = 0x68},
  715 + { .reg = 0x3c000000+4*0x90140, .val = 0x8},
  716 + { .reg = 0x3c000000+4*0x90141, .val = 0x8558},
  717 + { .reg = 0x3c000000+4*0x90142, .val = 0x168},
  718 + { .reg = 0x3c000000+4*0x90143, .val = 0xf},
  719 + { .reg = 0x3c000000+4*0x90144, .val = 0x408},
  720 + { .reg = 0x3c000000+4*0x90145, .val = 0x169},
  721 + { .reg = 0x3c000000+4*0x90146, .val = 0xc},
  722 + { .reg = 0x3c000000+4*0x90147, .val = 0x0},
  723 + { .reg = 0x3c000000+4*0x90148, .val = 0x68},
  724 + { .reg = 0x3c000000+4*0x90149, .val = 0x0},
  725 + { .reg = 0x3c000000+4*0x9014a, .val = 0x408},
  726 + { .reg = 0x3c000000+4*0x9014b, .val = 0x169},
  727 + { .reg = 0x3c000000+4*0x9014c, .val = 0x0},
  728 + { .reg = 0x3c000000+4*0x9014d, .val = 0x8558},
  729 + { .reg = 0x3c000000+4*0x9014e, .val = 0x168},
  730 + { .reg = 0x3c000000+4*0x9014f, .val = 0x8},
  731 + { .reg = 0x3c000000+4*0x90150, .val = 0x3c8},
  732 + { .reg = 0x3c000000+4*0x90151, .val = 0x1a9},
  733 + { .reg = 0x3c000000+4*0x90152, .val = 0x3},
  734 + { .reg = 0x3c000000+4*0x90153, .val = 0x370},
  735 + { .reg = 0x3c000000+4*0x90154, .val = 0x129},
  736 + { .reg = 0x3c000000+4*0x90155, .val = 0x20},
  737 + { .reg = 0x3c000000+4*0x90156, .val = 0x2aa},
  738 + { .reg = 0x3c000000+4*0x90157, .val = 0x9},
  739 + { .reg = 0x3c000000+4*0x90158, .val = 0x0},
  740 + { .reg = 0x3c000000+4*0x90159, .val = 0x400},
  741 + { .reg = 0x3c000000+4*0x9015a, .val = 0x10e},
  742 + { .reg = 0x3c000000+4*0x9015b, .val = 0x8},
  743 + { .reg = 0x3c000000+4*0x9015c, .val = 0xe8},
  744 + { .reg = 0x3c000000+4*0x9015d, .val = 0x109},
  745 + { .reg = 0x3c000000+4*0x9015e, .val = 0x0},
  746 + { .reg = 0x3c000000+4*0x9015f, .val = 0x8140},
  747 + { .reg = 0x3c000000+4*0x90160, .val = 0x10c},
  748 + { .reg = 0x3c000000+4*0x90161, .val = 0x10},
  749 + { .reg = 0x3c000000+4*0x90162, .val = 0x8138},
  750 + { .reg = 0x3c000000+4*0x90163, .val = 0x10c},
  751 + { .reg = 0x3c000000+4*0x90164, .val = 0x8},
  752 + { .reg = 0x3c000000+4*0x90165, .val = 0x7c8},
  753 + { .reg = 0x3c000000+4*0x90166, .val = 0x101},
  754 + { .reg = 0x3c000000+4*0x90167, .val = 0x8},
  755 + { .reg = 0x3c000000+4*0x90168, .val = 0x0},
  756 + { .reg = 0x3c000000+4*0x90169, .val = 0x8},
  757 + { .reg = 0x3c000000+4*0x9016a, .val = 0x8},
  758 + { .reg = 0x3c000000+4*0x9016b, .val = 0x448},
  759 + { .reg = 0x3c000000+4*0x9016c, .val = 0x109},
  760 + { .reg = 0x3c000000+4*0x9016d, .val = 0xf},
  761 + { .reg = 0x3c000000+4*0x9016e, .val = 0x7c0},
  762 + { .reg = 0x3c000000+4*0x9016f, .val = 0x109},
  763 + { .reg = 0x3c000000+4*0x90170, .val = 0x0},
  764 + { .reg = 0x3c000000+4*0x90171, .val = 0xe8},
  765 + { .reg = 0x3c000000+4*0x90172, .val = 0x109},
  766 + { .reg = 0x3c000000+4*0x90173, .val = 0x47},
  767 + { .reg = 0x3c000000+4*0x90174, .val = 0x630},
  768 + { .reg = 0x3c000000+4*0x90175, .val = 0x109},
  769 + { .reg = 0x3c000000+4*0x90176, .val = 0x8},
  770 + { .reg = 0x3c000000+4*0x90177, .val = 0x618},
  771 + { .reg = 0x3c000000+4*0x90178, .val = 0x109},
  772 + { .reg = 0x3c000000+4*0x90179, .val = 0x8},
  773 + { .reg = 0x3c000000+4*0x9017a, .val = 0xe0},
  774 + { .reg = 0x3c000000+4*0x9017b, .val = 0x109},
  775 + { .reg = 0x3c000000+4*0x9017c, .val = 0x0},
  776 + { .reg = 0x3c000000+4*0x9017d, .val = 0x7c8},
  777 + { .reg = 0x3c000000+4*0x9017e, .val = 0x109},
  778 + { .reg = 0x3c000000+4*0x9017f, .val = 0x8},
  779 + { .reg = 0x3c000000+4*0x90180, .val = 0x8140},
  780 + { .reg = 0x3c000000+4*0x90181, .val = 0x10c},
  781 + { .reg = 0x3c000000+4*0x90182, .val = 0x0},
  782 + { .reg = 0x3c000000+4*0x90183, .val = 0x1},
  783 + { .reg = 0x3c000000+4*0x90184, .val = 0x8},
  784 + { .reg = 0x3c000000+4*0x90185, .val = 0x8},
  785 + { .reg = 0x3c000000+4*0x90186, .val = 0x4},
  786 + { .reg = 0x3c000000+4*0x90187, .val = 0x8},
  787 + { .reg = 0x3c000000+4*0x90188, .val = 0x8},
  788 + { .reg = 0x3c000000+4*0x90189, .val = 0x7c8},
  789 + { .reg = 0x3c000000+4*0x9018a, .val = 0x101},
  790 + { .reg = 0x3c000000+4*0x90006, .val = 0x0},
  791 + { .reg = 0x3c000000+4*0x90007, .val = 0x0},
  792 + { .reg = 0x3c000000+4*0x90008, .val = 0x8},
  793 + { .reg = 0x3c000000+4*0x90009, .val = 0x0},
  794 + { .reg = 0x3c000000+4*0x9000a, .val = 0x0},
  795 + { .reg = 0x3c000000+4*0x9000b, .val = 0x0},
  796 + { .reg = 0x3c000000+4*0xd00e7, .val = 0x400},
  797 + { .reg = 0x3c000000+4*0x90017, .val = 0x0},
  798 + { .reg = 0x3c000000+4*0x9001f, .val = 0x2a},
  799 + { .reg = 0x3c000000+4*0x90026, .val = 0x6a},
  800 + { .reg = 0x3c000000+4*0x400d0, .val = 0x0},
  801 + { .reg = 0x3c000000+4*0x400d1, .val = 0x101},
  802 + { .reg = 0x3c000000+4*0x400d2, .val = 0x105},
  803 + { .reg = 0x3c000000+4*0x400d3, .val = 0x107},
  804 + { .reg = 0x3c000000+4*0x400d4, .val = 0x10f},
  805 + { .reg = 0x3c000000+4*0x400d5, .val = 0x202},
  806 + { .reg = 0x3c000000+4*0x400d6, .val = 0x20a},
  807 + { .reg = 0x3c000000+4*0x400d7, .val = 0x20b},
  808 + { .reg = 0x3c000000+4*0x2003a, .val = 0x2},
  809 + { .reg = 0x3c000000+4*0x2000b, .val = 0x5d},
  810 + { .reg = 0x3c000000+4*0x2000c, .val = 0xbb},
  811 + { .reg = 0x3c000000+4*0x2000d, .val = 0x753},
  812 + { .reg = 0x3c000000+4*0x2000e, .val = 0x2c},
  813 + { .reg = 0x3c000000+4*0x9000c, .val = 0x0},
  814 + { .reg = 0x3c000000+4*0x9000d, .val = 0x173},
  815 + { .reg = 0x3c000000+4*0x9000e, .val = 0x60},
  816 + { .reg = 0x3c000000+4*0x9000f, .val = 0x6110},
  817 + { .reg = 0x3c000000+4*0x90010, .val = 0x2152},
  818 + { .reg = 0x3c000000+4*0x90011, .val = 0xdfbd},
  819 + { .reg = 0x3c000000+4*0x90012, .val = 0x60},
  820 + { .reg = 0x3c000000+4*0x90013, .val = 0x6152},
  821 + { .reg = 0x3c000000+4*0x20010, .val = 0x5a},
  822 + { .reg = 0x3c000000+4*0x20011, .val = 0x3},
  823 + { .reg = 0x3c000000+4*0x40080, .val = 0xe0},
  824 + { .reg = 0x3c000000+4*0x40081, .val = 0x12},
  825 + { .reg = 0x3c000000+4*0x40082, .val = 0xe0},
  826 + { .reg = 0x3c000000+4*0x40083, .val = 0x12},
  827 + { .reg = 0x3c000000+4*0x40084, .val = 0xe0},
  828 + { .reg = 0x3c000000+4*0x40085, .val = 0x12},
  829 + { .reg = 0x3c000000+4*0x400fd, .val = 0xf},
  830 + { .reg = 0x3c000000+4*0x10011, .val = 0x1},
  831 + { .reg = 0x3c000000+4*0x10012, .val = 0x1},
  832 + { .reg = 0x3c000000+4*0x10013, .val = 0x180},
  833 + { .reg = 0x3c000000+4*0x10018, .val = 0x1},
  834 + { .reg = 0x3c000000+4*0x10002, .val = 0x6209},
  835 + { .reg = 0x3c000000+4*0x100b2, .val = 0x1},
  836 + { .reg = 0x3c000000+4*0x101b4, .val = 0x1},
  837 + { .reg = 0x3c000000+4*0x102b4, .val = 0x1},
  838 + { .reg = 0x3c000000+4*0x103b4, .val = 0x1},
  839 + { .reg = 0x3c000000+4*0x104b4, .val = 0x1},
  840 + { .reg = 0x3c000000+4*0x105b4, .val = 0x1},
  841 + { .reg = 0x3c000000+4*0x106b4, .val = 0x1},
  842 + { .reg = 0x3c000000+4*0x107b4, .val = 0x1},
  843 + { .reg = 0x3c000000+4*0x108b4, .val = 0x1},
  844 + { .reg = 0x3c000000+4*0x11011, .val = 0x1},
  845 + { .reg = 0x3c000000+4*0x11012, .val = 0x1},
  846 + { .reg = 0x3c000000+4*0x11013, .val = 0x180},
  847 + { .reg = 0x3c000000+4*0x11018, .val = 0x1},
  848 + { .reg = 0x3c000000+4*0x11002, .val = 0x6209},
  849 + { .reg = 0x3c000000+4*0x110b2, .val = 0x1},
  850 + { .reg = 0x3c000000+4*0x111b4, .val = 0x1},
  851 + { .reg = 0x3c000000+4*0x112b4, .val = 0x1},
  852 + { .reg = 0x3c000000+4*0x113b4, .val = 0x1},
  853 + { .reg = 0x3c000000+4*0x114b4, .val = 0x1},
  854 + { .reg = 0x3c000000+4*0x115b4, .val = 0x1},
  855 + { .reg = 0x3c000000+4*0x116b4, .val = 0x1},
  856 + { .reg = 0x3c000000+4*0x117b4, .val = 0x1},
  857 + { .reg = 0x3c000000+4*0x118b4, .val = 0x1},
  858 + { .reg = 0x3c000000+4*0x12011, .val = 0x1},
  859 + { .reg = 0x3c000000+4*0x12012, .val = 0x1},
  860 + { .reg = 0x3c000000+4*0x12013, .val = 0x180},
  861 + { .reg = 0x3c000000+4*0x12018, .val = 0x1},
  862 + { .reg = 0x3c000000+4*0x12002, .val = 0x6209},
  863 + { .reg = 0x3c000000+4*0x120b2, .val = 0x1},
  864 + { .reg = 0x3c000000+4*0x121b4, .val = 0x1},
  865 + { .reg = 0x3c000000+4*0x122b4, .val = 0x1},
  866 + { .reg = 0x3c000000+4*0x123b4, .val = 0x1},
  867 + { .reg = 0x3c000000+4*0x124b4, .val = 0x1},
  868 + { .reg = 0x3c000000+4*0x125b4, .val = 0x1},
  869 + { .reg = 0x3c000000+4*0x126b4, .val = 0x1},
  870 + { .reg = 0x3c000000+4*0x127b4, .val = 0x1},
  871 + { .reg = 0x3c000000+4*0x128b4, .val = 0x1},
  872 + { .reg = 0x3c000000+4*0x13011, .val = 0x1},
  873 + { .reg = 0x3c000000+4*0x13012, .val = 0x1},
  874 + { .reg = 0x3c000000+4*0x13013, .val = 0x180},
  875 + { .reg = 0x3c000000+4*0x13018, .val = 0x1},
  876 + { .reg = 0x3c000000+4*0x13002, .val = 0x6209},
  877 + { .reg = 0x3c000000+4*0x130b2, .val = 0x1},
  878 + { .reg = 0x3c000000+4*0x131b4, .val = 0x1},
  879 + { .reg = 0x3c000000+4*0x132b4, .val = 0x1},
  880 + { .reg = 0x3c000000+4*0x133b4, .val = 0x1},
  881 + { .reg = 0x3c000000+4*0x134b4, .val = 0x1},
  882 + { .reg = 0x3c000000+4*0x135b4, .val = 0x1},
  883 + { .reg = 0x3c000000+4*0x136b4, .val = 0x1},
  884 + { .reg = 0x3c000000+4*0x137b4, .val = 0x1},
  885 + { .reg = 0x3c000000+4*0x138b4, .val = 0x1},
  886 + { .reg = 0x3c000000+4*0x2003a, .val = 0x2},
  887 + { .reg = 0x3c000000+4*0xc0080, .val = 0x2},
  888 + { .reg = 0x3c000000+4*0xd0000, .val = 0x1},
  889 + { .reg = DDR_PHY_FLAG_ADDR, .val = 0x08},
  890 +};
  891 +
  892 +
  893 +
  894 +void lpddr4_750M_cfg_phy(void)
  895 +{
  896 + uint32_t index, reg, val, num;
  897 +
  898 + num = sizeof(phy_init_cfg)/sizeof(struct ddr_phy_param);
  899 +
  900 + dwc_ddrphy_phyinit_userCustom_overrideUserInput();
  901 + dwc_ddrphy_phyinit_userCustom_A_bringupPower();
  902 + dwc_ddrphy_phyinit_userCustom_B_startClockResetPhy();
  903 +
  904 + for (index = 0; index < num; index++) {
  905 + val = phy_init_cfg[index].val;
  906 + reg = phy_init_cfg[index].reg;
  907 + writel(val,(void __iomem *)(u64)reg);
  908 + if(reg == DDR_PHY_FLAG_ADDR) {
  909 + switch(val) {
  910 + case 0x00:
  911 + dwc_ddrphy_phyinit_userCustom_E_setDfiClk(0);
  912 + break;
  913 + case 0x01:
  914 + ddr_load_train_code(FW_1D_IMAGE);
  915 + break;
  916 + case 0x02:
  917 + dwc_ddrphy_phyinit_userCustom_G_waitFwDone();
  918 + break;
  919 + case 0x03:
  920 + dwc_ddrphy_phyinit_userCustom_H_readMsgBlock(0);
  921 + break;
  922 + case 0x04:
  923 + dwc_ddrphy_phyinit_userCustom_E_setDfiClk(0);
  924 + break;
  925 + case 0x05:
  926 + ddr_load_train_code(FW_2D_IMAGE);
  927 + break;
  928 + case 0x06:
  929 + dwc_ddrphy_phyinit_userCustom_G_waitFwDone();
  930 + break;
  931 + case 0x07:
  932 + dwc_ddrphy_phyinit_userCustom_H_readMsgBlock(1);
  933 + break;
  934 + case 0x08:
  935 + dwc_ddrphy_phyinit_userCustom_customPostTrain();
  936 + dwc_ddrphy_phyinit_userCustom_J_enterMissionMode();
  937 + break;
  938 + default:
  939 + break;
  940 + }
  941 + }
  942 + }
  943 +}
board/freescale/imx8mm_evk/ddr/lpddr4_pmu_training_3000mts_fw09.c
Diff comments   View file @ b02221d
  1 +/*
  2 +* Copyright 2018 NXP
  3 +*
  4 +* SPDX-License-Identifier: GPL-2.0+
  5 +*/
  6 +
  7 +#include <common.h>
  8 +#include <errno.h>
  9 +#include <asm/io.h>
  10 +#include <asm/arch/ddr.h>
  11 +#include <asm/arch/clock.h>
  12 +#include "lpddr4_define.h"
  13 +#include "ddr.h"
  14 +
  15 +void ddr_init(void)
  16 +{
  17 + volatile unsigned int tmp;
  18 +
  19 + /*
  20 + * Desc: assert [0]ddr1_preset_n, [1]ddr1_core_reset_n,
  21 + * [2]ddr1_phy_reset, [3]ddr1_phy_pwrokin_n,
  22 + * [4]src_system_rst_b!
  23 + */
  24 + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00003F);
  25 +
  26 + /* Desc: deassert [4]src_system_rst_b! */
  27 + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00000F);
  28 +
  29 + /*
  30 + * Desc: change the clock source of dram_apb_clk_root
  31 + * to source 4 --800MHz/4
  32 + */
  33 + #if 0
  34 + reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(1),(0x7<<24)|(0x7<<16));
  35 + reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_SET(1),(0x4<<24)|(0x3<<16));
  36 + #else
  37 +
  38 + clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | \
  39 + CLK_ROOT_SOURCE_SEL(0) | \
  40 + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1));
  41 + clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON | \
  42 + CLK_ROOT_SOURCE_SEL(0) | \
  43 + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1));
  44 + clock_set_target_val(NOC_CLK_ROOT, CLK_ROOT_ON | \
  45 + CLK_ROOT_SOURCE_SEL(0) | \
  46 + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1));
  47 + clock_set_target_val(NOC_APB_CLK_ROOT, CLK_ROOT_ON | \
  48 + CLK_ROOT_SOURCE_SEL(0) | \
  49 + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1));
  50 + #endif
  51 +
  52 + /* Desc: disable iso PGC_CPU_MAPPING,PU_PGC_SW_PUP_REQ */
  53 + reg32_write(0x303A00EC,0x0000ffff);
  54 + reg32setbit(0x303A00F8,5);
  55 +
  56 + /*
  57 + * Desc: configure dram pll to 750M
  58 + */
  59 + dram_pll_init(DRAM_PLL_OUT_750M);
  60 +
  61 +
  62 + /*
  63 + * Desc: release [0]ddr1_preset_n, [1]ddr1_core_reset_n,
  64 + * [2]ddr1_phy_reset, [3]ddr1_phy_pwrokin_n
  65 + */
  66 + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006);
  67 +
  68 + /* Desc: Configure uMCTL2's registers */
  69 + lpddr4_3000mts_cfg_umctl2();
  70 +
  71 + /* Desc: diable ctlupd */
  72 + reg32_write(DDRC_DFIUPD0(0), 0xE0300018);
  73 +
  74 + /*
  75 + * Desc: release [1]ddr1_core_reset_n, [2]ddr1_phy_reset,
  76 + * [3]ddr1_phy_pwrokin_n
  77 + */
  78 + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000004);
  79 +
  80 + /*
  81 + * Desc: release [1]ddr1_core_reset_n, [2]ddr1_phy_reset,
  82 + * [3]ddr1_phy_pwrokin_n
  83 + */
  84 + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000000);
  85 +
  86 + /*
  87 + * Desc: ('b00000000_00000000_00000000_00000000) ('d0)
  88 + */
  89 + reg32_write(DDRC_DBG1(0), 0x00000000);
  90 +
  91 + /*
  92 + * Desc: [8]--1: lpddr4_sr allowed; [5]--1: software entry to SR
  93 + */
  94 + reg32_write(DDRC_PWRCTL(0), 0x000000a8);
  95 +
  96 + tmp=0;
  97 + while(tmp != 0x223) {
  98 + tmp = 0x33f & (reg32_read(DDRC_STAT(0)));
  99 + ddr_dbg("C: waiting for STAT selfref_type= Self Refresh\n");
  100 + }
  101 +
  102 + /*
  103 + * Desc: ('b00000000_00000000_00000000_00000000) ('d0)
  104 + */
  105 + reg32_write(DDRC_SWCTL(0), 0x00000000);
  106 +
  107 + /*
  108 + * Desc: LPDDR4 mode
  109 + */
  110 + reg32_write(DDRC_DDR_SS_GPR0, 0x01);
  111 +
  112 + /*
  113 + * Desc: [12:8]dfi_freq, [5]dfi_init_start, [4]ctl_idle_en
  114 + */
  115 + reg32_write(DDRC_DFIMISC(0), 0x00000010);
  116 +
  117 + /*
  118 + * Desc: Configure LPDDR4 PHY's registers
  119 + */
  120 + lpddr4_750M_cfg_phy();
  121 +
  122 + reg32_write(DDRC_RFSHCTL3(0), 0x00000000);
  123 + reg32_write(DDRC_SWCTL(0), 0x0000);
  124 +
  125 + /*
  126 + * Desc: Set DFIMISC.dfi_init_start to 1
  127 + * [5]--1: dfi_init_start, [4] ctl_idle_en
  128 + */
  129 + reg32_write(DDRC_DFIMISC(0), 0x00000030);
  130 + reg32_write(DDRC_SWCTL(0), 0x0001);
  131 +
  132 + /*
  133 + * Desc: wait DFISTAT.dfi_init_complete to 1
  134 + */
  135 + while(!(0x1 & (reg32_read(DDRC_DFISTAT(0)))));
  136 +
  137 + reg32_write(DDRC_SWCTL(0), 0x0000);
  138 +
  139 + /*
  140 + * Desc: clear DFIMISC.dfi_init_complete_en
  141 + * ('b00000000_00000000_00000000_00010000) ('d16)
  142 + */
  143 + reg32_write(DDRC_DFIMISC(0), 0x00000010);
  144 +
  145 + /*
  146 + * Desc: set DFIMISC.dfi_init_complete_en again
  147 + * ('b00000000_00000000_00000000_00010001) ('d17)
  148 + */
  149 + reg32_write(DDRC_DFIMISC(0), 0x00000011);
  150 +
  151 + /*
  152 + * Desc: ('b00000000_00000000_00000000_10001000) ('d136)
  153 + */
  154 + reg32_write(DDRC_PWRCTL(0), 0x00000088);
  155 +
  156 + /*
  157 + * Desc: set SWCTL.sw_done to enable quasi-dynamic
  158 + * register programming outside reset.
  159 + * ('b00000000_00000000_00000000_00000001) ('d1)
  160 + */
  161 + reg32_write(DDRC_SWCTL(0), 0x00000001);
  162 +
  163 + /*
  164 + * Desc: wait SWSTAT.sw_done_ack to 1
  165 + */
  166 + while(!(0x1 & (reg32_read(DDRC_SWSTAT(0)))));
  167 +
  168 + /*
  169 + * Desc: wait STAT.operating_mode([2:0] for lpddr4) to normal state
  170 + */
  171 + while(0x1 != (0x7 & (reg32_read(DDRC_STAT(0)))));
  172 +
  173 + /*
  174 + * Desc: ('b00000000_00000000_00000000_10001000) ('d136)
  175 + */
  176 + reg32_write(DDRC_PWRCTL(0), 0x00000088);
  177 +
  178 +
  179 + /*
  180 + * Desc: enable port 0
  181 + * ('b00000000_00000000_00000000_00000001) ('d1)
  182 + */
  183 + reg32_write(DDRC_PCTRL_0(0), 0x00000001);
  184 +}
board/freescale/imx8mm_evk/imx8mm_evk.c
Diff comments   View file @ b02221d
  1 +/*
  2 + * Copyright 2018 NXP
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <common.h>
  8 +#include <malloc.h>
  9 +#include <errno.h>
  10 +#include <asm/io.h>
  11 +#include <miiphy.h>
  12 +#include <netdev.h>
  13 +#include <asm/mach-imx/iomux-v3.h>
  14 +#include <asm-generic/gpio.h>
  15 +#include <fsl_esdhc.h>
  16 +#include <mmc.h>
  17 +#include <asm/arch/imx8mm_pins.h>
  18 +#include <asm/arch/sys_proto.h>
  19 +#include <asm/mach-imx/gpio.h>
  20 +#include <asm/mach-imx/mxc_i2c.h>
  21 +#include <asm/arch/clock.h>
  22 +#include <spl.h>
  23 +#include <asm/mach-imx/dma.h>
  24 +#include <power/pmic.h>
  25 +#include <power/bd71837.h>
  26 +
  27 +DECLARE_GLOBAL_DATA_PTR;
  28 +
  29 +#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
  30 +
  31 +static iomux_v3_cfg_t const uart_pads[] = {
  32 + IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  33 + IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  34 +};
  35 +
  36 +#ifdef CONFIG_FSL_FSPI
  37 +#define QSPI_PAD_CTRL (PAD_CTL_DSE2 | PAD_CTL_HYS)
  38 +static iomux_v3_cfg_t const qspi_pads[] = {
  39 + IMX8MM_PAD_NAND_ALE_QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL | PAD_CTL_PE | PAD_CTL_PUE),
  40 + IMX8MM_PAD_NAND_CE0_B_QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL),
  41 +
  42 + IMX8MM_PAD_NAND_DATA00_QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
  43 + IMX8MM_PAD_NAND_DATA01_QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
  44 + IMX8MM_PAD_NAND_DATA02_QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
  45 + IMX8MM_PAD_NAND_DATA03_QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
  46 +};
  47 +
  48 +int board_qspi_init(void)
  49 +{
  50 + imx_iomux_v3_setup_multiple_pads(qspi_pads, ARRAY_SIZE(qspi_pads));
  51 +
  52 + set_clk_qspi();
  53 +
  54 + return 0;
  55 +}
  56 +#endif
  57 +
  58 +#ifdef CONFIG_MXC_SPI
  59 +#define SPI_PAD_CTRL (PAD_CTL_DSE2 | PAD_CTL_HYS)
  60 +static iomux_v3_cfg_t const ecspi1_pads[] = {
  61 + IMX8MM_PAD_ECSPI1_SCLK_ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
  62 + IMX8MM_PAD_ECSPI1_MOSI_ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
  63 + IMX8MM_PAD_ECSPI1_MISO_ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
  64 + IMX8MM_PAD_ECSPI1_SS0_GPIO5_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL),
  65 +};
  66 +
  67 +static iomux_v3_cfg_t const ecspi2_pads[] = {
  68 + IMX8MM_PAD_ECSPI2_SCLK_ECSPI2_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
  69 + IMX8MM_PAD_ECSPI2_MOSI_ECSPI2_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
  70 + IMX8MM_PAD_ECSPI2_MISO_ECSPI2_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
  71 + IMX8MM_PAD_ECSPI2_SS0_GPIO5_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
  72 +};
  73 +
  74 +static void setup_spi(void)
  75 +{
  76 + imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
  77 + imx_iomux_v3_setup_multiple_pads(ecspi2_pads, ARRAY_SIZE(ecspi2_pads));
  78 + gpio_request(IMX_GPIO_NR(5, 9), "ECSPI1 CS");
  79 + gpio_request(IMX_GPIO_NR(5, 13), "ECSPI2 CS");
  80 +}
  81 +
  82 +int board_spi_cs_gpio(unsigned bus, unsigned cs)
  83 +{
  84 + if (bus == 0)
  85 + return IMX_GPIO_NR(5, 9);
  86 + else
  87 + return IMX_GPIO_NR(5, 13);
  88 +}
  89 +#endif
  90 +
  91 +#ifdef CONFIG_NAND_MXS
  92 +#define NAND_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL2 | PAD_CTL_HYS)
  93 +#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL2 | PAD_CTL_PUE)
  94 +static iomux_v3_cfg_t const gpmi_pads[] = {
  95 + IMX8MM_PAD_NAND_ALE_RAWNAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
  96 + IMX8MM_PAD_NAND_CE0_B_RAWNAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  97 + IMX8MM_PAD_NAND_CLE_RAWNAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL),
  98 + IMX8MM_PAD_NAND_DATA00_RAWNAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  99 + IMX8MM_PAD_NAND_DATA01_RAWNAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  100 + IMX8MM_PAD_NAND_DATA02_RAWNAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  101 + IMX8MM_PAD_NAND_DATA03_RAWNAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  102 + IMX8MM_PAD_NAND_DATA04_RAWNAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  103 + IMX8MM_PAD_NAND_DATA05_RAWNAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  104 + IMX8MM_PAD_NAND_DATA06_RAWNAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  105 + IMX8MM_PAD_NAND_DATA07_RAWNAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  106 + IMX8MM_PAD_NAND_RE_B_RAWNAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  107 + IMX8MM_PAD_NAND_READY_B_RAWNAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL),
  108 + IMX8MM_PAD_NAND_WE_B_RAWNAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  109 + IMX8MM_PAD_NAND_WP_B_RAWNAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  110 +};
  111 +
  112 +static void setup_gpmi_nand(void)
  113 +{
  114 + imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
  115 + mxs_dma_init();
  116 +}
  117 +#endif
  118 +
  119 +int board_early_init_f(void)
  120 +{
  121 + imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  122 +
  123 + return 0;
  124 +}
  125 +
  126 +#ifdef CONFIG_BOARD_POSTCLK_INIT
  127 +int board_postclk_init(void)
  128 +{
  129 + /* TODO */
  130 + return 0;
  131 +}
  132 +#endif
  133 +
  134 +int dram_init(void)
  135 +{
  136 + gd->ram_size = PHYS_SDRAM_SIZE;
  137 +
  138 + return 0;
  139 +}
  140 +
  141 +#ifdef CONFIG_OF_BOARD_SETUP
  142 +int ft_board_setup(void *blob, bd_t *bd)
  143 +{
  144 + return 0;
  145 +}
  146 +#endif
  147 +
  148 +#ifdef CONFIG_FEC_MXC
  149 +#define FEC_RST_PAD IMX_GPIO_NR(4, 22)
  150 +static iomux_v3_cfg_t const fec1_rst_pads[] = {
  151 + IMX8MM_PAD_SAI2_RXC_GPIO4_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
  152 +};
  153 +
  154 +static void setup_iomux_fec(void)
  155 +{
  156 + imx_iomux_v3_setup_multiple_pads(fec1_rst_pads,
  157 + ARRAY_SIZE(fec1_rst_pads));
  158 +
  159 + gpio_request(FEC_RST_PAD, "fec1_rst");
  160 + gpio_direction_output(FEC_RST_PAD, 0);
  161 + udelay(500);
  162 + gpio_direction_output(FEC_RST_PAD, 1);
  163 +}
  164 +
  165 +static int setup_fec(void)
  166 +{
  167 + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
  168 + = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
  169 +
  170 + setup_iomux_fec();
  171 +
  172 + /* Use 125M anatop REF_CLK1 for ENET1, not from external */
  173 + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
  174 + IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT, 0);
  175 + return set_clk_enet(ENET_125MHZ);
  176 +}
  177 +
  178 +int board_phy_config(struct phy_device *phydev)
  179 +{
  180 + /* enable rgmii rxc skew and phy mode select to RGMII copper */
  181 + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
  182 + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
  183 +
  184 + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
  185 + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
  186 + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
  187 + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
  188 +
  189 + if (phydev->drv->config)
  190 + phydev->drv->config(phydev);
  191 + return 0;
  192 +}
  193 +#endif
  194 +
  195 +int board_init(void)
  196 +{
  197 +#ifdef CONFIG_MXC_SPI
  198 + setup_spi();
  199 +#endif
  200 +
  201 +#ifdef CONFIG_FEC_MXC
  202 + setup_fec();
  203 +#endif
  204 +
  205 +#ifdef CONFIG_FSL_FSPI
  206 + board_qspi_init();
  207 +#endif
  208 +
  209 +#ifdef CONFIG_NAND_MXS
  210 + setup_gpmi_nand(); /* SPL will call the board_early_init_f */
  211 +#endif
  212 + return 0;
  213 +}
  214 +
  215 +int board_mmc_get_env_dev(int devno)
  216 +{
  217 + return devno - 1;
  218 +}
  219 +
  220 +int mmc_map_to_kernel_blk(int devno)
  221 +{
  222 + return devno + 1;
  223 +}
  224 +
  225 +int board_late_init(void)
  226 +{
  227 +#ifdef CONFIG_ENV_IS_IN_MMC
  228 + board_late_mmc_env_init();
  229 +#endif
  230 +
  231 + return 0;
  232 +}
  233 +
  234 +#ifdef CONFIG_POWER
  235 +#define I2C_PMIC 0
  236 +int power_init_board(void)
  237 +{
  238 + struct pmic *p;
  239 + int ret;
  240 + unsigned int reg;
  241 +
  242 + return 0;
  243 +
  244 + ret = power_bd71837_init(I2C_PMIC);
  245 + if (ret)
  246 + printf("power init failed");
  247 +
  248 + p = pmic_get("BD71837");
  249 + pmic_probe(p);
  250 +
  251 +#if 0
  252 + /* unlock the PMIC regs */
  253 + pmic_reg_write(p, BD71837_REGLOCK, 0x1);
  254 +
  255 + /* Set BUCK5 output for DRAM to 1.0V */
  256 + pmic_reg_write(p, BD71837_BUCK5_VOLT, 0x3);
  257 +
  258 + /* lock the PMIC regs */
  259 + pmic_reg_write(p, BD71837_REGLOCK, 0x11);
  260 +#endif
  261 + return 0;
  262 +}
  263 +#endif
board/freescale/imx8mm_evk/spl.c
Diff comments   View file @ b02221d
  1 +/*
  2 + * Copyright 2018 NXP
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <common.h>
  8 +#include <spl.h>
  9 +#include <asm/io.h>
  10 +#include <errno.h>
  11 +#include <asm/io.h>
  12 +#include <asm/mach-imx/iomux-v3.h>
  13 +#include <asm/arch/imx8mm_pins.h>
  14 +#include <asm/arch/sys_proto.h>
  15 +#include <power/pmic.h>
  16 +#include <power/pfuze100_pmic.h>
  17 +#include "../common/pfuze.h"
  18 +#include <asm/arch/clock.h>
  19 +#include <asm/mach-imx/gpio.h>
  20 +#include <asm/mach-imx/mxc_i2c.h>
  21 +#include <fsl_esdhc.h>
  22 +#include <mmc.h>
  23 +#include "ddr/ddr.h"
  24 +
  25 +DECLARE_GLOBAL_DATA_PTR;
  26 +
  27 +void spl_dram_init(void)
  28 +{
  29 + /* ddr train */
  30 + ddr_init();
  31 +}
  32 +
  33 +#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12)
  34 +#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
  35 +
  36 +int board_mmc_getcd(struct mmc *mmc)
  37 +{
  38 + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  39 + int ret = 0;
  40 +
  41 + switch (cfg->esdhc_base) {
  42 + case USDHC3_BASE_ADDR:
  43 + ret = 1;
  44 + break;
  45 + case USDHC2_BASE_ADDR:
  46 + ret = !gpio_get_value(USDHC2_CD_GPIO);
  47 + return ret;
  48 + }
  49 +
  50 + return 1;
  51 +}
  52 +
  53 +#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE |PAD_CTL_PE | \
  54 + PAD_CTL_FSEL2)
  55 +#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PE | PAD_CTL_DSE1)
  56 +
  57 +static iomux_v3_cfg_t const usdhc3_pads[] = {
  58 + IMX8MM_PAD_NAND_WE_B_USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  59 + IMX8MM_PAD_NAND_WP_B_USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  60 + IMX8MM_PAD_NAND_DATA04_USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  61 + IMX8MM_PAD_NAND_DATA05_USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  62 + IMX8MM_PAD_NAND_DATA06_USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  63 + IMX8MM_PAD_NAND_DATA07_USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  64 + IMX8MM_PAD_NAND_RE_B_USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  65 + IMX8MM_PAD_NAND_CE2_B_USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  66 + IMX8MM_PAD_NAND_CE3_B_USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  67 + IMX8MM_PAD_NAND_CLE_USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  68 +};
  69 +
  70 +static iomux_v3_cfg_t const usdhc2_pads[] = {
  71 + IMX8MM_PAD_SD2_CLK_USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  72 + IMX8MM_PAD_SD2_CMD_USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  73 + IMX8MM_PAD_SD2_DATA0_USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  74 + IMX8MM_PAD_SD2_DATA1_USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  75 + IMX8MM_PAD_SD2_DATA2_USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  76 + IMX8MM_PAD_SD2_DATA3_USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  77 + IMX8MM_PAD_SD2_CD_B_GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
  78 + IMX8MM_PAD_SD2_RESET_B_GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
  79 +};
  80 +
  81 +static struct fsl_esdhc_cfg usdhc_cfg[2] = {
  82 + {USDHC2_BASE_ADDR, 0, 1},
  83 + {USDHC3_BASE_ADDR, 0, 1},
  84 +};
  85 +
  86 +int board_mmc_init(bd_t *bis)
  87 +{
  88 + int i, ret;
  89 + /*
  90 + * According to the board_mmc_init() the following map is done:
  91 + * (U-Boot device node) (Physical Port)
  92 + * mmc0 USDHC1
  93 + * mmc1 USDHC2
  94 + */
  95 + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
  96 + switch (i) {
  97 + case 0:
  98 + usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
  99 + imx_iomux_v3_setup_multiple_pads(
  100 + usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
  101 + gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
  102 + gpio_direction_output(USDHC2_PWR_GPIO, 0);
  103 + udelay(500);
  104 + gpio_direction_output(USDHC2_PWR_GPIO, 1);
  105 + break;
  106 + case 1:
  107 + usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC3_CLK_ROOT);
  108 + imx_iomux_v3_setup_multiple_pads(
  109 + usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
  110 + break;
  111 + default:
  112 + printf("Warning: you configured more USDHC controllers"
  113 + "(%d) than supported by the board\n", i + 1);
  114 + return -EINVAL;
  115 + }
  116 +
  117 + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
  118 + if (ret)
  119 + return ret;
  120 + }
  121 +
  122 + return 0;
  123 +}
  124 +
  125 +void spl_board_init(void)
  126 +{
  127 + /* TODO */
  128 + /* enable_tzc380(); */
  129 +
  130 + /* DDR initialization */
  131 + spl_dram_init();
  132 +
  133 + puts("Normal Boot\n");
  134 +}
  135 +
  136 +#ifdef CONFIG_SPL_LOAD_FIT
  137 +int board_fit_config_name_match(const char *name)
  138 +{
  139 + /* Just empty function now - can't decide what to choose */
  140 + debug("%s: %s\n", __func__, name);
  141 +
  142 + return 0;
  143 +}
  144 +#endif
  145 +
  146 +void board_init_f(ulong dummy)
  147 +{
  148 + /* Clear global data */
  149 + memset((void *)gd, 0, sizeof(gd_t));
  150 +
  151 + arch_cpu_init();
  152 +
  153 + board_early_init_f();
  154 +
  155 + timer_init();
  156 +
  157 + preloader_console_init();
  158 +
  159 + /* Clear the BSS. */
  160 + memset(__bss_start, 0, __bss_end - __bss_start);
  161 +
  162 + board_init_r(NULL, 0);
  163 +}
configs/imx8mm_evk_defconfig
Diff comments   View file @ b02221d
  1 +CONFIG_ARM=y
  2 +CONFIG_ARCH_IMX8M=y
  3 +CONFIG_SYS_TEXT_BASE=0x40200000
  4 +CONFIG_SYS_MALLOC_F_LEN=0x2000
  5 +CONFIG_TARGET_IMX8MM_EVK=y
  6 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
  7 +CONFIG_SPL=y
  8 +CONFIG_SPL_BOARD_INIT=y
  9 +CONFIG_HUSH_PARSER=y
  10 +CONFIG_OF_LIBFDT=y
  11 +CONFIG_FS_FAT=y
  12 +CONFIG_CMD_CACHE=y
  13 +CONFIG_CMD_EXT2=y
  14 +CONFIG_CMD_EXT4=y
  15 +CONFIG_CMD_EXT4_WRITE=y
  16 +CONFIG_CMD_FAT=y
  17 +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8mm-evk"
  18 +CONFIG_ENV_IS_IN_MMC=y
  19 +CONFIG_OF_CONTROL=y
  20 +CONFIG_PINCTRL=y
  21 +CONFIG_PINCTRL_IMX8M=y
  22 +CONFIG_SYS_I2C_MXC=y
  23 +CONFIG_CMD_I2C=y
  24 +CONFIG_DM_I2C=y
  25 +CONFIG_DM_GPIO=y
  26 +CONFIG_CMD_GPIO=y
  27 +CONFIG_DM_MMC=y
  28 +CONFIG_CMD_REGULATOR=y
  29 +# CONFIG_DM_PMIC=y
  30 +CONFIG_DM_REGULATOR=y
  31 +CONFIG_DM_REGULATOR_PFUZE100=y
  32 +CONFIG_DM_REGULATOR_FIXED=y
  33 +CONFIG_DM_REGULATOR_GPIO=y
  34 +CONFIG_DM_ETH=y
  35 +CONFIG_CMD_PMIC=y
  36 +CONFIG_NXP_TMU=n
  37 +CONFIG_DM_THERMAL=y
  38 +CONFIG_FIT=y
  39 +CONFIG_SPL_FIT=y
  40 +CONFIG_SPL_LOAD_FIT=y
  41 +CONFIG_BOOTDELAY=-1
  42 +CONFIG_CMD_SF=y
  43 +CONFIG_FSL_FSPI=y
  44 +CONFIG_DM_SPI=y
  45 +CONFIG_DM_SPI_FLASH=y
  46 +CONFIG_SPI_FLASH=y
  47 +CONFIG_SPI_FLASH_STMICRO=y
include/configs/imx8mm_evk.h
Diff comments   View file @ b02221d
  1 +/*
  2 + * Copyright 2018 NXP
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#ifndef __IMX8MM_EVK_H
  8 +#define __IMX8MM_EVK_H
  9 +
  10 +#include <linux/sizes.h>
  11 +#include <asm/arch/imx-regs.h>
  12 +
  13 +#ifdef CONFIG_SECURE_BOOT
  14 +#define CONFIG_CSF_SIZE 0x2000 /* 8K region */
  15 +#endif
  16 +
  17 +#define CONFIG_SPL_TEXT_BASE 0x7E1000
  18 +#define CONFIG_SPL_MAX_SIZE (124 * 1024)
  19 +#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
  20 +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
  21 +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
  22 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
  23 +
  24 +#ifdef CONFIG_SPL_BUILD
  25 +/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
  26 +#define CONFIG_SPL_POWER_SUPPORT
  27 +#define CONFIG_SPL_I2C_SUPPORT
  28 +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
  29 +#define CONFIG_SPL_STACK 0x187FF0
  30 +#define CONFIG_SPL_LIBCOMMON_SUPPORT
  31 +#define CONFIG_SPL_LIBGENERIC_SUPPORT
  32 +#define CONFIG_SPL_SERIAL_SUPPORT
  33 +#define CONFIG_SPL_GPIO_SUPPORT
  34 +#define CONFIG_SPL_MMC_SUPPORT
  35 +#define CONFIG_SPL_BSS_START_ADDR 0x00180000
  36 +#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */
  37 +#define CONFIG_SYS_SPL_MALLOC_START 0x00182000
  38 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x2000 /* 8 KB */
  39 +#define CONFIG_SYS_ICACHE_OFF
  40 +#define CONFIG_SYS_DCACHE_OFF
  41 +
  42 +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */
  43 +
  44 +#undef CONFIG_DM_MMC
  45 +#undef CONFIG_DM_PMIC
  46 +#undef CONFIG_DM_PMIC_PFUZE100
  47 +
  48 +#define CONFIG_SYS_I2C
  49 +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
  50 +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
  51 +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
  52 +
  53 +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  54 +#endif
  55 +
  56 +#define CONFIG_REMAKE_ELF
  57 +
  58 +#define CONFIG_BOARD_EARLY_INIT_F
  59 +#define CONFIG_BOARD_POSTCLK_INIT
  60 +#define CONFIG_BOARD_LATE_INIT
  61 +
  62 +/* Flat Device Tree Definitions */
  63 +#define CONFIG_OF_BOARD_SETUP
  64 +
  65 +#undef CONFIG_CMD_EXPORTENV
  66 +#undef CONFIG_CMD_IMPORTENV
  67 +#undef CONFIG_CMD_IMLS
  68 +
  69 +#undef CONFIG_CMD_CRC32
  70 +#undef CONFIG_BOOTM_NETBSD
  71 +
  72 +/* ENET Config */
  73 +/* ENET1 */
  74 +#if defined(CONFIG_CMD_NET)
  75 +#define CONFIG_CMD_PING
  76 +#define CONFIG_CMD_DHCP
  77 +#define CONFIG_CMD_MII
  78 +#define CONFIG_MII
  79 +#define CONFIG_ETHPRIME "FEC"
  80 +
  81 +#define CONFIG_FEC_MXC
  82 +#define CONFIG_FEC_XCV_TYPE RGMII
  83 +#define CONFIG_FEC_MXC_PHYADDR 0
  84 +#define FEC_QUIRK_ENET_MAC
  85 +
  86 +#define CONFIG_PHY_GIGE
  87 +#define IMX_FEC_BASE 0x30BE0000
  88 +
  89 +#define CONFIG_PHYLIB
  90 +#define CONFIG_PHY_ATHEROS
  91 +#endif
  92 +
  93 +#define CONFIG_MFG_ENV_SETTINGS \
  94 + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \
  95 + "rdinit=/linuxrc " \
  96 + "g_mass_storage.stall=0 g_mass_storage.removable=1 " \
  97 + "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
  98 + "g_mass_storage.iSerialNumber=\"\" "\
  99 + "clk_ignore_unused "\
  100 + "\0" \
  101 + "initrd_addr=0x43800000\0" \
  102 + "initrd_high=0xffffffff\0" \
  103 + "bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
  104 +/* Initial environment variables */
  105 +#define CONFIG_EXTRA_ENV_SETTINGS \
  106 + CONFIG_MFG_ENV_SETTINGS \
  107 + "script=boot.scr\0" \
  108 + "image=Image\0" \
  109 + "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \
  110 + "fdt_addr=0x43000000\0" \
  111 + "fdt_high=0xffffffffffffffff\0" \
  112 + "boot_fdt=try\0" \
  113 + "fdt_file=fsl-imx8mm-evk.dtb\0" \
  114 + "initrd_addr=0x43800000\0" \
  115 + "initrd_high=0xffffffffffffffff\0" \
  116 + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
  117 + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
  118 + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
  119 + "mmcautodetect=yes\0" \
  120 + "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
  121 + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
  122 + "bootscript=echo Running bootscript from mmc ...; " \
  123 + "source\0" \
  124 + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
  125 + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
  126 + "mmcboot=echo Booting from mmc ...; " \
  127 + "run mmcargs; " \
  128 + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
  129 + "if run loadfdt; then " \
  130 + "booti ${loadaddr} - ${fdt_addr}; " \
  131 + "else " \
  132 + "echo WARN: Cannot load the DT; " \
  133 + "fi; " \
  134 + "else " \
  135 + "echo wait for boot; " \
  136 + "fi;\0" \
  137 + "netargs=setenv bootargs console=${console} " \
  138 + "root=/dev/nfs " \
  139 + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
  140 + "netboot=echo Booting from net ...; " \
  141 + "run netargs; " \
  142 + "if test ${ip_dyn} = yes; then " \
  143 + "setenv get_cmd dhcp; " \
  144 + "else " \
  145 + "setenv get_cmd tftp; " \
  146 + "fi; " \
  147 + "${get_cmd} ${loadaddr} ${image}; " \
  148 + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
  149 + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
  150 + "booti ${loadaddr} - ${fdt_addr}; " \
  151 + "else " \
  152 + "echo WARN: Cannot load the DT; " \
  153 + "fi; " \
  154 + "else " \
  155 + "booti; " \
  156 + "fi;\0"
  157 +
  158 +#define CONFIG_BOOTCOMMAND \
  159 + "mmc dev ${mmcdev}; if mmc rescan; then " \
  160 + "if run loadbootscript; then " \
  161 + "run bootscript; " \
  162 + "else " \
  163 + "if run loadimage; then " \
  164 + "run mmcboot; " \
  165 + "else run netboot; " \
  166 + "fi; " \
  167 + "fi; " \
  168 + "else booti ${loadaddr} - ${fdt_addr}; fi"
  169 +
  170 +/* Link Definitions */
  171 +#define CONFIG_LOADADDR 0x40480000
  172 +
  173 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
  174 +
  175 +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
  176 +#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
  177 +#define CONFIG_SYS_INIT_SP_OFFSET \
  178 + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  179 +#define CONFIG_SYS_INIT_SP_ADDR \
  180 + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
  181 +
  182 +#define CONFIG_ENV_OVERWRITE
  183 +#define CONFIG_ENV_OFFSET (64 * SZ_64K)
  184 +#define CONFIG_ENV_SIZE 0x1000
  185 +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC2 */
  186 +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
  187 +
  188 +/* Size of malloc() pool */
  189 +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2*1024) + (16*1024)) * 1024)
  190 +
  191 +#define CONFIG_SYS_SDRAM_BASE 0x40000000
  192 +#define PHYS_SDRAM 0x40000000
  193 +#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
  194 +#define CONFIG_NR_DRAM_BANKS 1
  195 +
  196 +#define CONFIG_BAUDRATE 115200
  197 +
  198 +#define CONFIG_MXC_UART
  199 +#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
  200 +
  201 +/* Monitor Command Prompt */
  202 +#undef CONFIG_SYS_PROMPT
  203 +#define CONFIG_SYS_PROMPT "u-boot=> "
  204 +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  205 +#define CONFIG_SYS_CBSIZE 2048
  206 +#define CONFIG_SYS_MAXARGS 64
  207 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  208 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
  209 + sizeof(CONFIG_SYS_PROMPT) + 16)
  210 +
  211 +#define CONFIG_IMX_BOOTAUX
  212 +
  213 +/* USDHC */
  214 +#define CONFIG_CMD_MMC
  215 +#define CONFIG_FSL_ESDHC
  216 +#define CONFIG_FSL_USDHC
  217 +
  218 +#define CONFIG_SYS_FSL_USDHC_NUM 2
  219 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0
  220 +
  221 +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
  222 +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
  223 +
  224 +#ifdef CONFIG_FSL_FSPI
  225 +#define CONFIG_SF_DEFAULT_BUS 0
  226 +#define CONFIG_SF_DEFAULT_CS 0
  227 +#define CONFIG_SF_DEFAULT_SPEED 40000000
  228 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
  229 +#define FSL_FSPI_FLASH_SIZE SZ_32M
  230 +#define FSL_FSPI_FLASH_NUM 1
  231 +#define FSPI0_BASE_ADDR 0x30bb0000
  232 +#define FSPI0_AMBA_BASE 0x0
  233 +#define CONFIG_SPI_FLASH_BAR
  234 +#define CONFIG_FSPI_QUAD_SUPPORT
  235 +
  236 +#define CONFIG_SYS_FSL_FSPI_AHB
  237 +#endif
  238 +
  239 +/* Enable SPI */
  240 +#ifndef CONFIG_NAND_MXS
  241 +#ifndef CONFIG_FSL_FSPI
  242 +#ifdef CONFIG_CMD_SF
  243 +#define CONFIG_SPI_FLASH
  244 +#define CONFIG_SPI_FLASH_STMICRO
  245 +#define CONFIG_MXC_SPI
  246 +#define CONFIG_SF_DEFAULT_BUS 0
  247 +#define CONFIG_SF_DEFAULT_SPEED 20000000
  248 +#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
  249 +#endif
  250 +#endif
  251 +#endif
  252 +
  253 +#ifdef CONFIG_NAND_MXS
  254 +#define CONFIG_CMD_NAND_TRIMFFS
  255 +
  256 +/* NAND stuff */
  257 +#define CONFIG_SYS_MAX_NAND_DEVICE 1
  258 +#define CONFIG_SYS_NAND_BASE 0x20000000
  259 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE
  260 +#define CONFIG_SYS_NAND_ONFI_DETECTION
  261 +
  262 +/* DMA stuff, needed for GPMI/MXS NAND support */
  263 +#define CONFIG_APBH_DMA
  264 +#define CONFIG_APBH_DMA_BURST
  265 +#define CONFIG_APBH_DMA_BURST8
  266 +#endif
  267 +
  268 +#define CONFIG_MXC_GPIO
  269 +
  270 +#define CONFIG_MXC_OCOTP
  271 +#define CONFIG_CMD_FUSE
  272 +
  273 +#ifndef CONFIG_DM_I2C
  274 +#define CONFIG_SYS_I2C
  275 +#endif
  276 +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
  277 +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
  278 +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
  279 +#define CONFIG_SYS_I2C_SPEED 100000
  280 +
  281 +#endif