Blame view
include/configs/T102xRDB.h
27.6 KB
48c6f328f powerpc/t1024rdb:... |
1 2 3 4 5 6 7 8 9 10 11 12 13 14 |
/* * Copyright 2014 Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ */ /* * T1024/T1023 RDB board configuration file */ #ifndef __T1024RDB_H #define __T1024RDB_H /* High Level Configuration Options */ |
48c6f328f powerpc/t1024rdb:... |
15 16 |
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ #define CONFIG_MP /* support multiple processors */ |
48c6f328f powerpc/t1024rdb:... |
17 18 19 20 21 22 23 24 |
#define CONFIG_ENABLE_36BIT_PHYS #ifdef CONFIG_PHYS_64BIT #define CONFIG_ADDR_MAP 1 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ #endif #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ |
51370d561 ddr: fsl: Merge m... |
25 |
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS |
48c6f328f powerpc/t1024rdb:... |
26 |
|
48c6f328f powerpc/t1024rdb:... |
27 28 29 |
#define CONFIG_ENV_OVERWRITE /* support deep sleep */ |
e5d5f5a8b powerpc: T1024: R... |
30 |
#ifdef CONFIG_ARCH_T1024 |
48c6f328f powerpc/t1024rdb:... |
31 |
#define CONFIG_DEEP_SLEEP |
e8a7f1c32 powerpc/t1023rdb:... |
32 |
#endif |
48c6f328f powerpc/t1024rdb:... |
33 34 35 |
#ifdef CONFIG_RAMBOOT_PBL #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg |
48c6f328f powerpc/t1024rdb:... |
36 37 |
#define CONFIG_SPL_FLUSH_IMAGE #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" |
48c6f328f powerpc/t1024rdb:... |
38 39 40 41 42 43 44 45 46 |
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000 #define CONFIG_SPL_PAD_TO 0x40000 #define CONFIG_SPL_MAX_SIZE 0x28000 #define RESET_VECTOR_OFFSET 0x27FFC #define BOOT_PAGE_OFFSET 0x27000 #ifdef CONFIG_SPL_BUILD #define CONFIG_SPL_SKIP_RELOCATE #define CONFIG_SPL_COMMON_INIT_DDR #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE |
48c6f328f powerpc/t1024rdb:... |
47 48 49 |
#endif #ifdef CONFIG_NAND |
48c6f328f powerpc/t1024rdb:... |
50 |
#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) |
f49b8c1b5 mpc85xx/t102xrdb:... |
51 52 |
#define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 |
48c6f328f powerpc/t1024rdb:... |
53 54 |
#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" |
960286b6d powerpc: T1024RDB... |
55 |
#if defined(CONFIG_TARGET_T1024RDB) |
ec90ac735 Txxx/RCW: Split u... |
56 |
#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_nand_rcw.cfg |
9082405d4 powerpc: T1023RDB... |
57 |
#elif defined(CONFIG_TARGET_T1023RDB) |
ec90ac735 Txxx/RCW: Split u... |
58 59 |
#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_nand_rcw.cfg #endif |
48c6f328f powerpc/t1024rdb:... |
60 61 62 63 |
#define CONFIG_SPL_NAND_BOOT #endif #ifdef CONFIG_SPIFLASH |
f49b8c1b5 mpc85xx/t102xrdb:... |
64 |
#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC |
48c6f328f powerpc/t1024rdb:... |
65 66 |
#define CONFIG_SPL_SPI_FLASH_MINIMAL #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) |
f49b8c1b5 mpc85xx/t102xrdb:... |
67 68 |
#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) |
48c6f328f powerpc/t1024rdb:... |
69 70 71 72 73 |
#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" #ifndef CONFIG_SPL_BUILD #define CONFIG_SYS_MPC85XX_NO_RESETVEC #endif |
960286b6d powerpc: T1024RDB... |
74 |
#if defined(CONFIG_TARGET_T1024RDB) |
ec90ac735 Txxx/RCW: Split u... |
75 |
#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_spi_rcw.cfg |
9082405d4 powerpc: T1023RDB... |
76 |
#elif defined(CONFIG_TARGET_T1023RDB) |
ec90ac735 Txxx/RCW: Split u... |
77 78 |
#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_spi_rcw.cfg #endif |
48c6f328f powerpc/t1024rdb:... |
79 80 81 82 |
#define CONFIG_SPL_SPI_BOOT #endif #ifdef CONFIG_SDCARD |
f49b8c1b5 mpc85xx/t102xrdb:... |
83 |
#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC |
48c6f328f powerpc/t1024rdb:... |
84 |
#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) |
f49b8c1b5 mpc85xx/t102xrdb:... |
85 86 |
#define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) |
48c6f328f powerpc/t1024rdb:... |
87 88 89 90 91 |
#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" #ifndef CONFIG_SPL_BUILD #define CONFIG_SYS_MPC85XX_NO_RESETVEC #endif |
960286b6d powerpc: T1024RDB... |
92 |
#if defined(CONFIG_TARGET_T1024RDB) |
ec90ac735 Txxx/RCW: Split u... |
93 |
#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_sd_rcw.cfg |
9082405d4 powerpc: T1023RDB... |
94 |
#elif defined(CONFIG_TARGET_T1023RDB) |
ec90ac735 Txxx/RCW: Split u... |
95 96 |
#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_sd_rcw.cfg #endif |
48c6f328f powerpc/t1024rdb:... |
97 98 99 100 |
#define CONFIG_SPL_MMC_BOOT #endif #endif /* CONFIG_RAMBOOT_PBL */ |
48c6f328f powerpc/t1024rdb:... |
101 102 103 |
#ifndef CONFIG_RESET_VECTOR_ADDRESS #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc #endif |
e856bdcfb flash: complete C... |
104 |
#ifdef CONFIG_MTD_NOR_FLASH |
48c6f328f powerpc/t1024rdb:... |
105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 |
#define CONFIG_FLASH_CFI_DRIVER #define CONFIG_SYS_FLASH_CFI #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE #endif /* PCIe Boot - Master */ #define CONFIG_SRIO_PCIE_BOOT_MASTER /* * for slave u-boot IMAGE instored in master memory space, * PHYS must be aligned based on the SIZE */ #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ #ifdef CONFIG_PHYS_64BIT #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull #else #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 #endif /* * for slave UCODE and ENV instored in master memory space, * PHYS must be aligned based on the SIZE */ #ifdef CONFIG_PHYS_64BIT #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull #else #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 #endif #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ /* slave core release by master*/ #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ /* PCIe Boot - Slave */ #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) /* Set 1M boot space for PCIe boot */ #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc |
48c6f328f powerpc/t1024rdb:... |
151 152 153 154 |
#endif #if defined(CONFIG_SPIFLASH) #define CONFIG_SYS_EXTRA_ENV_RELOC |
48c6f328f powerpc/t1024rdb:... |
155 156 157 158 159 160 |
#define CONFIG_ENV_SPI_BUS 0 #define CONFIG_ENV_SPI_CS 0 #define CONFIG_ENV_SPI_MAX_HZ 10000000 #define CONFIG_ENV_SPI_MODE 0 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ |
960286b6d powerpc: T1024RDB... |
161 |
#if defined(CONFIG_TARGET_T1024RDB) |
48c6f328f powerpc/t1024rdb:... |
162 |
#define CONFIG_ENV_SECT_SIZE 0x10000 |
9082405d4 powerpc: T1023RDB... |
163 |
#elif defined(CONFIG_TARGET_T1023RDB) |
e8a7f1c32 powerpc/t1023rdb:... |
164 165 |
#define CONFIG_ENV_SECT_SIZE 0x40000 #endif |
48c6f328f powerpc/t1024rdb:... |
166 167 |
#elif defined(CONFIG_SDCARD) #define CONFIG_SYS_EXTRA_ENV_RELOC |
48c6f328f powerpc/t1024rdb:... |
168 169 170 171 172 |
#define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_OFFSET (512 * 0x800) #elif defined(CONFIG_NAND) #define CONFIG_SYS_EXTRA_ENV_RELOC |
48c6f328f powerpc/t1024rdb:... |
173 |
#define CONFIG_ENV_SIZE 0x2000 |
960286b6d powerpc: T1024RDB... |
174 |
#if defined(CONFIG_TARGET_T1024RDB) |
48c6f328f powerpc/t1024rdb:... |
175 |
#define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) |
9082405d4 powerpc: T1023RDB... |
176 |
#elif defined(CONFIG_TARGET_T1023RDB) |
e8a7f1c32 powerpc/t1023rdb:... |
177 178 |
#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) #endif |
48c6f328f powerpc/t1024rdb:... |
179 |
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) |
48c6f328f powerpc/t1024rdb:... |
180 181 182 183 184 |
#define CONFIG_ENV_ADDR 0xffe20000 #define CONFIG_ENV_SIZE 0x2000 #elif defined(CONFIG_ENV_IS_NOWHERE) #define CONFIG_ENV_SIZE 0x2000 #else |
48c6f328f powerpc/t1024rdb:... |
185 186 187 188 |
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ #endif |
48c6f328f powerpc/t1024rdb:... |
189 190 191 192 193 194 |
#ifndef __ASSEMBLY__ unsigned long get_board_sys_clk(void); unsigned long get_board_ddr_clk(void); #endif #define CONFIG_SYS_CLK_FREQ 100000000 |
e8a7f1c32 powerpc/t1023rdb:... |
195 |
#define CONFIG_DDR_CLK_FREQ 100000000 |
48c6f328f powerpc/t1024rdb:... |
196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 |
/* * These can be toggled for performance analysis, otherwise use default. */ #define CONFIG_SYS_CACHE_STASHING #define CONFIG_BACKSIDE_L2_CACHE #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E #define CONFIG_BTB /* toggle branch predition */ #define CONFIG_DDR_ECC #ifdef CONFIG_DDR_ECC #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x00400000 #define CONFIG_SYS_ALT_MEMTEST |
48c6f328f powerpc/t1024rdb:... |
213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 |
/* * Config the L3 Cache as L3 SRAM */ #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 #define CONFIG_SYS_L3_SIZE (256 << 10) #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) #endif #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_DCSRBAR 0xf0000000 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull #endif /* EEPROM */ #define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 0 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 /* * DDR Setup */ #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) |
e8a7f1c32 powerpc/t1023rdb:... |
250 |
#define CONFIG_FSL_DDR_INTERACTIVE |
960286b6d powerpc: T1024RDB... |
251 |
#if defined(CONFIG_TARGET_T1024RDB) |
48c6f328f powerpc/t1024rdb:... |
252 |
#define CONFIG_DDR_SPD |
48c6f328f powerpc/t1024rdb:... |
253 254 |
#define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x51 |
48c6f328f powerpc/t1024rdb:... |
255 |
#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ |
9082405d4 powerpc: T1023RDB... |
256 |
#elif defined(CONFIG_TARGET_T1023RDB) |
e8a7f1c32 powerpc/t1023rdb:... |
257 258 259 |
#define CONFIG_SYS_DDR_RAW_TIMING #define CONFIG_SYS_SDRAM_SIZE 2048 #endif |
48c6f328f powerpc/t1024rdb:... |
260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 |
/* * IFC Definitions */ #define CONFIG_SYS_FLASH_BASE 0xe8000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) #else #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE #endif #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) /* NOR Flash Timing Params */ |
960286b6d powerpc: T1024RDB... |
279 |
#if defined(CONFIG_TARGET_T1024RDB) |
48c6f328f powerpc/t1024rdb:... |
280 |
#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 |
9082405d4 powerpc: T1023RDB... |
281 |
#elif defined(CONFIG_TARGET_T1023RDB) |
ff7ea2d18 powerpc/t1023rdb:... |
282 |
#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \ |
e8a7f1c32 powerpc/t1023rdb:... |
283 284 |
CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN) #endif |
48c6f328f powerpc/t1024rdb:... |
285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 |
#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ FTIM0_NOR_TEADC(0x5) | \ FTIM0_NOR_TEAHC(0x5)) #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ FTIM1_NOR_TRAD_NOR(0x1A) |\ FTIM1_NOR_TSEQRAD_NOR(0x13)) #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ FTIM2_NOR_TCH(0x4) | \ FTIM2_NOR_TWPH(0x0E) | \ FTIM2_NOR_TWP(0x1c)) #define CONFIG_SYS_NOR_FTIM3 0x0 #define CONFIG_SYS_FLASH_QUIET_TEST #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ #define CONFIG_SYS_FLASH_EMPTY_INFO #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} |
960286b6d powerpc: T1024RDB... |
307 |
#ifdef CONFIG_TARGET_T1024RDB |
48c6f328f powerpc/t1024rdb:... |
308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 |
/* CPLD on IFC */ #define CONFIG_SYS_CPLD_BASE 0xffdf0000 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) #define CONFIG_SYS_CSPR2_EXT (0xf) #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) #define CONFIG_SYS_CSOR2 0x0 /* CPLD Timing parameters for IFC CS2 */ #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ FTIM0_GPCM_TEADC(0x0e) | \ FTIM0_GPCM_TEAHC(0x0e)) #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ FTIM1_GPCM_TRAD(0x1f)) #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ FTIM2_GPCM_TCH(0x8) | \ FTIM2_GPCM_TWP(0x1f)) #define CONFIG_SYS_CS2_FTIM3 0x0 |
e8a7f1c32 powerpc/t1023rdb:... |
329 |
#endif |
48c6f328f powerpc/t1024rdb:... |
330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 |
/* NAND Flash on IFC */ #define CONFIG_NAND_FSL_IFC #define CONFIG_SYS_NAND_BASE 0xff800000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) #else #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE #endif #define CONFIG_SYS_NAND_CSPR_EXT (0xf) #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ | CSPR_MSEL_NAND /* MSEL = NAND */ \ | CSPR_V) #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) |
960286b6d powerpc: T1024RDB... |
345 |
#if defined(CONFIG_TARGET_T1024RDB) |
48c6f328f powerpc/t1024rdb:... |
346 347 348 349 350 351 352 |
#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ |
e8a7f1c32 powerpc/t1023rdb:... |
353 |
#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) |
9082405d4 powerpc: T1023RDB... |
354 |
#elif defined(CONFIG_TARGET_T1023RDB) |
7842950f7 powerpc/T102xRDB:... |
355 356 357 |
#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ |
e8a7f1c32 powerpc/t1023rdb:... |
358 359 360 361 362 363 |
| CSOR_NAND_RAL_3 /* RAL 3Bytes */ \ | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \ | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) #endif |
48c6f328f powerpc/t1024rdb:... |
364 365 |
#define CONFIG_SYS_NAND_ONFI_DETECTION |
48c6f328f powerpc/t1024rdb:... |
366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 |
/* ONFI NAND Flash mode0 Timing Params */ #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ FTIM0_NAND_TWP(0x18) | \ FTIM0_NAND_TWCHT(0x07) | \ FTIM0_NAND_TWH(0x0a)) #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ FTIM1_NAND_TWBE(0x39) | \ FTIM1_NAND_TRR(0x0e) | \ FTIM1_NAND_TRP(0x18)) #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ FTIM2_NAND_TREH(0x0a) | \ FTIM2_NAND_TWHRE(0x1e)) #define CONFIG_SYS_NAND_FTIM3 0x0 #define CONFIG_SYS_NAND_DDR_LAW 11 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
48c6f328f powerpc/t1024rdb:... |
383 |
|
48c6f328f powerpc/t1024rdb:... |
384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 |
#if defined(CONFIG_NAND) #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 #else #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 #endif #ifdef CONFIG_SPL_BUILD #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE #else #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE #endif #if defined(CONFIG_RAMBOOT_PBL) #define CONFIG_SYS_RAMBOOT #endif #define CONFIG_BOARD_EARLY_INIT_R #define CONFIG_MISC_INIT_R #define CONFIG_HWCONFIG /* define to use L1 as initial stack */ #define CONFIG_L1_INIT_RAM #define CONFIG_SYS_INIT_RAM_LOCK #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf |
b3142e2cf powerpc: configs:... |
441 |
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 |
48c6f328f powerpc/t1024rdb:... |
442 443 444 445 446 |
/* The assembler doesn't like typecast */ #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) #else |
b3142e2cf powerpc: configs:... |
447 |
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ |
48c6f328f powerpc/t1024rdb:... |
448 449 450 451 452 453 454 455 456 457 458 459 460 461 |
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS #endif #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_LEN (768 * 1024) #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) /* Serial Port */ #define CONFIG_CONS_INDEX 1 |
48c6f328f powerpc/t1024rdb:... |
462 463 464 465 466 467 468 469 470 471 472 |
#define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) |
48c6f328f powerpc/t1024rdb:... |
473 |
|
48c6f328f powerpc/t1024rdb:... |
474 475 476 477 |
/* Video */ #undef CONFIG_FSL_DIU_FB /* RDB doesn't support DIU */ #ifdef CONFIG_FSL_DIU_FB #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) |
48c6f328f powerpc/t1024rdb:... |
478 479 480 481 482 483 484 485 486 |
#define CONFIG_VIDEO_LOGO #define CONFIG_VIDEO_BMP_LOGO #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS /* * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so * disable empty flash sector detection, which is I/O-intensive. */ #undef CONFIG_SYS_FLASH_EMPTY_INFO #endif |
48c6f328f powerpc/t1024rdb:... |
487 488 489 490 491 492 493 494 495 |
/* I2C */ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 |
ff7ea2d18 powerpc/t1023rdb:... |
496 497 |
#define I2C_PCA6408_BUS_NUM 1 #define I2C_PCA6408_ADDR 0x20 |
48c6f328f powerpc/t1024rdb:... |
498 499 500 501 502 503 504 505 506 507 508 509 510 511 |
/* I2C bus multiplexer */ #define I2C_MUX_CH_DEFAULT 0x8 /* * RTC configuration */ #define RTC #define CONFIG_RTC_DS1337 1 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* * eSPI - Enhanced SPI */ |
48c6f328f powerpc/t1024rdb:... |
512 513 514 515 516 517 518 519 |
#define CONFIG_SPI_FLASH_BAR #define CONFIG_SF_DEFAULT_SPEED 10000000 #define CONFIG_SF_DEFAULT_MODE 0 /* * General PCIe * Memory space is mapped 1-1, but I/O space must start from 0. */ |
b38eaec53 include/configs: ... |
520 521 522 |
#define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE3 /* PCIE controller 3 */ |
5d7370107 powerpc: T1040: R... |
523 |
#ifdef CONFIG_ARCH_T1040 |
b38eaec53 include/configs: ... |
524 |
#define CONFIG_PCIE4 /* PCIE controller 4 */ |
48c6f328f powerpc/t1024rdb:... |
525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 |
#endif #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ #define CONFIG_PCI_INDIRECT_BRIDGE #ifdef CONFIG_PCI /* controller 1, direct to uli, tgtid 3, Base address 20000 */ #ifdef CONFIG_PCIE1 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull #else #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 #endif #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull #else #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 #endif #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ #endif /* controller 2, Slot 2, tgtid 2, Base address 201000 */ #ifdef CONFIG_PCIE2 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull #else #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 #endif #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull #else #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 #endif #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ #endif /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #ifdef CONFIG_PCIE3 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull #else #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 #endif #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull #else #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 #endif #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ #endif /* controller 4, Base address 203000, to be removed */ #ifdef CONFIG_PCIE4 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull #else #define CONFIG_SYS_PCIE4_MEM_BUS 0xb0000000 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xb0000000 #endif #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull #else #define CONFIG_SYS_PCIE4_IO_PHYS 0xf8030000 #endif #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ #endif |
48c6f328f powerpc/t1024rdb:... |
614 |
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
48c6f328f powerpc/t1024rdb:... |
615 616 617 618 619 620 621 622 |
#endif /* CONFIG_PCI */ /* * USB */ #define CONFIG_HAS_FSL_DR_USB #ifdef CONFIG_HAS_FSL_DR_USB |
48c6f328f powerpc/t1024rdb:... |
623 624 |
#define CONFIG_USB_EHCI_FSL #define CONFIG_EHCI_HCD_INIT_AFTER_RESET |
48c6f328f powerpc/t1024rdb:... |
625 626 627 628 629 |
#endif /* * SDHC */ |
48c6f328f powerpc/t1024rdb:... |
630 631 632 |
#ifdef CONFIG_MMC #define CONFIG_FSL_ESDHC #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR |
48c6f328f powerpc/t1024rdb:... |
633 634 635 636 |
#endif /* Qman/Bman */ #ifndef CONFIG_NOBQFMAN |
2a8b34220 powerpc/T10xx: Fi... |
637 |
#define CONFIG_SYS_BMAN_NUM_PORTALS 10 |
48c6f328f powerpc/t1024rdb:... |
638 639 640 641 642 643 644 |
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull #else #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE #endif #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 |
3fa66db45 mpc85xx: inhibit ... |
645 646 647 648 649 650 651 652 |
#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ CONFIG_SYS_BMAN_CENA_SIZE) #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 |
2a8b34220 powerpc/T10xx: Fi... |
653 |
#define CONFIG_SYS_QMAN_NUM_PORTALS 10 |
48c6f328f powerpc/t1024rdb:... |
654 655 656 657 658 659 660 |
#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull #else #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE #endif #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 |
3fa66db45 mpc85xx: inhibit ... |
661 662 663 664 665 666 667 668 |
#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ CONFIG_SYS_QMAN_CENA_SIZE) #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 |
48c6f328f powerpc/t1024rdb:... |
669 670 |
#define CONFIG_SYS_DPAA_FMAN |
960286b6d powerpc: T1024RDB... |
671 |
#ifdef CONFIG_TARGET_T1024RDB |
48c6f328f powerpc/t1024rdb:... |
672 673 |
#define CONFIG_QE #define CONFIG_U_QE |
ff7ea2d18 powerpc/t1023rdb:... |
674 |
#endif |
48c6f328f powerpc/t1024rdb:... |
675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 |
/* Default address of microcode for the Linux FMan driver */ #if defined(CONFIG_SPIFLASH) /* * env is stored at 0x100000, sector size is 0x10000, ucode is stored after * env, so we got 0x110000. */ #define CONFIG_SYS_QE_FW_IN_SPIFLASH #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 #define CONFIG_SYS_QE_FW_ADDR 0x130000 #elif defined(CONFIG_SDCARD) /* * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is * about 1MB (2048 blocks), Env is stored after the image, and the env size is * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). */ #define CONFIG_SYS_QE_FMAN_FW_IN_MMC #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND |
960286b6d powerpc: T1024RDB... |
695 |
#if defined(CONFIG_TARGET_T1024RDB) |
48c6f328f powerpc/t1024rdb:... |
696 697 |
#define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) #define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) |
9082405d4 powerpc: T1023RDB... |
698 |
#elif defined(CONFIG_TARGET_T1023RDB) |
e8a7f1c32 powerpc/t1023rdb:... |
699 700 701 |
#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE) #endif |
48c6f328f powerpc/t1024rdb:... |
702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 |
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) /* * Slave has no ucode locally, it can fetch this from remote. When implementing * in two corenet boards, slave's ucode could be stored in master's memory * space, the address can be mapped from slave TLB->slave LAW-> * slave SRIO or PCIE outbound window->master inbound window-> * master LAW->the ucode address in master's memory space. */ #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) #endif /* CONFIG_NOBQFMAN */ #ifdef CONFIG_SYS_DPAA_FMAN #define CONFIG_FMAN_ENET #define CONFIG_PHYLIB_10G #define CONFIG_PHY_REALTEK |
e26416a3f powerpc/t1024rdb:... |
725 |
#define CONFIG_PHY_AQUANTIA |
960286b6d powerpc: T1024RDB... |
726 |
#if defined(CONFIG_TARGET_T1024RDB) |
48c6f328f powerpc/t1024rdb:... |
727 728 |
#define RGMII_PHY1_ADDR 0x2 #define RGMII_PHY2_ADDR 0x6 |
e8a7f1c32 powerpc/t1023rdb:... |
729 |
#define SGMII_AQR_PHY_ADDR 0x2 |
48c6f328f powerpc/t1024rdb:... |
730 |
#define FM1_10GEC1_PHY_ADDR 0x1 |
9082405d4 powerpc: T1023RDB... |
731 |
#elif defined(CONFIG_TARGET_T1023RDB) |
e8a7f1c32 powerpc/t1023rdb:... |
732 733 734 735 |
#define RGMII_PHY1_ADDR 0x1 #define SGMII_RTK_PHY_ADDR 0x3 #define SGMII_AQR_PHY_ADDR 0x2 #endif |
48c6f328f powerpc/t1024rdb:... |
736 737 738 739 740 |
#endif #ifdef CONFIG_FMAN_ENET #define CONFIG_MII /* MII PHY management */ #define CONFIG_ETHPRIME "FM1@DTSEC4" |
48c6f328f powerpc/t1024rdb:... |
741 742 743 744 745 |
#endif /* * Dynamic MTD Partition support with mtdparts */ |
e856bdcfb flash: complete C... |
746 |
#ifdef CONFIG_MTD_NOR_FLASH |
48c6f328f powerpc/t1024rdb:... |
747 748 |
#define CONFIG_MTD_DEVICE #define CONFIG_MTD_PARTITIONS |
48c6f328f powerpc/t1024rdb:... |
749 |
#define CONFIG_FLASH_CFI_MTD |
48c6f328f powerpc/t1024rdb:... |
750 751 752 753 754 755 756 757 758 |
#endif /* * Environment */ #define CONFIG_LOADS_ECHO /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ /* |
48c6f328f powerpc/t1024rdb:... |
759 760 |
* Miscellaneous configurable options */ |
48c6f328f powerpc/t1024rdb:... |
761 |
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
48c6f328f powerpc/t1024rdb:... |
762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 |
/* * For booting Linux, the board info and command line data * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ #ifdef CONFIG_CMD_KGDB #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #endif /* * Environment Configuration */ #define CONFIG_ROOTPATH "/opt/nfsroot" #define CONFIG_BOOTFILE "uImage" |
e8a7f1c32 powerpc/t1023rdb:... |
780 |
#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ |
48c6f328f powerpc/t1024rdb:... |
781 |
#define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ |
48c6f328f powerpc/t1024rdb:... |
782 |
#define __USB_PHY_TYPE utmi |
e5d5f5a8b powerpc: T1024: R... |
783 |
#ifdef CONFIG_ARCH_T1024 |
e8a7f1c32 powerpc/t1023rdb:... |
784 785 |
#define CONFIG_BOARDNAME t1024rdb #define BANK_INTLV cs0_cs1 |
48c6f328f powerpc/t1024rdb:... |
786 |
#else |
e8a7f1c32 powerpc/t1023rdb:... |
787 788 |
#define CONFIG_BOARDNAME t1023rdb #define BANK_INTLV null |
48c6f328f powerpc/t1024rdb:... |
789 790 791 792 |
#endif #define CONFIG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ |
e8a7f1c32 powerpc/t1023rdb:... |
793 |
"bank_intlv=" __stringify(BANK_INTLV) "\0" \ |
48c6f328f powerpc/t1024rdb:... |
794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 |
"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \ "fdtfile=" __stringify(CONFIG_BOARDNAME) "/" \ __stringify(CONFIG_BOARDNAME) ".dtb\0" \ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ "netdev=eth0\0" \ "tftpflash=tftpboot $loadaddr $uboot && " \ "protect off $ubootaddr +$filesize && " \ "erase $ubootaddr +$filesize && " \ "cp.b $loadaddr $ubootaddr $filesize && " \ "protect on $ubootaddr +$filesize && " \ "cmp.b $loadaddr $ubootaddr $filesize\0" \ "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ |
b24a4f624 powerpc/85xx: Inc... |
810 |
"fdtaddr=1e00000\0" \ |
48c6f328f powerpc/t1024rdb:... |
811 812 813 814 815 816 817 818 819 |
"bdev=sda3\0" #define CONFIG_LINUX \ "setenv bootargs root=/dev/ram rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "setenv ramdiskaddr 0x02000000;" \ "setenv fdtaddr 0x00c00000;" \ "setenv loadaddr 0x1000000;" \ "bootm $loadaddr $ramdiskaddr $fdtaddr" |
48c6f328f powerpc/t1024rdb:... |
820 821 822 823 824 825 826 827 828 829 |
#define CONFIG_NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ "nfsroot=$serverip:$rootpath " \ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $loadaddr $bootfile;" \ "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr - $fdtaddr" #define CONFIG_BOOTCOMMAND CONFIG_LINUX |
48c6f328f powerpc/t1024rdb:... |
830 |
#include <asm/fsl_secure_boot.h> |
ef6c55a24 secure_boot: incl... |
831 |
|
48c6f328f powerpc/t1024rdb:... |
832 |
#endif /* __T1024RDB_H */ |