arm: mx6: cm_fx6: add ethernet support

Add ethernet support for Compulab CM-FX6 CoM Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@ti.com> Acked-by: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>

arm: mx6: cm_fx6: add ethernet support
Add ethernet support for Compulab CM-FX6 CoM Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@ti.com> Acked-by: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Nikita Kiryanov · Stefano Babic
1 parent a6b0652bb5
Showing 3 changed files with 115 additions and 2 deletions Side-by-side Diff
board/compulab/cm_fx6/cm_fx6.c
board/compulab/cm_fx6/common.h
include/configs/cm_fx6.h
@@ -10,13 +10,100 @@
  
 #include <common.h>
 #include <fsl_esdhc.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <fdt_support.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/io.h>
+#include <asm/gpio.h>
 #include "common.h"
  
 DECLARE_GLOBAL_DATA_PTR;
  
+#ifdef CONFIG_FEC_MXC
+#define ENET_PAD_CTRL		(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+				 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+static int mx6_rgmii_rework(struct phy_device *phydev)
+{
+	unsigned short val;
+
+	/* Ar8031 phy SmartEEE feature cause link status generates glitch,
+	 * which cause ethernet link down/up issue, so disable SmartEEE
+	 */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003);
+	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
+	val &= ~(0x1 << 8);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
+
+	/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
+
+	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
+	val &= 0xffe3;
+	val |= 0x18;
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
+
+	/* introduce tx clock delay */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
+	val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
+	val |= 0x0100;
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
+
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	mx6_rgmii_rework(phydev);
+
+	if (phydev->drv->config)
+		return phydev->drv->config(phydev);
+
+	return 0;
+}
+
+static iomux_v3_cfg_t const enet_pads[] = {
+	IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_ENET_MDC__ENET_MDC   | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_GPIO_0__CCM_CLKO1    | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_GPIO_3__CCM_CLKO2    | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(0x84)),
+	IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK  |
+						MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
+						MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
+						MUX_PAD_CTRL(ENET_PAD_CTRL)),
+};
+
+int board_eth_init(bd_t *bis)
+{
+	SETUP_IOMUX_PADS(enet_pads);
+	/* phy reset */
+	gpio_direction_output(CM_FX6_ENET_NRST, 0);
+	udelay(500);
+	gpio_set_value(CM_FX6_ENET_NRST, 1);
+	enable_enet_clk(1);
+	return cpu_eth_init(bis);
+}
+#endif
+
 #ifdef CONFIG_NAND_MXS
 static iomux_v3_cfg_t const nand_pads[] = {
 	IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
@@ -76,6 +163,19 @@
 	}
  
 	return 0;
+}
+#endif
+
+#ifdef CONFIG_OF_BOARD_SETUP
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	uint8_t enetaddr[6];
+
+	/* MAC addr */
+	if (eth_getenv_enetaddr("ethaddr", enetaddr)) {
+		fdt_find_and_setprop(blob, "/fec", "local-mac-address",
+				     enetaddr, 6, 1);
+	}
 }
 #endif
  
@@ -15,6 +15,7 @@
  
 #define CM_FX6_ECSPI_BUS0_CS0	IMX_GPIO_NR(2, 30)
 #define CM_FX6_GREEN_LED	IMX_GPIO_NR(2, 31)
+#define CM_FX6_ENET_NRST	IMX_GPIO_NR(2, 8)
  
 void cm_fx6_set_usdhc_iomux(void);
 void cm_fx6_set_ecspi_iomux(void);
@@ -35,8 +35,6 @@
 #undef CONFIG_CMD_XIMG
 #undef CONFIG_CMD_FPGA
 #undef CONFIG_CMD_IMLS
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
  
 /* MMC */
 #define CONFIG_MMC
@@ -189,6 +187,19 @@
 #define CONFIG_APBH_DMA_BURST8
 #endif
  
+/* Ethernet */
+#define CONFIG_FEC_MXC
+#define CONFIG_FEC_MXC_PHYADDR		0
+#define CONFIG_FEC_XCV_TYPE		RGMII
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_ATHEROS
+#define CONFIG_MII
+#define CONFIG_ETHPRIME			"FEC0"
+#define CONFIG_ARP_TIMEOUT		200UL
+#define CONFIG_NETMASK			255.255.255.0
+#define CONFIG_NET_RETRY_COUNT		5
+
 /* GPIO */
 #define CONFIG_MXC_GPIO
  
@@ -206,6 +217,7 @@
 #define CONFIG_STACKSIZE			(128 * 1024)
 #define CONFIG_SYS_MALLOC_LEN			(2 * 1024 * 1024)
 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	800 /* 400 KB */
+#define CONFIG_OF_BOARD_SETUP
  
 /* SPL */
 #include "imx6_spl.h"
...	...	@@ -10,13 +10,100 @@
10	10
11	11	#include <common.h>
12	12	#include <fsl_esdhc.h>
	13	+#include <miiphy.h>
	14	+#include <netdev.h>
	15	+#include <fdt_support.h>
13	16	#include <asm/arch/crm_regs.h>
14	17	#include <asm/arch/sys_proto.h>
15	18	#include <asm/io.h>
	19	+#include <asm/gpio.h>
16	20	#include "common.h"
17	21
18	22	DECLARE_GLOBAL_DATA_PTR;
19	23
	24	+#ifdef CONFIG_FEC_MXC
	25	+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP \| PAD_CTL_SPEED_MED \| \
	26	+ PAD_CTL_DSE_40ohm \| PAD_CTL_HYS)
	27	+
	28	+static int mx6_rgmii_rework(struct phy_device *phydev)
	29	+{
	30	+ unsigned short val;
	31	+
	32	+ /* Ar8031 phy SmartEEE feature cause link status generates glitch,
	33	+ * which cause ethernet link down/up issue, so disable SmartEEE
	34	+ */
	35	+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3);
	36	+ phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d);
	37	+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003);
	38	+ val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
	39	+ val &= ~(0x1 << 8);
	40	+ phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
	41	+
	42	+ /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
	43	+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
	44	+ phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
	45	+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
	46	+
	47	+ val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
	48	+ val &= 0xffe3;
	49	+ val \|= 0x18;
	50	+ phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
	51	+
	52	+ /* introduce tx clock delay */
	53	+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
	54	+ val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
	55	+ val \|= 0x0100;
	56	+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
	57	+
	58	+ return 0;
	59	+}
	60	+
	61	+int board_phy_config(struct phy_device *phydev)
	62	+{
	63	+ mx6_rgmii_rework(phydev);
	64	+
	65	+ if (phydev->drv->config)
	66	+ return phydev->drv->config(phydev);
	67	+
	68	+ return 0;
	69	+}
	70	+
	71	+static iomux_v3_cfg_t const enet_pads[] = {
	72	+ IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	73	+ IOMUX_PADS(PAD_ENET_MDC__ENET_MDC \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	74	+ IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	75	+ IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	76	+ IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	77	+ IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	78	+ IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	79	+ IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	80	+ IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	81	+ IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	82	+ IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	83	+ IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	84	+ IOMUX_PADS(PAD_GPIO_0__CCM_CLKO1 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	85	+ IOMUX_PADS(PAD_GPIO_3__CCM_CLKO2 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	86	+ IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 \| MUX_PAD_CTRL(0x84)),
	87	+ IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK \|
	88	+ MUX_PAD_CTRL(ENET_PAD_CTRL)),
	89	+ IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL \|
	90	+ MUX_PAD_CTRL(ENET_PAD_CTRL)),
	91	+ IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL \|
	92	+ MUX_PAD_CTRL(ENET_PAD_CTRL)),
	93	+};
	94	+
	95	+int board_eth_init(bd_t *bis)
	96	+{
	97	+ SETUP_IOMUX_PADS(enet_pads);
	98	+ /* phy reset */
	99	+ gpio_direction_output(CM_FX6_ENET_NRST, 0);
	100	+ udelay(500);
	101	+ gpio_set_value(CM_FX6_ENET_NRST, 1);
	102	+ enable_enet_clk(1);
	103	+ return cpu_eth_init(bis);
	104	+}
	105	+#endif
	106	+
20	107	#ifdef CONFIG_NAND_MXS
21	108	static iomux_v3_cfg_t const nand_pads[] = {
22	109	IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE \| MUX_PAD_CTRL(NO_PAD_CTRL)),
...	...	@@ -76,6 +163,19 @@
76	163	}
77	164
78	165	return 0;
	166	+}
	167	+#endif
	168	+
	169	+#ifdef CONFIG_OF_BOARD_SETUP
	170	+void ft_board_setup(void blob, bd_t bd)
	171	+{
	172	+ uint8_t enetaddr[6];
	173	+
	174	+ /* MAC addr */
	175	+ if (eth_getenv_enetaddr("ethaddr", enetaddr)) {
	176	+ fdt_find_and_setprop(blob, "/fec", "local-mac-address",
	177	+ enetaddr, 6, 1);
	178	+ }
79	179	}
80	180	#endif
81	181
...	...	@@ -15,6 +15,7 @@
15	15
16	16	#define CM_FX6_ECSPI_BUS0_CS0 IMX_GPIO_NR(2, 30)
17	17	#define CM_FX6_GREEN_LED IMX_GPIO_NR(2, 31)
	18	+#define CM_FX6_ENET_NRST IMX_GPIO_NR(2, 8)
18	19
19	20	void cm_fx6_set_usdhc_iomux(void);
20	21	void cm_fx6_set_ecspi_iomux(void);
...	...	@@ -35,8 +35,6 @@
35	35	#undef CONFIG_CMD_XIMG
36	36	#undef CONFIG_CMD_FPGA
37	37	#undef CONFIG_CMD_IMLS
38		-#undef CONFIG_CMD_NET
39		-#undef CONFIG_CMD_NFS
40	38
41	39	/* MMC */
42	40	#define CONFIG_MMC
...	...	@@ -189,6 +187,19 @@
189	187	#define CONFIG_APBH_DMA_BURST8
190	188	#endif
191	189
	190	+/* Ethernet */
	191	+#define CONFIG_FEC_MXC
	192	+#define CONFIG_FEC_MXC_PHYADDR 0
	193	+#define CONFIG_FEC_XCV_TYPE RGMII
	194	+#define IMX_FEC_BASE ENET_BASE_ADDR
	195	+#define CONFIG_PHYLIB
	196	+#define CONFIG_PHY_ATHEROS
	197	+#define CONFIG_MII
	198	+#define CONFIG_ETHPRIME "FEC0"
	199	+#define CONFIG_ARP_TIMEOUT 200UL
	200	+#define CONFIG_NETMASK 255.255.255.0
	201	+#define CONFIG_NET_RETRY_COUNT 5
	202	+
192	203	/* GPIO */
193	204	#define CONFIG_MXC_GPIO
194	205
...	...	@@ -206,6 +217,7 @@
206	217	#define CONFIG_STACKSIZE (128 * 1024)
207	218	#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024)
208	219	#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800 /* 400 KB */
	220	+#define CONFIG_OF_BOARD_SETUP
209	221
210	222	/* SPL */
211	223	#include "imx6_spl.h"