arm: socfpga: clock: Sync with reference code

Add the missing pieces from the reference clock code from Altera. This puts the code on par with the Altera U-Boot fork for all but the SDRAM self-refresh bits, which are not part of this patch. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>

arm: socfpga: clock: Sync with reference code
Add the missing pieces from the reference clock code from Altera. This puts the code on par with the Altera U-Boot fork for all but the SDRAM self-refresh bits, which are not part of this patch. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
Marek Vasut
1 parent 44428ab6ab
Showing 2 changed files with 29 additions and 16 deletions Side-by-side Diff
arch/arm/cpu/armv7/socfpga/clock_manager.c
arch/arm/include/asm/arch-socfpga/clock_manager.h
@@ -16,9 +16,16 @@
 static void cm_wait_for_lock(uint32_t mask)
 {
 	register uint32_t inter_val;
+	uint32_t retry = 0;
 	do {
 		inter_val = readl(&clock_manager_base->inter) & mask;
-	} while (inter_val != mask);
+		if (inter_val == mask)
+			retry++;
+		else
+			retry = 0;
+		if (retry >= 10)
+			break;
+	} while (1);
 }
  
 /* function to poll in the fsm busy bit */
  
  
@@ -114,15 +121,15 @@
 	cm_write_bypass(CLKMGR_BYPASS_PERPLL | CLKMGR_BYPASS_SDRPLL |
 			CLKMGR_BYPASS_MAINPLL);
  
-	/*
-	 * Put all plls VCO registers back to reset value.
-	 * Some code might have messed with them.
-	 */
-	writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE,
+	/* Put all plls VCO registers back to reset value. */
+	writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE &
+	       ~CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK,
 	       &clock_manager_base->main_pll.vco);
-	writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE,
+	writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE &
+	       ~CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK,
 	       &clock_manager_base->per_pll.vco);
-	writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE,
+	writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE &
+	       ~CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
 	       &clock_manager_base->sdr_pll.vco);
  
 	/*
  
@@ -147,15 +154,10 @@
 	 * We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN
 	 * with numerator and denominator.
 	 */
-	writel(cfg->main_vco_base | CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK,
-	       &clock_manager_base->main_pll.vco);
+	writel(cfg->main_vco_base, &clock_manager_base->main_pll.vco);
+	writel(cfg->peri_vco_base, &clock_manager_base->per_pll.vco);
+	writel(cfg->sdram_vco_base, &clock_manager_base->sdr_pll.vco);
  
-	writel(cfg->peri_vco_base | CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK,
-	       &clock_manager_base->per_pll.vco);
-
-	writel(cfg->sdram_vco_base | CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
-	       &clock_manager_base->sdr_pll.vco);
-
 	/*
 	 * Time starts here
 	 * must wait 7 us from BGPWRDN_SET(0) to VCO_ENABLE_SET(1)
@@ -189,6 +191,9 @@
 	writel(cfg->perqspiclk, &clock_manager_base->per_pll.perqspiclk);
  
 	/* Peri pernandsdmmcclk */
+	writel(cfg->mainnandsdmmcclk,
+	       &clock_manager_base->main_pll.mainnandsdmmcclk);
+
 	writel(cfg->pernandsdmmcclk,
 	       &clock_manager_base->per_pll.pernandsdmmcclk);
  
@@ -318,6 +323,11 @@
 	writel(~0, &clock_manager_base->main_pll.en);
 	writel(~0, &clock_manager_base->per_pll.en);
 	writel(~0, &clock_manager_base->sdr_pll.en);
+
+	/* Clear the loss of lock bits (write 1 to clear) */
+	writel(CLKMGR_INTER_SDRPLLLOST_MASK | CLKMGR_INTER_PERPLLLOST_MASK |
+	       CLKMGR_INTER_MAINPLLLOST_MASK,
+	       &clock_manager_base->inter);
 }
  
 static unsigned int cm_get_main_vco_clk_hz(void)
@@ -135,6 +135,9 @@
 #define CLKMGR_INTER_SDRPLLLOCKED_MASK			0x00000100
 #define CLKMGR_INTER_PERPLLLOCKED_MASK			0x00000080
 #define CLKMGR_INTER_MAINPLLLOCKED_MASK			0x00000040
+#define CLKMGR_INTER_PERPLLLOST_MASK			0x00000010
+#define CLKMGR_INTER_SDRPLLLOST_MASK			0x00000020
+#define CLKMGR_INTER_MAINPLLLOST_MASK			0x00000008
  
 #define CLKMGR_STAT_BUSY				(1 << 0)
...	...	@@ -16,9 +16,16 @@
16	16	static void cm_wait_for_lock(uint32_t mask)
17	17	{
18	18	register uint32_t inter_val;
	19	+ uint32_t retry = 0;
19	20	do {
20	21	inter_val = readl(&clock_manager_base->inter) & mask;
21		- } while (inter_val != mask);
	22	+ if (inter_val == mask)
	23	+ retry++;
	24	+ else
	25	+ retry = 0;
	26	+ if (retry >= 10)
	27	+ break;
	28	+ } while (1);
22	29	}
23	30
24	31	/* function to poll in the fsm busy bit */
25	32
26	33
...	...	@@ -114,15 +121,15 @@
114	121	cm_write_bypass(CLKMGR_BYPASS_PERPLL \| CLKMGR_BYPASS_SDRPLL \|
115	122	CLKMGR_BYPASS_MAINPLL);
116	123
117		- /*
118		- * Put all plls VCO registers back to reset value.
119		- * Some code might have messed with them.
120		- */
121		- writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE,
	124	+ /* Put all plls VCO registers back to reset value. */
	125	+ writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE &
	126	+ ~CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK,
122	127	&clock_manager_base->main_pll.vco);
123		- writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE,
	128	+ writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE &
	129	+ ~CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK,
124	130	&clock_manager_base->per_pll.vco);
125		- writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE,
	131	+ writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE &
	132	+ ~CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
126	133	&clock_manager_base->sdr_pll.vco);
127	134
128	135	/*
129	136
...	...	@@ -147,15 +154,10 @@
147	154	* We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN
148	155	* with numerator and denominator.
149	156	*/
150		- writel(cfg->main_vco_base \| CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK,
151		- &clock_manager_base->main_pll.vco);
	157	+ writel(cfg->main_vco_base, &clock_manager_base->main_pll.vco);
	158	+ writel(cfg->peri_vco_base, &clock_manager_base->per_pll.vco);
	159	+ writel(cfg->sdram_vco_base, &clock_manager_base->sdr_pll.vco);
152	160
153		- writel(cfg->peri_vco_base \| CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK,
154		- &clock_manager_base->per_pll.vco);
155		-
156		- writel(cfg->sdram_vco_base \| CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
157		- &clock_manager_base->sdr_pll.vco);
158		-
159	161	/*
160	162	* Time starts here
161	163	* must wait 7 us from BGPWRDN_SET(0) to VCO_ENABLE_SET(1)
...	...	@@ -189,6 +191,9 @@
189	191	writel(cfg->perqspiclk, &clock_manager_base->per_pll.perqspiclk);
190	192
191	193	/* Peri pernandsdmmcclk */
	194	+ writel(cfg->mainnandsdmmcclk,
	195	+ &clock_manager_base->main_pll.mainnandsdmmcclk);
	196	+
192	197	writel(cfg->pernandsdmmcclk,
193	198	&clock_manager_base->per_pll.pernandsdmmcclk);
194	199
...	...	@@ -318,6 +323,11 @@
318	323	writel(~0, &clock_manager_base->main_pll.en);
319	324	writel(~0, &clock_manager_base->per_pll.en);
320	325	writel(~0, &clock_manager_base->sdr_pll.en);
	326	+
	327	+ /* Clear the loss of lock bits (write 1 to clear) */
	328	+ writel(CLKMGR_INTER_SDRPLLLOST_MASK \| CLKMGR_INTER_PERPLLLOST_MASK \|
	329	+ CLKMGR_INTER_MAINPLLLOST_MASK,
	330	+ &clock_manager_base->inter);
321	331	}
322	332
323	333	static unsigned int cm_get_main_vco_clk_hz(void)
...	...	@@ -135,6 +135,9 @@
135	135	#define CLKMGR_INTER_SDRPLLLOCKED_MASK 0x00000100
136	136	#define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000080
137	137	#define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000040
	138	+#define CLKMGR_INTER_PERPLLLOST_MASK 0x00000010
	139	+#define CLKMGR_INTER_SDRPLLLOST_MASK 0x00000020
	140	+#define CLKMGR_INTER_MAINPLLLOST_MASK 0x00000008
138	141
139	142	#define CLKMGR_STAT_BUSY (1 << 0)
140	143