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Commit 44428ab6abbba58aa90b982d4d41b39cbcbec966

Authored by Marek Vasut
1 parent 5d8ad0cd3a
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

arm: socfpga: clock: Clean up bit definitions 

Clean up the clock code definitions so they are aligned with mainline
standards. There are no functional changes in this patch.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>

Showing 3 changed files with 323 additions and 303 deletions Side-by-side Diff

arch/arm/cpu/armv7/socfpga/clock_manager.c
Diff comments   View file @ 44428ab
... ... @@ -13,25 +13,6 @@
13 13 static const struct socfpga_clock_manager *clock_manager_base =
14 14 (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
15 15  
16   -#define CLKMGR_BYPASS_ENABLE 1
17   -#define CLKMGR_BYPASS_DISABLE 0
18   -#define CLKMGR_STAT_IDLE 0
19   -#define CLKMGR_STAT_BUSY 1
20   -#define CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1 0
21   -#define CLKMGR_BYPASS_PERPLLSRC_SELECT_INPUT_MUX 1
22   -#define CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1 0
23   -#define CLKMGR_BYPASS_SDRPLLSRC_SELECT_INPUT_MUX 1
24   -
25   -#define CLEAR_BGP_EN_PWRDN \
26   - (CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)| \
27   - CLKMGR_MAINPLLGRP_VCO_EN_SET(0)| \
28   - CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0))
29   -
30   -#define VCO_EN_BASE \
31   - (CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)| \
32   - CLKMGR_MAINPLLGRP_VCO_EN_SET(1)| \
33   - CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0))
34   -
35 16 static void cm_wait_for_lock(uint32_t mask)
36 17 {
37 18 register uint32_t inter_val;
... ... @@ -130,14 +111,8 @@
130 111 writel(0, &clock_manager_base->per_pll.en);
131 112  
132 113 /* Put all plls in bypass */
133   - cm_write_bypass(
134   - CLKMGR_BYPASS_PERPLLSRC_SET(
135   - CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1) |
136   - CLKMGR_BYPASS_SDRPLLSRC_SET(
137   - CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1) |
138   - CLKMGR_BYPASS_PERPLL_SET(CLKMGR_BYPASS_ENABLE) |
139   - CLKMGR_BYPASS_SDRPLL_SET(CLKMGR_BYPASS_ENABLE) |
140   - CLKMGR_BYPASS_MAINPLL_SET(CLKMGR_BYPASS_ENABLE));
  114 + cm_write_bypass(CLKMGR_BYPASS_PERPLL | CLKMGR_BYPASS_SDRPLL |
  115 + CLKMGR_BYPASS_MAINPLL);
141 116  
142 117 /*
143 118 * Put all plls VCO registers back to reset value.
144 119  
145 120  
... ... @@ -172,19 +147,14 @@
172 147 * We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN
173 148 * with numerator and denominator.
174 149 */
175   - writel(cfg->main_vco_base | CLEAR_BGP_EN_PWRDN |
176   - CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK,
177   - &clock_manager_base->main_pll.vco);
  150 + writel(cfg->main_vco_base | CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK,
  151 + &clock_manager_base->main_pll.vco);
178 152  
179   - writel(cfg->peri_vco_base | CLEAR_BGP_EN_PWRDN |
180   - CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK,
181   - &clock_manager_base->per_pll.vco);
  153 + writel(cfg->peri_vco_base | CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK,
  154 + &clock_manager_base->per_pll.vco);
182 155  
183   - writel(CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(0) |
184   - CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
185   - cfg->sdram_vco_base | CLEAR_BGP_EN_PWRDN |
186   - CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
187   - &clock_manager_base->sdr_pll.vco);
  156 + writel(cfg->sdram_vco_base | CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
  157 + &clock_manager_base->sdr_pll.vco);
188 158  
189 159 /*
190 160 * Time starts here
191 161  
192 162  
... ... @@ -234,18 +204,16 @@
234 204  
235 205 /* Enable vco */
236 206 /* main pll vco */
237   - writel(cfg->main_vco_base | VCO_EN_BASE,
  207 + writel(cfg->main_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
238 208 &clock_manager_base->main_pll.vco);
239 209  
240 210 /* periferal pll */
241   - writel(cfg->peri_vco_base | VCO_EN_BASE,
  211 + writel(cfg->peri_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
242 212 &clock_manager_base->per_pll.vco);
243 213  
244 214 /* sdram pll vco */
245   - writel(CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(0) |
246   - CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
247   - cfg->sdram_vco_base | VCO_EN_BASE,
248   - &clock_manager_base->sdr_pll.vco);
  215 + writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
  216 + &clock_manager_base->sdr_pll.vco);
249 217  
250 218 /* L3 MP and L3 SP */
251 219 writel(cfg->maindiv, &clock_manager_base->main_pll.maindiv);
... ... @@ -296,8 +264,8 @@
296 264 &clock_manager_base->per_pll.vco);
297 265  
298 266 /* assert sdram outresetall */
299   - writel(cfg->sdram_vco_base | VCO_EN_BASE|
300   - CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(1),
  267 + writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN|
  268 + CLKMGR_SDRPLLGRP_VCO_OUTRESETALL,
301 269 &clock_manager_base->sdr_pll.vco);
302 270  
303 271 /* deassert main outresetall */
... ... @@ -309,9 +277,8 @@
309 277 &clock_manager_base->per_pll.vco);
310 278  
311 279 /* deassert sdram outresetall */
312   - writel(CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
313   - cfg->sdram_vco_base | VCO_EN_BASE,
314   - &clock_manager_base->sdr_pll.vco);
  280 + writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
  281 + &clock_manager_base->sdr_pll.vco);
315 282  
316 283 /*
317 284 * now that we've toggled outreset all, all the clocks
318 285  
... ... @@ -335,18 +302,10 @@
335 302 CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK);
336 303  
337 304 /* Take all three PLLs out of bypass when safe mode is cleared. */
338   - cm_write_bypass(
339   - CLKMGR_BYPASS_PERPLLSRC_SET(
340   - CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1) |
341   - CLKMGR_BYPASS_SDRPLLSRC_SET(
342   - CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1) |
343   - CLKMGR_BYPASS_PERPLL_SET(CLKMGR_BYPASS_DISABLE) |
344   - CLKMGR_BYPASS_SDRPLL_SET(CLKMGR_BYPASS_DISABLE) |
345   - CLKMGR_BYPASS_MAINPLL_SET(CLKMGR_BYPASS_DISABLE));
  305 + cm_write_bypass(0);
346 306  
347 307 /* clear safe mode */
348   - cm_write_ctrl(readl(&clock_manager_base->ctrl) |
349   - CLKMGR_CTRL_SAFEMODE_SET(CLKMGR_CTRL_SAFEMODE_MASK));
  308 + cm_write_ctrl(readl(&clock_manager_base->ctrl) | CLKMGR_CTRL_SAFEMODE);
350 309  
351 310 /*
352 311 * now that safe mode is clear with clocks gated
... ... @@ -367,9 +326,11 @@
367 326  
368 327 /* get the main VCO clock */
369 328 reg = readl(&clock_manager_base->main_pll.vco);
370   - clock = CONFIG_HPS_CLK_OSC1_HZ /
371   - (CLKMGR_MAINPLLGRP_VCO_DENOM_GET(reg) + 1);
372   - clock *= (CLKMGR_MAINPLLGRP_VCO_NUMER_GET(reg) + 1);
  329 + clock = CONFIG_HPS_CLK_OSC1_HZ;
  330 + clock /= ((reg & CLKMGR_MAINPLLGRP_VCO_DENOM_MASK) >>
  331 + CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) + 1;
  332 + clock *= ((reg & CLKMGR_MAINPLLGRP_VCO_NUMER_MASK) >>
  333 + CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET) + 1;
373 334  
374 335 return clock;
375 336 }
... ... @@ -380,7 +341,8 @@
380 341  
381 342 /* identify PER PLL clock source */
382 343 reg = readl(&clock_manager_base->per_pll.vco);
383   - reg = CLKMGR_PERPLLGRP_VCO_SSRC_GET(reg);
  344 + reg = (reg & CLKMGR_PERPLLGRP_VCO_SSRC_MASK) >>
  345 + CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET;
384 346 if (reg == CLKMGR_VCO_SSRC_EOSC1)
385 347 clock = CONFIG_HPS_CLK_OSC1_HZ;
386 348 else if (reg == CLKMGR_VCO_SSRC_EOSC2)
... ... @@ -390,8 +352,10 @@
390 352  
391 353 /* get the PER VCO clock */
392 354 reg = readl(&clock_manager_base->per_pll.vco);
393   - clock /= (CLKMGR_PERPLLGRP_VCO_DENOM_GET(reg) + 1);
394   - clock *= (CLKMGR_PERPLLGRP_VCO_NUMER_GET(reg) + 1);
  355 + clock /= ((reg & CLKMGR_PERPLLGRP_VCO_DENOM_MASK) >>
  356 + CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) + 1;
  357 + clock *= ((reg & CLKMGR_PERPLLGRP_VCO_NUMER_MASK) >>
  358 + CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET) + 1;
395 359  
396 360 return clock;
397 361 }
... ... @@ -416,7 +380,8 @@
416 380  
417 381 /* identify SDRAM PLL clock source */
418 382 reg = readl(&clock_manager_base->sdr_pll.vco);
419   - reg = CLKMGR_SDRPLLGRP_VCO_SSRC_GET(reg);
  383 + reg = (reg & CLKMGR_SDRPLLGRP_VCO_SSRC_MASK) >>
  384 + CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET;
420 385 if (reg == CLKMGR_VCO_SSRC_EOSC1)
421 386 clock = CONFIG_HPS_CLK_OSC1_HZ;
422 387 else if (reg == CLKMGR_VCO_SSRC_EOSC2)
423 388  
... ... @@ -426,12 +391,15 @@
426 391  
427 392 /* get the SDRAM VCO clock */
428 393 reg = readl(&clock_manager_base->sdr_pll.vco);
429   - clock /= (CLKMGR_SDRPLLGRP_VCO_DENOM_GET(reg) + 1);
430   - clock *= (CLKMGR_SDRPLLGRP_VCO_NUMER_GET(reg) + 1);
  394 + clock /= ((reg & CLKMGR_SDRPLLGRP_VCO_DENOM_MASK) >>
  395 + CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) + 1;
  396 + clock *= ((reg & CLKMGR_SDRPLLGRP_VCO_NUMER_MASK) >>
  397 + CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) + 1;
431 398  
432 399 /* get the SDRAM (DDR_DQS) clock */
433 400 reg = readl(&clock_manager_base->sdr_pll.ddrdqsclk);
434   - reg = CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_GET(reg);
  401 + reg = (reg & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK) >>
  402 + CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET;
435 403 clock /= (reg + 1);
436 404  
437 405 return clock;
... ... @@ -443,7 +411,8 @@
443 411  
444 412 /* identify the source of L4 SP clock */
445 413 reg = readl(&clock_manager_base->main_pll.l4src);
446   - reg = CLKMGR_MAINPLLGRP_L4SRC_L4SP_GET(reg);
  414 + reg = (reg & CLKMGR_MAINPLLGRP_L4SRC_L4SP) >>
  415 + CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET;
447 416  
448 417 if (reg == CLKMGR_L4_SP_CLK_SRC_MAINPLL) {
449 418 clock = cm_get_main_vco_clk_hz();
... ... @@ -463,7 +432,8 @@
463 432  
464 433 /* get the L4 SP clock which supplied to UART */
465 434 reg = readl(&clock_manager_base->main_pll.maindiv);
466   - reg = CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_GET(reg);
  435 + reg = (reg & CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK) >>
  436 + CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET;
467 437 clock = clock / (1 << reg);
468 438  
469 439 return clock;
... ... @@ -475,7 +445,8 @@
475 445  
476 446 /* identify the source of MMC clock */
477 447 reg = readl(&clock_manager_base->per_pll.src);
478   - reg = CLKMGR_PERPLLGRP_SRC_SDMMC_GET(reg);
  448 + reg = (reg & CLKMGR_PERPLLGRP_SRC_SDMMC_MASK) >>
  449 + CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET;
479 450  
480 451 if (reg == CLKMGR_SDMMC_CLK_SRC_F2S) {
481 452 clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
... ... @@ -504,7 +475,8 @@
504 475  
505 476 /* identify the source of QSPI clock */
506 477 reg = readl(&clock_manager_base->per_pll.src);
507   - reg = CLKMGR_PERPLLGRP_SRC_QSPI_GET(reg);
  478 + reg = (reg & CLKMGR_PERPLLGRP_SRC_QSPI_MASK) >>
  479 + CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET;
508 480  
509 481 if (reg == CLKMGR_QSPI_CLK_SRC_F2S) {
510 482 clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
arch/arm/cpu/armv7/socfpga/spl.c
Diff comments   View file @ 44428ab
... ... @@ -19,6 +19,31 @@
19 19  
20 20 DECLARE_GLOBAL_DATA_PTR;
21 21  
  22 +#define MAIN_VCO_BASE ( \
  23 + (CONFIG_HPS_MAINPLLGRP_VCO_DENOM << \
  24 + CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) | \
  25 + (CONFIG_HPS_MAINPLLGRP_VCO_NUMER << \
  26 + CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET) \
  27 + )
  28 +
  29 +#define PERI_VCO_BASE ( \
  30 + (CONFIG_HPS_PERPLLGRP_VCO_PSRC << \
  31 + CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET) | \
  32 + (CONFIG_HPS_PERPLLGRP_VCO_DENOM << \
  33 + CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) | \
  34 + (CONFIG_HPS_PERPLLGRP_VCO_NUMER << \
  35 + CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET) \
  36 + )
  37 +
  38 +#define SDR_VCO_BASE ( \
  39 + (CONFIG_HPS_SDRPLLGRP_VCO_SSRC << \
  40 + CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET) | \
  41 + (CONFIG_HPS_SDRPLLGRP_VCO_DENOM << \
  42 + CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) | \
  43 + (CONFIG_HPS_SDRPLLGRP_VCO_NUMER << \
  44 + CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) \
  45 + )
  46 +
22 47 u32 spl_boot_device(void)
23 48 {
24 49 return BOOT_DEVICE_RAM;
25 50  
26 51  
... ... @@ -33,86 +58,87 @@
33 58 cm_config_t cm_default_cfg = {
34 59 /* main group */
35 60 MAIN_VCO_BASE,
36   - CLKMGR_MAINPLLGRP_MPUCLK_CNT_SET(
37   - CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT),
38   - CLKMGR_MAINPLLGRP_MAINCLK_CNT_SET(
39   - CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT),
40   - CLKMGR_MAINPLLGRP_DBGATCLK_CNT_SET(
41   - CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT),
42   - CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_SET(
43   - CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT),
44   - CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(
45   - CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT),
46   - CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_SET(
47   - CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT),
48   - CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_SET(
49   - CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK) |
50   - CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_SET(
51   - CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK) |
52   - CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_SET(
53   - CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK) |
54   - CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET(
55   - CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK),
56   - CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_SET(
57   - CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK) |
58   - CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_SET(
59   - CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK),
60   - CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_SET(
61   - CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK),
62   - CLKMGR_MAINPLLGRP_L4SRC_L4MP_SET(
63   - CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP) |
64   - CLKMGR_MAINPLLGRP_L4SRC_L4SP_SET(
65   - CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP),
  61 + (CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT <<
  62 + CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET),
  63 + (CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT <<
  64 + CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET),
  65 + (CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT <<
  66 + CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET),
  67 + (CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT <<
  68 + CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET),
  69 + (CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT <<
  70 + CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
  71 + (CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT <<
  72 + CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET),
  73 + (CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK <<
  74 + CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET) |
  75 + (CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK <<
  76 + CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET) |
  77 + (CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK <<
  78 + CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET) |
  79 + (CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK <<
  80 + CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET),
  81 + (CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK <<
  82 + CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET) |
  83 + (CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK <<
  84 + CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET),
  85 + (CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK <<
  86 + CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET),
  87 + (CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP <<
  88 + CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET) |
  89 + (CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP <<
  90 + CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET),
66 91  
67 92 /* peripheral group */
68 93 PERI_VCO_BASE,
69   - CLKMGR_PERPLLGRP_EMAC0CLK_CNT_SET(
70   - CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT),
71   - CLKMGR_PERPLLGRP_EMAC1CLK_CNT_SET(
72   - CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT),
73   - CLKMGR_PERPLLGRP_PERQSPICLK_CNT_SET(
74   - CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT),
75   - CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(
76   - CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT),
77   - CLKMGR_PERPLLGRP_PERBASECLK_CNT_SET(
78   - CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT),
79   - CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_SET(
80   - CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT),
81   - CLKMGR_PERPLLGRP_DIV_USBCLK_SET(
82   - CONFIG_HPS_PERPLLGRP_DIV_USBCLK) |
83   - CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(
84   - CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK) |
85   - CLKMGR_PERPLLGRP_DIV_CAN0CLK_SET(
86   - CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK) |
87   - CLKMGR_PERPLLGRP_DIV_CAN1CLK_SET(
88   - CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK),
89   - CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_SET(
90   - CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK),
91   - CLKMGR_PERPLLGRP_SRC_QSPI_SET(
92   - CONFIG_HPS_PERPLLGRP_SRC_QSPI) |
93   - CLKMGR_PERPLLGRP_SRC_NAND_SET(
94   - CONFIG_HPS_PERPLLGRP_SRC_NAND) |
95   - CLKMGR_PERPLLGRP_SRC_SDMMC_SET(
96   - CONFIG_HPS_PERPLLGRP_SRC_SDMMC),
  94 + (CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT <<
  95 + CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET),
  96 + (CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT <<
  97 + CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET),
  98 + (CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT <<
  99 + CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET),
  100 + (CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT <<
  101 + CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
  102 + (CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT <<
  103 + CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET),
  104 + (CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT <<
  105 + CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET),
  106 + (CONFIG_HPS_PERPLLGRP_DIV_USBCLK <<
  107 + CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET) |
  108 + (CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK <<
  109 + CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET) |
  110 + (CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK <<
  111 + CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET) |
  112 + (CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK <<
  113 + CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET),
  114 + (CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK <<
  115 + CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET),
  116 + (CONFIG_HPS_PERPLLGRP_SRC_QSPI <<
  117 + CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET) |
  118 + (CONFIG_HPS_PERPLLGRP_SRC_NAND <<
  119 + CLKMGR_PERPLLGRP_SRC_NAND_OFFSET) |
  120 + (CONFIG_HPS_PERPLLGRP_SRC_SDMMC <<
  121 + CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET),
97 122  
98 123 /* sdram pll group */
99 124 SDR_VCO_BASE,
100   - CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_SET(
101   - CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE) |
102   - CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_SET(
103   - CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT),
104   - CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_SET(
105   - CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE) |
106   - CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_SET(
107   - CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT),
108   - CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_SET(
109   - CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE) |
110   - CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_SET(
111   - CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT),
112   - CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_SET(
113   - CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE) |
114   - CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_SET(
115   - CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT),
  125 + (CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE <<
  126 + CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET) |
  127 + (CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT <<
  128 + CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET),
  129 + (CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE <<
  130 + CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET) |
  131 + (CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT <<
  132 + CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET),
  133 + (CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE <<
  134 + CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET) |
  135 + (CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT <<
  136 + CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET),
  137 + (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE <<
  138 + CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET) |
  139 + (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT <<
  140 + CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET),
  141 +
116 142 };
117 143  
118 144 debug("Freezing all I/O banks\n");
arch/arm/include/asm/arch-socfpga/clock_manager.h
Diff comments   View file @ 44428ab
... ... @@ -118,166 +118,188 @@
118 118 u32 _pad_0xe8_0x200[70];
119 119 };
120 120  
121   -#define CLKMGR_CTRL_SAFEMODE_MASK 0x00000001
122   -#define CLKMGR_CTRL_SAFEMODE_SET(x) (((x) << 0) & 0x00000001)
  121 +#define CLKMGR_CTRL_SAFEMODE (1 << 0)
  122 +#define CLKMGR_CTRL_SAFEMODE_OFFSET 0
123 123  
124   -#define CLKMGR_BYPASS_MAINPLL_SET(x) (((x) << 0) & 0x00000001)
125   -#define CLKMGR_BYPASS_PERPLLSRC_SET(x) (((x) << 4) & 0x00000010)
126   -#define CLKMGR_BYPASS_PERPLL_SET(x) (((x) << 3) & 0x00000008)
127   -#define CLKMGR_BYPASS_SDRPLLSRC_SET(x) (((x) << 2) & 0x00000004)
128   -#define CLKMGR_BYPASS_SDRPLL_SET(x) (((x) << 1) & 0x00000002)
  124 +#define CLKMGR_BYPASS_PERPLLSRC (1 << 4)
  125 +#define CLKMGR_BYPASS_PERPLLSRC_OFFSET 4
  126 +#define CLKMGR_BYPASS_PERPLL (1 << 3)
  127 +#define CLKMGR_BYPASS_PERPLL_OFFSET 3
  128 +#define CLKMGR_BYPASS_SDRPLLSRC (1 << 2)
  129 +#define CLKMGR_BYPASS_SDRPLLSRC_OFFSET 2
  130 +#define CLKMGR_BYPASS_SDRPLL (1 << 1)
  131 +#define CLKMGR_BYPASS_SDRPLL_OFFSET 1
  132 +#define CLKMGR_BYPASS_MAINPLL (1 << 0)
  133 +#define CLKMGR_BYPASS_MAINPLL_OFFSET 0
129 134  
130   -#define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000040
131   -#define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000080
132   -#define CLKMGR_INTER_SDRPLLLOCKED_MASK 0x00000100
  135 +#define CLKMGR_INTER_SDRPLLLOCKED_MASK 0x00000100
  136 +#define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000080
  137 +#define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000040
133 138  
  139 +#define CLKMGR_STAT_BUSY (1 << 0)
  140 +
134 141 /* Main PLL */
135   -#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(x) (((x) << 0) & 0x00000001)
136   -#define CLKMGR_MAINPLLGRP_VCO_DENOM_GET(x) (((x) & 0x003f0000) >> 16)
137   -#define CLKMGR_MAINPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000)
138   -#define CLKMGR_MAINPLLGRP_VCO_EN_SET(x) (((x) << 1) & 0x00000002)
139   -#define CLKMGR_MAINPLLGRP_VCO_NUMER_GET(x) (((x) & 0x0000fff8) >> 3)
140   -#define CLKMGR_MAINPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8)
141   -#define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
142   -#define CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(x) (((x) << 2) & 0x00000004)
143   -#define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
144   -#define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE 0x8001000d
  142 +#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN (1 << 0)
  143 +#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_OFFSET 0
  144 +#define CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET 16
  145 +#define CLKMGR_MAINPLLGRP_VCO_DENOM_MASK 0x003f0000
  146 +#define CLKMGR_MAINPLLGRP_VCO_EN (1 << 1)
  147 +#define CLKMGR_MAINPLLGRP_VCO_EN_OFFSET 1
  148 +#define CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET 3
  149 +#define CLKMGR_MAINPLLGRP_VCO_NUMER_MASK 0x0000fff8
  150 +#define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
  151 +#define CLKMGR_MAINPLLGRP_VCO_PWRDN (1 << 2)
  152 +#define CLKMGR_MAINPLLGRP_VCO_PWRDN_OFFSET 2
  153 +#define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
  154 +#define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE 0x8001000d
145 155  
146   -#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
  156 +#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET 0
  157 +#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_MASK 0x000001ff
147 158  
148   -#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
  159 +#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET 0
  160 +#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_MASK 0x000001ff
149 161  
150   -#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
  162 +#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET 0
  163 +#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_MASK 0x000001ff
151 164  
152   -#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
  165 +#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET 0
  166 +#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_MASK 0x000001ff
153 167  
154   -#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
  168 +#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_OFFSET 0
  169 +#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_MASK 0x000001ff
155 170  
156   -#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
  171 +#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET 0
  172 +#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_MASK 0x000001ff
157 173  
158   -#define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK 0x00000010
159   -#define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK 0x00000020
160   -#define CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK 0x00000080
161   -#define CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK 0x00000040
162   -#define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK 0x00000004
163   -#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK 0x00000200
  174 +#define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK 0x00000010
  175 +#define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK 0x00000020
  176 +#define CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK 0x00000080
  177 +#define CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK 0x00000040
  178 +#define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK 0x00000004
  179 +#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK 0x00000200
164 180  
165   -#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_SET(x) (((x) << 0) & 0x00000003)
166   -#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_SET(x) (((x) << 2) & 0x0000000c)
167   -#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_SET(x) (((x) << 4) & 0x00000070)
168   -#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_GET(x) (((x) & 0x00000380) >> 7)
169   -#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET(x) (((x) << 7) & 0x00000380)
  181 +#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET 0
  182 +#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_MASK 0x00000003
  183 +#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET 2
  184 +#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_MASK 0x0000000c
  185 +#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET 4
  186 +#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_MASK 0x00000070
  187 +#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET 7
  188 +#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK 0x00000380
170 189  
171   -#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_SET(x) (((x) << 0) & 0x00000003)
172   -#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_SET(x) (((x) << 2) & 0x0000000c)
  190 +#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET 0
  191 +#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_MASK 0x00000003
  192 +#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET 2
  193 +#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_MASK 0x0000000c
173 194  
174   -#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_SET(x) (((x) << 0) & 0x00000007)
  195 +#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET 0
  196 +#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_MASK 0x00000007
175 197  
176   -#define CLKMGR_MAINPLLGRP_L4SRC_L4MP_SET(x) (((x) << 0) & 0x00000001)
177   -#define CLKMGR_MAINPLLGRP_L4SRC_L4SP_GET(x) (((x) & 0x00000002) >> 1)
178   -#define CLKMGR_MAINPLLGRP_L4SRC_L4SP_SET(x) (((x) << 1) & 0x00000002)
179   -#define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE 0x00000000
180   -#define CLKMGR_L4_SP_CLK_SRC_MAINPLL 0x0
181   -#define CLKMGR_L4_SP_CLK_SRC_PERPLL 0x1
  198 +#define CLKMGR_MAINPLLGRP_L4SRC_L4MP (1 << 0)
  199 +#define CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET 0
  200 +#define CLKMGR_MAINPLLGRP_L4SRC_L4SP (1 << 1)
  201 +#define CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET 1
  202 +#define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE 0x00000000
  203 +#define CLKMGR_L4_SP_CLK_SRC_MAINPLL 0x0
  204 +#define CLKMGR_L4_SP_CLK_SRC_PERPLL 0x1
182 205  
183 206 /* Per PLL */
184   -#define CLKMGR_PERPLLGRP_VCO_DENOM_GET(x) (((x) & 0x003f0000) >> 16)
185   -#define CLKMGR_PERPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000)
186   -#define CLKMGR_PERPLLGRP_VCO_NUMER_GET(x) (((x) & 0x0000fff8) >> 3)
187   -#define CLKMGR_PERPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8)
188   -#define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
189   -#define CLKMGR_PERPLLGRP_VCO_PSRC_SET(x) (((x) << 22) & 0x00c00000)
190   -#define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
191   -#define CLKMGR_PERPLLGRP_VCO_RESET_VALUE 0x8001000d
192   -#define CLKMGR_PERPLLGRP_VCO_SSRC_GET(x) (((x) & 0x00c00000) >> 22)
193   -#define CLKMGR_VCO_SSRC_EOSC1 0x0
194   -#define CLKMGR_VCO_SSRC_EOSC2 0x1
195   -#define CLKMGR_VCO_SSRC_F2S 0x2
  207 +#define CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET 16
  208 +#define CLKMGR_PERPLLGRP_VCO_DENOM_MASK 0x003f0000
  209 +#define CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET 3
  210 +#define CLKMGR_PERPLLGRP_VCO_NUMER_MASK 0x0000fff8
  211 +#define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
  212 +#define CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET 22
  213 +#define CLKMGR_PERPLLGRP_VCO_PSRC_MASK 0x00c00000
  214 +#define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
  215 +#define CLKMGR_PERPLLGRP_VCO_RESET_VALUE 0x8001000d
  216 +#define CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET 22
  217 +#define CLKMGR_PERPLLGRP_VCO_SSRC_MASK 0x00c00000
196 218  
197   -#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
  219 +#define CLKMGR_VCO_SSRC_EOSC1 0x0
  220 +#define CLKMGR_VCO_SSRC_EOSC2 0x1
  221 +#define CLKMGR_VCO_SSRC_F2S 0x2
198 222  
199   -#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
  223 +#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET 0
  224 +#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_MASK 0x000001ff
200 225  
201   -#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
  226 +#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET 0
  227 +#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_MASK 0x000001ff
202 228  
203   -#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
  229 +#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET 0
  230 +#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_MASK 0x000001ff
204 231  
205   -#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
  232 +#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET 0
  233 +#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_MASK 0x000001ff
206 234  
207   -#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
  235 +#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET 0
  236 +#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_MASK 0x000001ff
208 237  
209   -#define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK 0x00000400
210   -#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK 0x00000100
  238 +#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET 0
  239 +#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_MASK 0x000001ff
211 240  
212   -#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_SET(x) (((x) << 6) & 0x000001c0)
213   -#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_SET(x) (((x) << 9) & 0x00000e00)
214   -#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(x) (((x) << 3) & 0x00000038)
215   -#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(x) (((x) << 3) & 0x00000038)
216   -#define CLKMGR_PERPLLGRP_DIV_USBCLK_SET(x) (((x) << 0) & 0x00000007)
  241 +#define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK 0x00000400
  242 +#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK 0x00000100
217 243  
218   -#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_SET(x) (((x) << 0) & 0x00ffffff)
  244 +#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET 6
  245 +#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_MASK 0x000001c0
  246 +#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET 9
  247 +#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_MASK 0x00000e00
  248 +#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET 3
  249 +#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET 3
  250 +#define CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET 0
  251 +#define CLKMGR_PERPLLGRP_DIV_USBCLK_MASK 0x00000007
219 252  
220   -#define CLKMGR_PERPLLGRP_SRC_NAND_SET(x) (((x) << 2) & 0x0000000c)
221   -#define CLKMGR_PERPLLGRP_SRC_QSPI_GET(x) (((x) & 0x00000030) >> 4)
222   -#define CLKMGR_PERPLLGRP_SRC_QSPI_SET(x) (((x) << 4) & 0x00000030)
223   -#define CLKMGR_PERPLLGRP_SRC_RESET_VALUE 0x00000015
224   -#define CLKMGR_PERPLLGRP_SRC_SDMMC_GET(x) (((x) & 0x00000003) >> 0)
225   -#define CLKMGR_PERPLLGRP_SRC_SDMMC_SET(x) (((x) << 0) & 0x00000003)
226   -#define CLKMGR_SDMMC_CLK_SRC_F2S 0x0
227   -#define CLKMGR_SDMMC_CLK_SRC_MAIN 0x1
228   -#define CLKMGR_SDMMC_CLK_SRC_PER 0x2
229   -#define CLKMGR_QSPI_CLK_SRC_F2S 0x0
230   -#define CLKMGR_QSPI_CLK_SRC_MAIN 0x1
231   -#define CLKMGR_QSPI_CLK_SRC_PER 0x2
  253 +#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET 0
  254 +#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_MASK 0x00ffffff
232 255  
  256 +#define CLKMGR_PERPLLGRP_SRC_NAND_OFFSET 2
  257 +#define CLKMGR_PERPLLGRP_SRC_NAND_MASK 0x0000000c
  258 +#define CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET 4
  259 +#define CLKMGR_PERPLLGRP_SRC_QSPI_MASK 0x00000030
  260 +#define CLKMGR_PERPLLGRP_SRC_RESET_VALUE 0x00000015
  261 +#define CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET 0
  262 +#define CLKMGR_PERPLLGRP_SRC_SDMMC_MASK 0x00000003
  263 +#define CLKMGR_SDMMC_CLK_SRC_F2S 0x0
  264 +#define CLKMGR_SDMMC_CLK_SRC_MAIN 0x1
  265 +#define CLKMGR_SDMMC_CLK_SRC_PER 0x2
  266 +#define CLKMGR_QSPI_CLK_SRC_F2S 0x0
  267 +#define CLKMGR_QSPI_CLK_SRC_MAIN 0x1
  268 +#define CLKMGR_QSPI_CLK_SRC_PER 0x2
  269 +
233 270 /* SDR PLL */
234   -#define CLKMGR_SDRPLLGRP_VCO_DENOM_GET(x) (((x) & 0x003f0000) >> 16)
235   -#define CLKMGR_SDRPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000)
236   -#define CLKMGR_SDRPLLGRP_VCO_NUMER_GET(x) (((x) & 0x0000fff8) >> 3)
237   -#define CLKMGR_SDRPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8)
238   -#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000)
239   -#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000)
240   -#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_MASK 0x7e000000
241   -#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(x) (((x) << 25) & 0x7e000000)
242   -#define CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
243   -#define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE 0x8001000d
244   -#define CLKMGR_SDRPLLGRP_VCO_SSRC_GET(x) (((x) & 0x00c00000) >> 22)
245   -#define CLKMGR_SDRPLLGRP_VCO_SSRC_SET(x) (((x) << 22) & 0x00c00000)
  271 +#define CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET 16
  272 +#define CLKMGR_SDRPLLGRP_VCO_DENOM_MASK 0x003f0000
  273 +#define CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET 3
  274 +#define CLKMGR_SDRPLLGRP_VCO_NUMER_MASK 0x0000fff8
  275 +#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL (1 << 24)
  276 +#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_OFFSET 24
  277 +#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_OFFSET 25
  278 +#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_MASK 0x7e000000
  279 +#define CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
  280 +#define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE 0x8001000d
  281 +#define CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET 22
  282 +#define CLKMGR_SDRPLLGRP_VCO_SSRC_MASK 0x00c00000
246 283  
247   -#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_GET(x) (((x) & 0x000001ff) >> 0)
248   -#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK 0x000001ff
249   -#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
250   -#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK 0x001ffe00
251   -#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
  284 +#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET 0
  285 +#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK 0x000001ff
  286 +#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET 9
  287 +#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK 0x00000e00
252 288  
253   -#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK 0x000001ff
254   -#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
255   -#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK 0x001ffe00
256   -#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
  289 +#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET 0
  290 +#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK 0x000001ff
  291 +#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET 9
  292 +#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK 0x00000e00
257 293  
258   -#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK 0x000001ff
259   -#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
260   -#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK 0x001ffe00
261   -#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
  294 +#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET 0
  295 +#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK 0x000001ff
  296 +#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET 9
  297 +#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK 0x00000e00
262 298  
263   -#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK 0x000001ff
264   -#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
265   -#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK 0x001ffe00
266   -#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
267   -
268   -#define MAIN_VCO_BASE \
269   - (CLKMGR_MAINPLLGRP_VCO_DENOM_SET(CONFIG_HPS_MAINPLLGRP_VCO_DENOM) | \
270   - CLKMGR_MAINPLLGRP_VCO_NUMER_SET(CONFIG_HPS_MAINPLLGRP_VCO_NUMER))
271   -
272   -#define PERI_VCO_BASE \
273   - (CLKMGR_PERPLLGRP_VCO_PSRC_SET(CONFIG_HPS_PERPLLGRP_VCO_PSRC) | \
274   - CLKMGR_PERPLLGRP_VCO_DENOM_SET(CONFIG_HPS_PERPLLGRP_VCO_DENOM) | \
275   - CLKMGR_PERPLLGRP_VCO_NUMER_SET(CONFIG_HPS_PERPLLGRP_VCO_NUMER))
276   -
277   -#define SDR_VCO_BASE \
278   - (CLKMGR_SDRPLLGRP_VCO_SSRC_SET(CONFIG_HPS_SDRPLLGRP_VCO_SSRC) | \
279   - CLKMGR_SDRPLLGRP_VCO_DENOM_SET(CONFIG_HPS_SDRPLLGRP_VCO_DENOM) | \
280   - CLKMGR_SDRPLLGRP_VCO_NUMER_SET(CONFIG_HPS_SDRPLLGRP_VCO_NUMER))
  299 +#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET 0
  300 +#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK 0x000001ff
  301 +#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET 9
  302 +#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK 0x00000e00
281 303  
282 304 #endif /* _CLOCK_MANAGER_H_ */