update/fix AcTux4 board

Signed-off-by: Michael Schwingen <michael@schwingen.org>

update/fix AcTux4 board
Signed-off-by: Michael Schwingen <michael@schwingen.org>
Michael Schwingen · Albert ARIBAUD
1 parent 8b5ab4c1b6
Showing 3 changed files with 86 additions and 60 deletions Side-by-side Diff
board/actux4/actux4.c
board/actux4/config.mk
include/configs/actux4.h
@@ -35,92 +35,107 @@
 #include <command.h>
 #include <malloc.h>
 #include <asm/arch/ixp425.h>
-
+#include <asm/io.h>
 #include <miiphy.h>
+#ifdef CONFIG_PCI
+#include <pci.h>
+#include <asm/arch/ixp425pci.h>
+#endif
  
 #include "actux4_hw.h"
  
 DECLARE_GLOBAL_DATA_PTR;
  
-int board_init (void)
+int board_early_init_f(void)
 {
+	writel(0xbd113c42, IXP425_EXP_CS1);
+	return 0;
+}
+
+int board_init(void)
+{
 	gd->bd->bi_arch_number = MACH_TYPE_ACTUX4;
  
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = 0x00000100;
  
-	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_nPWRON);
-	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_nPWRON);
+	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_nPWRON);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_nPWRON);
  
-	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_IORST);
-	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_IORST);
+	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_IORST);
  
 	/* led not populated on board*/
-	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_LED3);
-	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_LED3);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED3);
+	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_LED3);
  
 	/* middle LED */
-	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_LED2);
-	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_LED2);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED2);
+	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_LED2);
  
 	/* right LED */
 	/* weak pulldown = LED weak on */
-	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_LED1);
-	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_LED1);
+	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_LED1);
+	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_LED1);
  
 	/* Setup GPIO's for Interrupt inputs */
-	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_USBINTA);
-	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_USBINTB);
-	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_USBINTC);
-	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_RTCINT);
-	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_PCI_INTA);
-	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_PCI_INTB);
+	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_USBINTA);
+	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_USBINTB);
+	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_USBINTC);
+	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_RTCINT);
+	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTA);
+	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTB);
  
-	GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_USBINTA);
-	GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_USBINTB);
-	GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_USBINTC);
-	GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_RTCINT);
-	GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_PCI_INTA);
-	GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_PCI_INTB);
+	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_USBINTA);
+	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_USBINTB);
+	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_USBINTC);
+	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_RTCINT);
+	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTA);
+	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTB);
  
 	/* Setup GPIO's for 33MHz clock output */
-	*IXP425_GPIO_GPCLKR = 0x011001FF;
-	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_EXTBUS_CLK);
-	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_PCI_CLK);
+	writel(0x011001FF, IXP425_GPIO_GPCLKR);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK);
  
-	*IXP425_EXP_CS1 = 0xbd113c42;
+	udelay(10000);
+	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST);
+	udelay(10000);
+	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST);
+	udelay(10000);
+	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST);
  
-	udelay (10000);
-	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_IORST);
-	udelay (10000);
-	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_IORST);
-	udelay (10000);
-	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_IORST);
-
 	return 0;
 }
  
 /* Check Board Identity */
-int checkboard (void)
+int checkboard(void)
 {
-	puts ("Board: AcTux-4\n");
-	return (0);
+	puts("Board: AcTux-4\n");
+	return 0;
 }
  
-int dram_init (void)
+int dram_init(void)
 {
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+	gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20);
+	return 0;
+}
  
-	return (0);
+#ifdef CONFIG_PCI
+struct pci_controller hose;
+
+void pci_init_board(void)
+{
+	pci_ixp_init(&hose);
 }
+#endif
  
 /*
  * Hardcoded flash setup:
  * Flash 0 is a non-CFI SST 39VF020 flash, 8 bit flash / 8 bit bus.
  * Flash 1 is an Intel *16 flash using the CFI driver.
  */
-ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
 {
 	if (banknum == 0) {	/* non-CFI boot flash */
 		info->portwidth = 1;
-CONFIG_SYS_TEXT_BASE = 0x00e00000
-
-# include NPE ethernet driver
-BOARDLIBS = arch/arm/cpu/ixp/npe/libnpe.o
@@ -37,12 +37,11 @@
 #define CONFIG_BAUDRATE			115200
 #define CONFIG_BOOTDELAY		3
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+#define CONFIG_BOARD_EARLY_INIT_F	1
  
 /***************************************************************
  * U-boot generic defines start here.
  ***************************************************************/
-#undef CONFIG_USE_IRQ
-
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN			(CONFIG_ENV_SIZE + 128*1024)
  
@@ -54,6 +53,15 @@
  
 #define CONFIG_CMD_ELF
  
+#define CONFIG_PCI
+#ifdef CONFIG_PCI
+#define CONFIG_CMD_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_IXP_PCI
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_CMD_PCI_ENUM
+#endif
+
 #define CONFIG_BOOTCOMMAND		"run boot_flash"
 /* enable passing of ATAGs */
 #define CONFIG_CMDLINE_TAG		1
@@ -81,8 +89,9 @@
 #define CONFIG_SYS_MEMTEST_START		0x00400000
 #define CONFIG_SYS_MEMTEST_END			0x00800000
  
-/* spec says 66.666 MHz, but it appears to be 33 */
-#define CONFIG_SYS_HZ				3333333
+/* timer clock - 2* OSC_IN system clock */
+#define CONFIG_IXP425_TIMER_CLK                 66000000
+#define CONFIG_SYS_HZ				1000
  
 /* default load address */
 #define CONFIG_SYS_LOAD_ADDR			0x00010000
@@ -97,10 +106,6 @@
  * The stack sizes are set up in start.S using the settings below
  */
 #define CONFIG_STACKSIZE		(128*1024)	/* regular stack */
-#ifdef CONFIG_USE_IRQ
-# define CONFIG_STACKSIZE_IRQ		(4*1024)	/* IRQ stack */
-# define CONFIG_STACKSIZE_FIQ		(4*1024)	/* FIQ stack */
-#endif
  
 /* Expansion bus settings */
 #define CONFIG_SYS_EXP_CS0			0xbd113003
@@ -108,7 +113,7 @@
 /* SDRAM settings */
 #define CONFIG_NR_DRAM_BANKS		1
 #define PHYS_SDRAM_1			0x00000000
-#define CONFIG_SYS_DRAM_BASE			0x00000000
+#define CONFIG_SYS_SDRAM_BASE			0x00000000
  
 /* 32MB SDRAM */
 #define CONFIG_SYS_SDR_CONFIG			0x18
@@ -118,6 +123,7 @@
 #define CONFIG_SYS_DRAM_SIZE			0x02000000
  
 /* FLASH organization */
+#define CONFIG_SYS_TEXT_BASE		0x50000000
 #define CONFIG_SYS_MAX_FLASH_BANKS		2
 /* max # of sectors per chip */
 #define CONFIG_SYS_MAX_FLASH_SECT		70
@@ -128,6 +134,7 @@
 #define CONFIG_SYS_FLASH_BASE			PHYS_FLASH_1
 #define CONFIG_SYS_MONITOR_BASE		PHYS_FLASH_1
 #define CONFIG_SYS_MONITOR_LEN			(252 << 10)
+#define CONFIG_BOARD_SIZE_LIMIT			258048
  
 /* Use common CFI driver */
 #define CONFIG_SYS_FLASH_CFI
@@ -152,6 +159,7 @@
 #define	CONFIG_PHY_ADDR			0x1C
 /* MII PHY management */
 #define CONFIG_MII			1
+
 /* Number of ethernet rx buffers & descriptors */
 #define CONFIG_SYS_RX_ETH_BUFFER		16
  
  
  
@@ -180,19 +188,22 @@
 	"mtd=IXP4XX-Flash.0:252k(uboot),4k(uboot_env);"			\
 	"IXP4XX-Flash.1:128k(ucode),1280k(linux),-(root)\0"		\
 	"kerneladdr=51020000\0"						\
+	"kernelfile=actux4/uImage\0"					\
+	"rootfile=actux4/rootfs\0"					\
 	"rootaddr=51160000\0"						\
 	"loadaddr=10000\0"						\
 	"updateboot_ser=mw.b 10000 ff 40000;"				\
 	" loady ${loadaddr};"						\
 	" run eraseboot writeboot\0"					\
 	"updateboot_net=mw.b 10000 ff 40000;"				\
-	" tftp ${loadaddr} u-boot.bin;"					\
+	" tftp ${loadaddr} actux4/u-boot.bin;"					\
 	" run eraseboot writeboot\0"					\
 	"eraseboot=protect off 50000000 5003efff;"			\
 	" erase 50000000 +${filesize}\0"				\
 	"writeboot=cp.b 10000 50000000 ${filesize}\0"			\
-	"eraseenv=protect off 5003f000 5003ffff;"			\
-	" erase 5003f000 5003ffff\0"					\
+	"updateucode=loady;"						\
+	" era ${npe_ucode} +${filesize};"				\
+	" cp.b ${loadaddr} ${npe_ucode} ${filesize}\0"			\
 	"updateroot=tftp ${loadaddr} ${rootfile};"			\
 	" era ${rootaddr} +${filesize};"				\
 	" cp.b ${loadaddr} ${rootaddr} ${filesize}\0"			\
@@ -210,6 +221,10 @@
 	"boot_net=run netargs addtty addeth;"				\
 	" tftpboot ${loadaddr} ${kernelfile};"				\
 	" bootm\0"
+
+/* additions for new relocation code, must be added to all boards */
+#define CONFIG_SYS_INIT_SP_ADDR						\
+	(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
  
 #endif /* __CONFIG_H */
...	...	@@ -35,92 +35,107 @@
35	35	#include <command.h>
36	36	#include <malloc.h>
37	37	#include <asm/arch/ixp425.h>
38		-
	38	+#include <asm/io.h>
39	39	#include <miiphy.h>
	40	+#ifdef CONFIG_PCI
	41	+#include <pci.h>
	42	+#include <asm/arch/ixp425pci.h>
	43	+#endif
40	44
41	45	#include "actux4_hw.h"
42	46
43	47	DECLARE_GLOBAL_DATA_PTR;
44	48
45		-int board_init (void)
	49	+int board_early_init_f(void)
46	50	{
	51	+ writel(0xbd113c42, IXP425_EXP_CS1);
	52	+ return 0;
	53	+}
	54	+
	55	+int board_init(void)
	56	+{
47	57	gd->bd->bi_arch_number = MACH_TYPE_ACTUX4;
48	58
49	59	/* adress of boot parameters */
50	60	gd->bd->bi_boot_params = 0x00000100;
51	61
52		- GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_nPWRON);
53		- GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_nPWRON);
	62	+ GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_nPWRON);
	63	+ GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_nPWRON);
54	64
55		- GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_IORST);
56		- GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_IORST);
	65	+ GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST);
	66	+ GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_IORST);
57	67
58	68	/* led not populated on board*/
59		- GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_LED3);
60		- GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_LED3);
	69	+ GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED3);
	70	+ GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_LED3);
61	71
62	72	/* middle LED */
63		- GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_LED2);
64		- GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_LED2);
	73	+ GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED2);
	74	+ GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_LED2);
65	75
66	76	/* right LED */
67	77	/* weak pulldown = LED weak on */
68		- GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_LED1);
69		- GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_LED1);
	78	+ GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_LED1);
	79	+ GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_LED1);
70	80
71	81	/* Setup GPIO's for Interrupt inputs */
72		- GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_USBINTA);
73		- GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_USBINTB);
74		- GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_USBINTC);
75		- GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_RTCINT);
76		- GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_PCI_INTA);
77		- GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_PCI_INTB);
	82	+ GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_USBINTA);
	83	+ GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_USBINTB);
	84	+ GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_USBINTC);
	85	+ GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_RTCINT);
	86	+ GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTA);
	87	+ GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTB);
78	88
79		- GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_USBINTA);
80		- GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_USBINTB);
81		- GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_USBINTC);
82		- GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_RTCINT);
83		- GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_PCI_INTA);
84		- GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_PCI_INTB);
	89	+ GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_USBINTA);
	90	+ GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_USBINTB);
	91	+ GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_USBINTC);
	92	+ GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_RTCINT);
	93	+ GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTA);
	94	+ GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTB);
85	95
86	96	/* Setup GPIO's for 33MHz clock output */
87		- *IXP425_GPIO_GPCLKR = 0x011001FF;
88		- GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_EXTBUS_CLK);
89		- GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_PCI_CLK);
	97	+ writel(0x011001FF, IXP425_GPIO_GPCLKR);
	98	+ GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK);
	99	+ GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK);
90	100
91		- *IXP425_EXP_CS1 = 0xbd113c42;
	101	+ udelay(10000);
	102	+ GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST);
	103	+ udelay(10000);
	104	+ GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST);
	105	+ udelay(10000);
	106	+ GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST);
92	107
93		- udelay (10000);
94		- GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_IORST);
95		- udelay (10000);
96		- GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_IORST);
97		- udelay (10000);
98		- GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_IORST);
99		-
100	108	return 0;
101	109	}
102	110
103	111	/* Check Board Identity */
104		-int checkboard (void)
	112	+int checkboard(void)
105	113	{
106		- puts ("Board: AcTux-4\n");
107		- return (0);
	114	+ puts("Board: AcTux-4\n");
	115	+ return 0;
108	116	}
109	117
110		-int dram_init (void)
	118	+int dram_init(void)
111	119	{
112		- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
113		- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
	120	+ gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20);
	121	+ return 0;
	122	+}
114	123
115		- return (0);
	124	+#ifdef CONFIG_PCI
	125	+struct pci_controller hose;
	126	+
	127	+void pci_init_board(void)
	128	+{
	129	+ pci_ixp_init(&hose);
116	130	}
	131	+#endif
117	132
118	133	/*
119	134	* Hardcoded flash setup:
120	135	* Flash 0 is a non-CFI SST 39VF020 flash, 8 bit flash / 8 bit bus.
121	136	* Flash 1 is an Intel *16 flash using the CFI driver.
122	137	*/
123		-ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
	138	+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
124	139	{
125	140	if (banknum == 0) { /* non-CFI boot flash */
126	141	info->portwidth = 1;
1		-CONFIG_SYS_TEXT_BASE = 0x00e00000
2		-
3		-# include NPE ethernet driver
4		-BOARDLIBS = arch/arm/cpu/ixp/npe/libnpe.o
...	...	@@ -37,12 +37,11 @@
37	37	#define CONFIG_BAUDRATE 115200
38	38	#define CONFIG_BOOTDELAY 3
39	39	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
	40	+#define CONFIG_BOARD_EARLY_INIT_F 1
40	41
41	42	/***************************************************************
42	43	* U-boot generic defines start here.
43	44	***************************************************************/
44		-#undef CONFIG_USE_IRQ
45		-
46	45	/* Size of malloc() pool */
47	46	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
48	47
...	...	@@ -54,6 +53,15 @@
54	53
55	54	#define CONFIG_CMD_ELF
56	55
	56	+#define CONFIG_PCI
	57	+#ifdef CONFIG_PCI
	58	+#define CONFIG_CMD_PCI
	59	+#define CONFIG_PCI_PNP
	60	+#define CONFIG_IXP_PCI
	61	+#define CONFIG_PCI_SCAN_SHOW
	62	+#define CONFIG_CMD_PCI_ENUM
	63	+#endif
	64	+
57	65	#define CONFIG_BOOTCOMMAND "run boot_flash"
58	66	/* enable passing of ATAGs */
59	67	#define CONFIG_CMDLINE_TAG 1
...	...	@@ -81,8 +89,9 @@
81	89	#define CONFIG_SYS_MEMTEST_START 0x00400000
82	90	#define CONFIG_SYS_MEMTEST_END 0x00800000
83	91
84		-/* spec says 66.666 MHz, but it appears to be 33 */
85		-#define CONFIG_SYS_HZ 3333333
	92	+/* timer clock - 2* OSC_IN system clock */
	93	+#define CONFIG_IXP425_TIMER_CLK 66000000
	94	+#define CONFIG_SYS_HZ 1000
86	95
87	96	/* default load address */
88	97	#define CONFIG_SYS_LOAD_ADDR 0x00010000
...	...	@@ -97,10 +106,6 @@
97	106	* The stack sizes are set up in start.S using the settings below
98	107	*/
99	108	#define CONFIG_STACKSIZE (1281024) / regular stack */
100		-#ifdef CONFIG_USE_IRQ
101		-# define CONFIG_STACKSIZE_IRQ (41024) / IRQ stack */
102		-# define CONFIG_STACKSIZE_FIQ (41024) / FIQ stack */
103		-#endif
104	109
105	110	/* Expansion bus settings */
106	111	#define CONFIG_SYS_EXP_CS0 0xbd113003
...	...	@@ -108,7 +113,7 @@
108	113	/* SDRAM settings */
109	114	#define CONFIG_NR_DRAM_BANKS 1
110	115	#define PHYS_SDRAM_1 0x00000000
111		-#define CONFIG_SYS_DRAM_BASE 0x00000000
	116	+#define CONFIG_SYS_SDRAM_BASE 0x00000000
112	117
113	118	/* 32MB SDRAM */
114	119	#define CONFIG_SYS_SDR_CONFIG 0x18
...	...	@@ -118,6 +123,7 @@
118	123	#define CONFIG_SYS_DRAM_SIZE 0x02000000
119	124
120	125	/* FLASH organization */
	126	+#define CONFIG_SYS_TEXT_BASE 0x50000000
121	127	#define CONFIG_SYS_MAX_FLASH_BANKS 2
122	128	/* max # of sectors per chip */
123	129	#define CONFIG_SYS_MAX_FLASH_SECT 70
...	...	@@ -128,6 +134,7 @@
128	134	#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
129	135	#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
130	136	#define CONFIG_SYS_MONITOR_LEN (252 << 10)
	137	+#define CONFIG_BOARD_SIZE_LIMIT 258048
131	138
132	139	/* Use common CFI driver */
133	140	#define CONFIG_SYS_FLASH_CFI
...	...	@@ -152,6 +159,7 @@
152	159	#define CONFIG_PHY_ADDR 0x1C
153	160	/* MII PHY management */
154	161	#define CONFIG_MII 1
	162	+
155	163	/* Number of ethernet rx buffers & descriptors */
156	164	#define CONFIG_SYS_RX_ETH_BUFFER 16
157	165
158	166
159	167
...	...	@@ -180,19 +188,22 @@
180	188	"mtd=IXP4XX-Flash.0:252k(uboot),4k(uboot_env);" \
181	189	"IXP4XX-Flash.1:128k(ucode),1280k(linux),-(root)\0" \
182	190	"kerneladdr=51020000\0" \
	191	+ "kernelfile=actux4/uImage\0" \
	192	+ "rootfile=actux4/rootfs\0" \
183	193	"rootaddr=51160000\0" \
184	194	"loadaddr=10000\0" \
185	195	"updateboot_ser=mw.b 10000 ff 40000;" \
186	196	" loady ${loadaddr};" \
187	197	" run eraseboot writeboot\0" \
188	198	"updateboot_net=mw.b 10000 ff 40000;" \
189		- " tftp ${loadaddr} u-boot.bin;" \
	199	+ " tftp ${loadaddr} actux4/u-boot.bin;" \
190	200	" run eraseboot writeboot\0" \
191	201	"eraseboot=protect off 50000000 5003efff;" \
192	202	" erase 50000000 +${filesize}\0" \
193	203	"writeboot=cp.b 10000 50000000 ${filesize}\0" \
194		- "eraseenv=protect off 5003f000 5003ffff;" \
195		- " erase 5003f000 5003ffff\0" \
	204	+ "updateucode=loady;" \
	205	+ " era ${npe_ucode} +${filesize};" \
	206	+ " cp.b ${loadaddr} ${npe_ucode} ${filesize}\0" \
196	207	"updateroot=tftp ${loadaddr} ${rootfile};" \
197	208	" era ${rootaddr} +${filesize};" \
198	209	" cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \
...	...	@@ -210,6 +221,10 @@
210	221	"boot_net=run netargs addtty addeth;" \
211	222	" tftpboot ${loadaddr} ${kernelfile};" \
212	223	" bootm\0"
	224	+
	225	+/* additions for new relocation code, must be added to all boards */
	226	+#define CONFIG_SYS_INIT_SP_ADDR \
	227	+ (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
213	228
214	229	#endif /* __CONFIG_H */