ARM: OMAP5: Fix warm reset with USB cable connected

Warm reset on OMAP5 freezes when USB cable is connected. Fix requires PRM_RSTTIME.RSTTIME1 to be programmed with the time for which reset should be held low for the voltages and the oscillator to reach stable state. There are 3 parameters to be considered for calculating the time, which are mostly board and PMIC dependent. -1- Time taken by the Oscillator to shut + restart -2- PMIC OTP times -3- Voltage rail ramp times, which inturn depends on the PMIC slew rate and value of the voltage ramp needed. In order to keep the code in u-boot simple, have a way for boards to specify a pre computed time directly using the 'CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC' option. If boards fail to specify the time, use a default as specified by 'CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC' instead. Using the default value translates into some ~22ms and should work in all cases. However in order to avoid this large delay hiding other bugs, its recommended that all boards look at their respective data sheets and specify a pre computed and optimal value using 'CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC' In order to help future board additions to compute this config option value, add a README at doc/README.omap-reset-time which explains how to compute the value. Also update the toplevel README with the additional option and pointers to doc/README.omap-reset-time. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> [rnayak@ti.com: Updated changelog and added the README] Signed-off-by: Rajendra Nayak <rnayak@ti.com>

ARM: OMAP5: Fix warm reset with USB cable connected
Warm reset on OMAP5 freezes when USB cable is connected. Fix requires PRM_RSTTIME.RSTTIME1 to be programmed with the time for which reset should be held low for the voltages and the oscillator to reach stable state. There are 3 parameters to be considered for calculating the time, which are mostly board and PMIC dependent. -1- Time taken by the Oscillator to shut + restart -2- PMIC OTP times -3- Voltage rail ramp times, which inturn depends on the PMIC slew rate and value of the voltage ramp needed. In order to keep the code in u-boot simple, have a way for boards to specify a pre computed time directly using the 'CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC' option. If boards fail to specify the time, use a default as specified by 'CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC' instead. Using the default value translates into some ~22ms and should work in all cases. However in order to avoid this large delay hiding other bugs, its recommended that all boards look at their respective data sheets and specify a pre computed and optimal value using 'CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC' In order to help future board additions to compute this config option value, add a README at doc/README.omap-reset-time which explains how to compute the value. Also update the toplevel README with the additional option and pointers to doc/README.omap-reset-time. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> [rnayak@ti.com: Updated changelog and added the README] Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Lokesh Vutla · Tom Rini
1 parent 15191c91a2
Showing 11 changed files with 73 additions and 0 deletions Side-by-side Diff
README
arch/arm/cpu/armv7/omap-common/clocks-common.c
arch/arm/cpu/armv7/omap-common/reset.c
arch/arm/cpu/armv7/omap5/hwinit.c
arch/arm/cpu/armv7/omap5/prcm-regs.c
arch/arm/include/asm/arch-omap4/sys_proto.h
arch/arm/include/asm/arch-omap5/clocks.h
arch/arm/include/asm/arch-omap5/sys_proto.h
arch/arm/include/asm/omap_common.h
doc/README.omap-reset-time
include/configs/omap5_uevm.h
@@ -3323,6 +3323,10 @@
 	offset _bss_start_ofs from CONFIG_SYS_TEXT_BASE, rather than
 	directly. You should not need to touch this setting.
  
+- CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC (OMAP only)
+	This is set by OMAP boards for the max time that reset should
+	be asserted. See doc/README.omap-reset-time for details on how
+	the value can be calulated on a given board.
  
 The following definitions that deal with the placement and management
 of environment data (variable area); in general, we support the
@@ -716,6 +716,7 @@
 		setup_non_essential_dplls();
 		enable_non_essential_clocks();
 #endif
+		setup_warmreset_time();
 		break;
 	default:
 		break;
@@ -39,4 +39,8 @@
 {
 	return (readl(PRM_RSTST) & PRM_RSTST_WARM_RESET_MASK);
 }
+
+void __weak setup_warmreset_time(void)
+{
+}
@@ -363,4 +363,23 @@
 {
 	return readl((*prcm)->prm_rstst) & PRM_RSTST_WARM_RESET_MASK;
 }
+
+void setup_warmreset_time(void)
+{
+	u32 rst_time, rst_val;
+
+#ifndef CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC
+	rst_time = CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC;
+#else
+	rst_time = CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC;
+#endif
+	rst_time = usec_to_32k(rst_time) << RSTTIME1_SHIFT;
+
+	if (rst_time > RSTTIME1_MASK)
+		rst_time = RSTTIME1_MASK;
+
+	rst_val = readl((*prcm)->prm_rsttime) & ~RSTTIME1_MASK;
+	rst_val |= rst_time;
+	writel(rst_val, (*prcm)->prm_rsttime);
+}
@@ -729,6 +729,7 @@
 	.cm_wkupaon_io_srcomp_clkctrl = 0x4ae07998,
 	.prm_rstctrl = 0x4ae07c00,
 	.prm_rstst = 0x4ae07c04,
+	.prm_rsttime = 0x4ae07c08,
 	.prm_vc_val_bypass = 0x4ae07ca0,
 	.prm_vc_cfg_i2c_mode = 0x4ae07cb4,
 	.prm_vc_cfg_i2c_clk = 0x4ae07cb8,
@@ -952,6 +953,7 @@
 	.cm_wkupaon_scrm_clkctrl		= 0x4ae07890,
 	.prm_rstctrl				= 0x4ae07d00,
 	.prm_rstst				= 0x4ae07d04,
+	.prm_rsttime				= 0x4ae07d08,
 	.prm_vc_val_bypass			= 0x4ae07da0,
 	.prm_vc_cfg_i2c_mode			= 0x4ae07db4,
 	.prm_vc_cfg_i2c_clk			= 0x4ae07db8,
@@ -58,6 +58,7 @@
 int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data);
 u32 warm_reset(void);
 void force_emif_self_refresh(void);
+void setup_warmreset_time(void);
 /*
  * This is used to verify if the configuration header
  * was executed by Romcode prior to control of transfer
@@ -190,6 +190,10 @@
 #define OPTFCLKEN_SRCOMP_FCLK_SHIFT		8
 #define OPTFCLKEN_SRCOMP_FCLK_MASK		(1 << 8)
  
+/* PRM_RSTTIME */
+#define RSTTIME1_SHIFT				0
+#define RSTTIME1_MASK				(0x3ff << 0)
+
 /* Clock frequencies */
 #define OMAP_SYS_CLK_FREQ_38_4_MHZ	38400000
 #define OMAP_SYS_CLK_IND_38_4_MHZ	6
@@ -251,5 +255,11 @@
 #define DPLL_NO_LOCK	0
 #define DPLL_LOCK	1
  
+/*
+ * MAX value for PRM_RSTTIME[9:0]RSTTIME1 stored is 0x3ff.
+ * 0x3ff is in the no of FUNC_32K_CLK cycles. Converting cycles
+ * into microsec and passing the value.
+ */
+#define CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC	31219
 #endif /* _CLOCKS_OMAP5_H_ */
@@ -64,6 +64,7 @@
 void force_emif_self_refresh(void);
 void get_ioregs(const struct ctrl_ioregs **regs);
 void srcomp_enable(void);
+void setup_warmreset_time(void);
  
 /*
  * This is used to verify if the configuration header
@@ -122,5 +123,14 @@
 #endif
 }
  
+static inline u32 div_round_up(u32 num, u32 den)
+{
+	return (num + den - 1)/den;
+}
+
+static inline u32 usec_to_32k(u32 usec)
+{
+	return div_round_up(32768 * usec, 1000000);
+}
 #endif
@@ -316,6 +316,7 @@
 	u32 cm_wkupaon_io_srcomp_clkctrl;
 	u32 prm_rstctrl;
 	u32 prm_rstst;
+	u32 prm_rsttime;
 	u32 prm_vc_val_bypass;
 	u32 prm_vc_cfg_i2c_mode;
 	u32 prm_vc_cfg_i2c_clk;
+README on how reset time on OMAPs should be calculated
+
+CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC:
+Most OMAPs' provide a way to specify the time for
+which the reset should be held low while the voltages
+and Oscillator outputs stabilize.
+
+This time is mostly board and PMIC dependent. Hence the
+boards are expected to specify a pre-computed time
+using the above option, (the details on how to compute
+the value are given below) without which a default time
+as specified by CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC
+is used.
+
+The value for CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC
+can be computed using a summation of the below 3 parameters
+-1- Time taken by the Osciallator to stop and restart
+-2- PMIC OTP time
+-3- Voltage ramp time, which can be derived using the
+PMIC slew rate and value of voltage ramp needed.
@@ -54,5 +54,6 @@
  
 #define CONFIG_SYS_PROMPT		"OMAP5430 EVM # "
  
+#define CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC	16296
 #endif /* __CONFIG_OMAP5_EVM_H */
...	...	@@ -3323,6 +3323,10 @@
3323	3323	offset _bss_start_ofs from CONFIG_SYS_TEXT_BASE, rather than
3324	3324	directly. You should not need to touch this setting.
3325	3325
	3326	+- CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC (OMAP only)
	3327	+ This is set by OMAP boards for the max time that reset should
	3328	+ be asserted. See doc/README.omap-reset-time for details on how
	3329	+ the value can be calulated on a given board.
3326	3330
3327	3331	The following definitions that deal with the placement and management
3328	3332	of environment data (variable area); in general, we support the
...	...	@@ -716,6 +716,7 @@
716	716	setup_non_essential_dplls();
717	717	enable_non_essential_clocks();
718	718	#endif
	719	+ setup_warmreset_time();
719	720	break;
720	721	default:
721	722	break;
...	...	@@ -39,4 +39,8 @@
39	39	{
40	40	return (readl(PRM_RSTST) & PRM_RSTST_WARM_RESET_MASK);
41	41	}
	42	+
	43	+void __weak setup_warmreset_time(void)
	44	+{
	45	+}
...	...	@@ -363,4 +363,23 @@
363	363	{
364	364	return readl((*prcm)->prm_rstst) & PRM_RSTST_WARM_RESET_MASK;
365	365	}
	366	+
	367	+void setup_warmreset_time(void)
	368	+{
	369	+ u32 rst_time, rst_val;
	370	+
	371	+#ifndef CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC
	372	+ rst_time = CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC;
	373	+#else
	374	+ rst_time = CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC;
	375	+#endif
	376	+ rst_time = usec_to_32k(rst_time) << RSTTIME1_SHIFT;
	377	+
	378	+ if (rst_time > RSTTIME1_MASK)
	379	+ rst_time = RSTTIME1_MASK;
	380	+
	381	+ rst_val = readl((*prcm)->prm_rsttime) & ~RSTTIME1_MASK;
	382	+ rst_val \|= rst_time;
	383	+ writel(rst_val, (*prcm)->prm_rsttime);
	384	+}
...	...	@@ -729,6 +729,7 @@
729	729	.cm_wkupaon_io_srcomp_clkctrl = 0x4ae07998,
730	730	.prm_rstctrl = 0x4ae07c00,
731	731	.prm_rstst = 0x4ae07c04,
	732	+ .prm_rsttime = 0x4ae07c08,
732	733	.prm_vc_val_bypass = 0x4ae07ca0,
733	734	.prm_vc_cfg_i2c_mode = 0x4ae07cb4,
734	735	.prm_vc_cfg_i2c_clk = 0x4ae07cb8,
...	...	@@ -952,6 +953,7 @@
952	953	.cm_wkupaon_scrm_clkctrl = 0x4ae07890,
953	954	.prm_rstctrl = 0x4ae07d00,
954	955	.prm_rstst = 0x4ae07d04,
	956	+ .prm_rsttime = 0x4ae07d08,
955	957	.prm_vc_val_bypass = 0x4ae07da0,
956	958	.prm_vc_cfg_i2c_mode = 0x4ae07db4,
957	959	.prm_vc_cfg_i2c_clk = 0x4ae07db8,
...	...	@@ -58,6 +58,7 @@
58	58	int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data);
59	59	u32 warm_reset(void);
60	60	void force_emif_self_refresh(void);
	61	+void setup_warmreset_time(void);
61	62	/*
62	63	* This is used to verify if the configuration header
63	64	* was executed by Romcode prior to control of transfer
...	...	@@ -190,6 +190,10 @@
190	190	#define OPTFCLKEN_SRCOMP_FCLK_SHIFT 8
191	191	#define OPTFCLKEN_SRCOMP_FCLK_MASK (1 << 8)
192	192
	193	+/* PRM_RSTTIME */
	194	+#define RSTTIME1_SHIFT 0
	195	+#define RSTTIME1_MASK (0x3ff << 0)
	196	+
193	197	/* Clock frequencies */
194	198	#define OMAP_SYS_CLK_FREQ_38_4_MHZ 38400000
195	199	#define OMAP_SYS_CLK_IND_38_4_MHZ 6
...	...	@@ -251,5 +255,11 @@
251	255	#define DPLL_NO_LOCK 0
252	256	#define DPLL_LOCK 1
253	257
	258	+/*
	259	+ * MAX value for PRM_RSTTIME[9:0]RSTTIME1 stored is 0x3ff.
	260	+ * 0x3ff is in the no of FUNC_32K_CLK cycles. Converting cycles
	261	+ * into microsec and passing the value.
	262	+ */
	263	+#define CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC 31219
254	264	#endif /* _CLOCKS_OMAP5_H_ */
...	...	@@ -64,6 +64,7 @@
64	64	void force_emif_self_refresh(void);
65	65	void get_ioregs(const struct ctrl_ioregs **regs);
66	66	void srcomp_enable(void);
	67	+void setup_warmreset_time(void);
67	68
68	69	/*
69	70	* This is used to verify if the configuration header
...	...	@@ -122,5 +123,14 @@
122	123	#endif
123	124	}
124	125
	126	+static inline u32 div_round_up(u32 num, u32 den)
	127	+{
	128	+ return (num + den - 1)/den;
	129	+}
	130	+
	131	+static inline u32 usec_to_32k(u32 usec)
	132	+{
	133	+ return div_round_up(32768 * usec, 1000000);
	134	+}
125	135	#endif
...	...	@@ -316,6 +316,7 @@
316	316	u32 cm_wkupaon_io_srcomp_clkctrl;
317	317	u32 prm_rstctrl;
318	318	u32 prm_rstst;
	319	+ u32 prm_rsttime;
319	320	u32 prm_vc_val_bypass;
320	321	u32 prm_vc_cfg_i2c_mode;
321	322	u32 prm_vc_cfg_i2c_clk;
	1	+README on how reset time on OMAPs should be calculated
	2	+
	3	+CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC:
	4	+Most OMAPs' provide a way to specify the time for
	5	+which the reset should be held low while the voltages
	6	+and Oscillator outputs stabilize.
	7	+
	8	+This time is mostly board and PMIC dependent. Hence the
	9	+boards are expected to specify a pre-computed time
	10	+using the above option, (the details on how to compute
	11	+the value are given below) without which a default time
	12	+as specified by CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC
	13	+is used.
	14	+
	15	+The value for CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC
	16	+can be computed using a summation of the below 3 parameters
	17	+-1- Time taken by the Osciallator to stop and restart
	18	+-2- PMIC OTP time
	19	+-3- Voltage ramp time, which can be derived using the
	20	+PMIC slew rate and value of voltage ramp needed.