Commit 0dd78fb9430e57ccc8e63369c6082b1c730f8aeb
Exists in
master
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56 other branches
Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx
* 'master' of git://git.denx.de/u-boot-ppc4xx: ppc4xx: Change DDR2 CL from 4 to 5 for intip ppc4xx: Improve lm63 pwm on dlvision-10g ppc4xx: Do not stop booting on any keypress on intip
Showing 2 changed files Side-by-side Diff
include/configs/dlvision-10g.h
| ... | ... | @@ -34,7 +34,7 @@ |
| 34 | 34 | * Include common defines/options for all AMCC eval boards |
| 35 | 35 | */ |
| 36 | 36 | #define CONFIG_HOSTNAME dlvsion-10g |
| 37 | -#define CONFIG_IDENT_STRING " dlvision-10g 0.01" | |
| 37 | +#define CONFIG_IDENT_STRING " dlvision-10g 0.02" | |
| 38 | 38 | #include "amcc-common.h" |
| 39 | 39 | |
| 40 | 40 | #define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */ |
| ... | ... | @@ -117,8 +117,8 @@ |
| 117 | 117 | #define CONFIG_DTT_LM63 1 /* National LM63 */ |
| 118 | 118 | #define CONFIG_DTT_SENSORS { 0x4c, 0x4e } /* Sensor addresses */ |
| 119 | 119 | #define CONFIG_DTT_PWM_LOOKUPTABLE \ |
| 120 | - { { 40, 10 }, { 43, 13 }, { 46, 16 }, \ | |
| 121 | - { 50, 20 }, { 53, 27 }, { 56, 34 }, { 60, 40 } } | |
| 120 | + { { 46, 10 }, { 48, 14 }, { 50, 19 }, { 52, 23 },\ | |
| 121 | + { 54, 27 }, { 56, 31 }, { 58, 36 }, { 60, 40 } } | |
| 122 | 122 | #define CONFIG_DTT_TACH_LIMIT 0xa10 |
| 123 | 123 | |
| 124 | 124 | /* EBC peripherals */ |
include/configs/intip.h
| ... | ... | @@ -37,10 +37,10 @@ |
| 37 | 37 | #define CONFIG_460EX 1 /* Specific PPC460EX */ |
| 38 | 38 | #ifdef CONFIG_DEVCONCENTER |
| 39 | 39 | #define CONFIG_HOSTNAME devconcenter |
| 40 | -#define CONFIG_IDENT_STRING " devconcenter 0.02" | |
| 40 | +#define CONFIG_IDENT_STRING " devconcenter 0.05" | |
| 41 | 41 | #else |
| 42 | 42 | #define CONFIG_HOSTNAME intip |
| 43 | -#define CONFIG_IDENT_STRING " intip 0.02" | |
| 43 | +#define CONFIG_IDENT_STRING " intip 0.05" | |
| 44 | 44 | #endif |
| 45 | 45 | #define CONFIG_440 1 |
| 46 | 46 | #define CONFIG_4xx 1 /* ... PPC4xx family */ |
| ... | ... | @@ -63,6 +63,10 @@ |
| 63 | 63 | #define CONFIG_FIT |
| 64 | 64 | #define CFG_ALT_MEMTEST |
| 65 | 65 | |
| 66 | +#undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */ | |
| 67 | +#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */ | |
| 68 | +#define CONFIG_AUTOBOOT_STOP_STR " " | |
| 69 | + | |
| 66 | 70 | /* |
| 67 | 71 | * Base addresses -- Note these are effective addresses where the |
| 68 | 72 | * actual resources get mapped (not physical addresses) |
| 69 | 73 | |
| ... | ... | @@ -196,13 +200,13 @@ |
| 196 | 200 | #define CONFIG_SYS_SDRAM0_INITPLR2 0x81020000 |
| 197 | 201 | #define CONFIG_SYS_SDRAM0_INITPLR3 0x81030000 |
| 198 | 202 | #define CONFIG_SYS_SDRAM0_INITPLR4 0x81010002 |
| 199 | -#define CONFIG_SYS_SDRAM0_INITPLR5 0xE4000542 | |
| 203 | +#define CONFIG_SYS_SDRAM0_INITPLR5 0xE4000552 | |
| 200 | 204 | #define CONFIG_SYS_SDRAM0_INITPLR6 0x81900400 |
| 201 | 205 | #define CONFIG_SYS_SDRAM0_INITPLR7 0x8A880000 |
| 202 | 206 | #define CONFIG_SYS_SDRAM0_INITPLR8 0x8A880000 |
| 203 | 207 | #define CONFIG_SYS_SDRAM0_INITPLR9 0x8A880000 |
| 204 | 208 | #define CONFIG_SYS_SDRAM0_INITPLR10 0x8A880000 |
| 205 | -#define CONFIG_SYS_SDRAM0_INITPLR11 0x81000442 | |
| 209 | +#define CONFIG_SYS_SDRAM0_INITPLR11 0x81000452 | |
| 206 | 210 | #define CONFIG_SYS_SDRAM0_INITPLR12 0x81010382 |
| 207 | 211 | #define CONFIG_SYS_SDRAM0_INITPLR13 0x81010002 |
| 208 | 212 | #define CONFIG_SYS_SDRAM0_INITPLR14 0x00000000 |
| 209 | 213 | |
| ... | ... | @@ -212,11 +216,11 @@ |
| 212 | 216 | #define CONFIG_SYS_SDRAM0_RDCC 0x40000000 |
| 213 | 217 | #define CONFIG_SYS_SDRAM0_DLCR 0x00000000 |
| 214 | 218 | #define CONFIG_SYS_SDRAM0_CLKTR 0x40000000 |
| 215 | -#define CONFIG_SYS_SDRAM0_WRDTR 0x84000823 | |
| 219 | +#define CONFIG_SYS_SDRAM0_WRDTR 0x86000823 | |
| 216 | 220 | #define CONFIG_SYS_SDRAM0_SDTR1 0x80201000 |
| 217 | 221 | #define CONFIG_SYS_SDRAM0_SDTR2 0x32204232 |
| 218 | 222 | #define CONFIG_SYS_SDRAM0_SDTR3 0x090C0D15 |
| 219 | -#define CONFIG_SYS_SDRAM0_MMODE 0x00000442 | |
| 223 | +#define CONFIG_SYS_SDRAM0_MMODE 0x00000452 | |
| 220 | 224 | #define CONFIG_SYS_SDRAM0_MEMODE 0x00000002 |
| 221 | 225 | |
| 222 | 226 | #define CONFIG_SYS_MBYTES_SDRAM 256 /* 256MB */ |