x86: crownbay: Enable Intel E1000 NIC support

We don't have driver for the Intel Topcliff PCH Gigabit Ethernet controller for now, so enable the Intle E1000 NIC support, which can be plugged into any PCIe slot on the Crown Bay board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>

x86: crownbay: Enable Intel E1000 NIC support
We don't have driver for the Intel Topcliff PCH Gigabit Ethernet controller for now, so enable the Intle E1000 NIC support, which can be plugged into any PCIe slot on the Crown Bay board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng · Simon Glass
1 parent adfe3b247a
Showing 2 changed files with 7 additions and 0 deletions Side-by-side Diff
board/intel/crownbay/crownbay.c
include/configs/crownbay.h
@@ -7,6 +7,7 @@
 #include <common.h>
 #include <asm/ibmpc.h>
 #include <asm/pnp_def.h>
+#include <netdev.h>
 #include <smsc_lpc47m.h>
  
 #define SERIAL_DEV PNP_DEV(0x2e, 4)
@@ -23,5 +24,10 @@
 void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
 {
 	return;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
 }
@@ -37,6 +37,7 @@
  
 #define CONFIG_SYS_EARLY_PCI_INIT
 #define CONFIG_PCI_PNP
+#define CONFIG_E1000
  
 #define CONFIG_STD_DEVICES_SETTINGS     "stdin=serial\0" \
 					"stdout=serial\0" \
...	...	@@ -7,6 +7,7 @@
7	7	#include <common.h>
8	8	#include <asm/ibmpc.h>
9	9	#include <asm/pnp_def.h>
	10	+#include <netdev.h>
10	11	#include <smsc_lpc47m.h>
11	12
12	13	#define SERIAL_DEV PNP_DEV(0x2e, 4)
...	...	@@ -23,5 +24,10 @@
23	24	void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
24	25	{
25	26	return;
	27	+}
	28	+
	29	+int board_eth_init(bd_t *bis)
	30	+{
	31	+ return pci_eth_init(bis);
26	32	}
...	...	@@ -37,6 +37,7 @@
37	37
38	38	#define CONFIG_SYS_EARLY_PCI_INIT
39	39	#define CONFIG_PCI_PNP
	40	+#define CONFIG_E1000
40	41
41	42	#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \
42	43	"stdout=serial\0" \